From afa6aa8b58de9ed30687291d8775e82d26430f3c Mon Sep 17 00:00:00 2001 From: arbee Date: Sat, 14 Apr 2018 22:01:33 -0400 Subject: sh4drc: UML implementations of FADD, FSUB, FMUL, and FDIV. [R. Belmont] --- src/devices/cpu/sh/sh.h | 17 ++ src/devices/cpu/sh/sh4.cpp | 578 +++++++++++++++++++++-------------------- src/devices/cpu/sh/sh4.h | 20 +- src/devices/cpu/sh/sh4comn.cpp | 50 ++-- src/devices/cpu/sh/sh4comn.h | 23 +- 5 files changed, 361 insertions(+), 327 deletions(-) diff --git a/src/devices/cpu/sh/sh.h b/src/devices/cpu/sh/sh.h index 6ff23a7c989..bc24786a0bb 100644 --- a/src/devices/cpu/sh/sh.h +++ b/src/devices/cpu/sh/sh.h @@ -139,6 +139,23 @@ public: uint32_t vbr; uint32_t m_delay; + + // SH3/4 additional DRC "near" state + uint32_t m_ppc; + uint32_t m_spc; + uint32_t m_ssr; + uint32_t m_rbnk[2][8]; + uint32_t m_sgr; + uint32_t m_fr[16]; + uint32_t m_xf[16]; + uint32_t m_cpu_off; + uint32_t m_pending_irq; + uint32_t m_test_irq; + uint32_t m_fpscr; + uint32_t m_fpul; + uint32_t m_dbr; + + int m_frt_input; }; internal_sh2_state *m_sh2_state; diff --git a/src/devices/cpu/sh/sh4.cpp b/src/devices/cpu/sh/sh4.cpp index ba411100e64..520354e8ba9 100644 --- a/src/devices/cpu/sh/sh4.cpp +++ b/src/devices/cpu/sh/sh4.cpp @@ -186,27 +186,27 @@ void sh4_base_device::LDTLB(const uint16_t opcode) #if 0 int sign_of(int n) { - return(m_fr[n] >> 31); + return(m_sh2_state->m_fr[n] >> 31); } void zero(int n, int sign) { if (sign == 0) - m_fr[n] = 0x00000000; + m_sh2_state->m_fr[n] = 0x00000000; else - m_fr[n] = 0x80000000; - if ((m_fpscr & PR) == 1) - m_fr[n + 1] = 0x00000000; + m_sh2_state->m_fr[n] = 0x80000000; + if ((m_sh2_state->m_fpscr & PR) == 1) + m_sh2_state->m_fr[n + 1] = 0x00000000; } int data_type_of(int n) { uint32_t abs; - abs = m_fr[n] & 0x7fffffff; - if ((m_fpscr & PR) == 0) { /* Single-precision */ + abs = m_sh2_state->m_fr[n] & 0x7fffffff; + if ((m_sh2_state->m_fpscr & PR) == 0) { /* Single-precision */ if (abs < 0x00800000) { - if (((m_fpscr & DN) == 1) || (abs == 0x00000000)) { + if (((m_sh2_state->m_fpscr & DN) == 1) || (abs == 0x00000000)) { if (sign_of(n) == 0) { zero(n, 0); return(SH4_FPU_PZERO); @@ -237,7 +237,7 @@ int data_type_of(int n) } else { /* Double-precision */ if (abs < 0x00100000) { - if (((m_fpscr & DN) == 1) || ((abs == 0x00000000) && (m_fr[n + 1] == 0x00000000))) { + if (((m_sh2_state->m_fpscr & DN) == 1) || ((abs == 0x00000000) && (m_sh2_state->m_fr[n + 1] == 0x00000000))) { if (sign_of(n) == 0) { zero(n, 0); return(SH4_FPU_PZERO); @@ -254,7 +254,7 @@ int data_type_of(int n) if (abs < 0x7ff00000) return(SH4_FPU_NORM); else - if ((abs == 0x7ff00000) && (m_fr[n + 1] == 0x00000000)) { + if ((abs == 0x7ff00000) && (m_sh2_state->m_fr[n + 1] == 0x00000000)) { if (sign_of(n) == 0) return(SH4_FPU_PINF); else @@ -475,14 +475,14 @@ inline void sh34_base_device::LDCMSR(const uint16_t opcode) /* RTE */ inline void sh34_base_device::RTE() { - m_sh2_state->m_delay = m_sh2_state->ea = m_spc; + m_sh2_state->m_delay = m_sh2_state->ea = m_sh2_state->m_spc; if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) sh4_syncronize_register_bank((m_sh2_state->sr & sRB) >> 29); - if ((m_ssr & sRB) != (m_sh2_state->sr & sRB)) - sh4_change_register_bank(m_ssr & sRB ? 1 : 0); + if ((m_sh2_state->m_ssr & sRB) != (m_sh2_state->sr & sRB)) + sh4_change_register_bank(m_sh2_state->m_ssr & sRB ? 1 : 0); - m_sh2_state->sr = m_ssr; + m_sh2_state->sr = m_sh2_state->m_ssr; m_sh2_state->icount--; sh4_exception_recompute(); } @@ -501,10 +501,10 @@ inline void sh34_base_device::TRAPA(uint32_t i) m_sh3internal_upper[SH3_TRA_ADDR] = imm << 2; } - m_ssr = m_sh2_state->sr; - m_spc = m_sh2_state->pc; + m_sh2_state->m_ssr = m_sh2_state->sr; + m_sh2_state->m_spc = m_sh2_state->pc; - m_sgr = m_sh2_state->r[15]; + m_sh2_state->m_sgr = m_sh2_state->r[15]; m_sh2_state->sr |= MD; if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) @@ -534,7 +534,7 @@ inline void sh34_base_device::STCRBANK(const uint16_t opcode) { uint32_t m = Rm; - m_sh2_state->r[Rn] = m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7]; + m_sh2_state->r[Rn] = m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7]; } /* STCMRBANK Rm_BANK,@-Rn */ @@ -544,7 +544,7 @@ inline void sh34_base_device::STCMRBANK(const uint16_t opcode) m_sh2_state->r[n] -= 4; m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7]); + WL(m_sh2_state->ea, m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7]); m_sh2_state->icount--; } @@ -555,7 +555,7 @@ inline void sh34_base_device::STCMSGR(const uint16_t opcode) m_sh2_state->r[n] -= 4; m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_sgr); + WL(m_sh2_state->ea, m_sh2_state->m_sgr); } /* STS.L FPUL,@-Rn */ @@ -565,7 +565,7 @@ inline void sh34_base_device::STSMFPUL(const uint16_t opcode) m_sh2_state->r[n] -= 4; m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_fpul); + WL(m_sh2_state->ea, m_sh2_state->m_fpul); } /* STS.L FPSCR,@-Rn */ @@ -575,7 +575,7 @@ inline void sh34_base_device::STSMFPSCR(const uint16_t opcode) m_sh2_state->r[n] -= 4; m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_fpscr & 0x003FFFFF); + WL(m_sh2_state->ea, m_sh2_state->m_fpscr & 0x003FFFFF); } /* STC.L DBR,@-Rn */ @@ -585,7 +585,7 @@ inline void sh34_base_device::STCMDBR(const uint16_t opcode) m_sh2_state->r[n] -= 4; m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_dbr); + WL(m_sh2_state->ea, m_sh2_state->m_dbr); } /* STC.L SSR,@-Rn */ @@ -595,7 +595,7 @@ inline void sh34_base_device::STCMSSR(const uint16_t opcode) m_sh2_state->r[n] -= 4; m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_ssr); + WL(m_sh2_state->ea, m_sh2_state->m_ssr); } /* STC.L SPC,@-Rn */ @@ -605,14 +605,14 @@ inline void sh34_base_device::STCMSPC(const uint16_t opcode) m_sh2_state->r[n] -= 4; m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_spc); + WL(m_sh2_state->ea, m_sh2_state->m_spc); } /* LDS.L @Rm+,FPUL */ inline void sh34_base_device::LDSMFPUL(const uint16_t opcode) { m_sh2_state->ea = m_sh2_state->r[Rn]; - m_fpul = RL(m_sh2_state->ea); + m_sh2_state->m_fpul = RL(m_sh2_state->ea); m_sh2_state->r[Rn] += 4; } @@ -621,26 +621,26 @@ inline void sh34_base_device::LDSMFPSCR(const uint16_t opcode) { uint32_t s; - s = m_fpscr; + s = m_sh2_state->m_fpscr; m_sh2_state->ea = m_sh2_state->r[Rn]; - m_fpscr = RL(m_sh2_state->ea); - m_fpscr &= 0x003FFFFF; + m_sh2_state->m_fpscr = RL(m_sh2_state->ea); + m_sh2_state->m_fpscr &= 0x003FFFFF; m_sh2_state->r[Rn] += 4; - if ((s & FR) != (m_fpscr & FR)) + if ((s & FR) != (m_sh2_state->m_fpscr & FR)) sh4_swap_fp_registers(); #ifdef LSB_FIRST - if ((s & PR) != (m_fpscr & PR)) + if ((s & PR) != (m_sh2_state->m_fpscr & PR)) sh4_swap_fp_couples(); #endif - m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; - m_fpu_pr = (m_fpscr & PR) ? 1 : 0; + m_fpu_sz = (m_sh2_state->m_fpscr & SZ) ? 1 : 0; + m_fpu_pr = (m_sh2_state->m_fpscr & PR) ? 1 : 0; } /* LDC.L @Rm+,DBR */ inline void sh34_base_device::LDCMDBR(const uint16_t opcode) { m_sh2_state->ea = m_sh2_state->r[Rn]; - m_dbr = RL(m_sh2_state->ea); + m_sh2_state->m_dbr = RL(m_sh2_state->ea); m_sh2_state->r[Rn] += 4; } @@ -650,7 +650,7 @@ inline void sh34_base_device::LDCMRBANK(const uint16_t opcode) uint32_t m = Rm; uint32_t n = Rn; m_sh2_state->ea = m_sh2_state->r[n]; - m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7] = RL(m_sh2_state->ea); + m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7] = RL(m_sh2_state->ea); m_sh2_state->r[n] += 4; } @@ -658,7 +658,7 @@ inline void sh34_base_device::LDCMRBANK(const uint16_t opcode) inline void sh34_base_device::LDCMSSR(const uint16_t opcode) { m_sh2_state->ea = m_sh2_state->r[Rn]; - m_ssr = RL(m_sh2_state->ea); + m_sh2_state->m_ssr = RL(m_sh2_state->ea); m_sh2_state->r[Rn] += 4; } @@ -666,14 +666,14 @@ inline void sh34_base_device::LDCMSSR(const uint16_t opcode) inline void sh34_base_device::LDCMSPC(const uint16_t opcode) { m_sh2_state->ea = m_sh2_state->r[Rn]; - m_spc = RL(m_sh2_state->ea); + m_sh2_state->m_spc = RL(m_sh2_state->ea); m_sh2_state->r[Rn] += 4; } /* LDS Rm,FPUL */ inline void sh34_base_device::LDSFPUL(const uint16_t opcode) { - m_fpul = m_sh2_state->r[Rn]; + m_sh2_state->m_fpul = m_sh2_state->r[Rn]; } /* LDS Rm,FPSCR */ @@ -681,59 +681,59 @@ inline void sh34_base_device::LDSFPSCR(const uint16_t opcode) { uint32_t s; - s = m_fpscr; - m_fpscr = m_sh2_state->r[Rn] & 0x003FFFFF; - if ((s & FR) != (m_fpscr & FR)) + s = m_sh2_state->m_fpscr; + m_sh2_state->m_fpscr = m_sh2_state->r[Rn] & 0x003FFFFF; + if ((s & FR) != (m_sh2_state->m_fpscr & FR)) sh4_swap_fp_registers(); #ifdef LSB_FIRST - if ((s & PR) != (m_fpscr & PR)) + if ((s & PR) != (m_sh2_state->m_fpscr & PR)) sh4_swap_fp_couples(); #endif - m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; - m_fpu_pr = (m_fpscr & PR) ? 1 : 0; + m_fpu_sz = (m_sh2_state->m_fpscr & SZ) ? 1 : 0; + m_fpu_pr = (m_sh2_state->m_fpscr & PR) ? 1 : 0; } /* LDC Rm,DBR */ inline void sh34_base_device::LDCDBR(const uint16_t opcode) { - m_dbr = m_sh2_state->r[Rn]; + m_sh2_state->m_dbr = m_sh2_state->r[Rn]; } /* STC SSR,Rn */ inline void sh34_base_device::STCSSR(const uint16_t opcode) { - m_sh2_state->r[Rn] = m_ssr; + m_sh2_state->r[Rn] = m_sh2_state->m_ssr; } /* STC SPC,Rn */ inline void sh34_base_device::STCSPC(const uint16_t opcode) { - m_sh2_state->r[Rn] = m_spc; + m_sh2_state->r[Rn] = m_sh2_state->m_spc; } /* STC SGR,Rn */ inline void sh34_base_device::STCSGR(const uint16_t opcode) { - m_sh2_state->r[Rn] = m_sgr; + m_sh2_state->r[Rn] = m_sh2_state->m_sgr; } /* STS FPUL,Rn */ inline void sh34_base_device::STSFPUL(const uint16_t opcode) { - m_sh2_state->r[Rn] = m_fpul; + m_sh2_state->r[Rn] = m_sh2_state->m_fpul; } /* STS FPSCR,Rn */ inline void sh34_base_device::STSFPSCR(const uint16_t opcode) { - m_sh2_state->r[Rn] = m_fpscr & 0x003FFFFF; + m_sh2_state->r[Rn] = m_sh2_state->m_fpscr & 0x003FFFFF; } /* STC DBR,Rn */ inline void sh34_base_device::STCDBR(const uint16_t opcode) { - m_sh2_state->r[Rn] = m_dbr; + m_sh2_state->r[Rn] = m_sh2_state->m_dbr; } /* SHAD Rm,Rn */ @@ -771,19 +771,19 @@ inline void sh34_base_device::LDCRBANK(const uint16_t opcode) { uint32_t m = Rm; - m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7] = m_sh2_state->r[Rn]; + m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7] = m_sh2_state->r[Rn]; } /* LDC Rm,SSR */ inline void sh34_base_device::LDCSSR(const uint16_t opcode) { - m_ssr = m_sh2_state->r[Rn]; + m_sh2_state->m_ssr = m_sh2_state->r[Rn]; } /* LDC Rm,SPC */ inline void sh34_base_device::LDCSPC(const uint16_t opcode) { - m_spc = m_sh2_state->r[Rn]; + m_sh2_state->m_spc = m_sh2_state->r[Rn]; } /* PREF @Rn */ @@ -862,9 +862,9 @@ inline void sh34_base_device::FMOVMRIFR(const uint16_t opcode) n ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[m]; - m_xf[n] = RL(m_sh2_state->ea); + m_sh2_state->m_xf[n] = RL(m_sh2_state->ea); m_sh2_state->r[m] += 4; - m_xf[n ^ 1] = RL(m_sh2_state->ea + 4); + m_sh2_state->m_xf[n ^ 1] = RL(m_sh2_state->ea + 4); m_sh2_state->r[m] += 4; } else { @@ -872,9 +872,9 @@ inline void sh34_base_device::FMOVMRIFR(const uint16_t opcode) n ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[m]; - m_fr[n] = RL(m_sh2_state->ea); + m_sh2_state->m_fr[n] = RL(m_sh2_state->ea); m_sh2_state->r[m] += 4; - m_fr[n ^ 1] = RL(m_sh2_state->ea + 4); + m_sh2_state->m_fr[n ^ 1] = RL(m_sh2_state->ea + 4); m_sh2_state->r[m] += 4; } } @@ -883,7 +883,7 @@ inline void sh34_base_device::FMOVMRIFR(const uint16_t opcode) #ifdef LSB_FIRST n ^= m_fpu_pr; #endif - m_fr[n] = RL(m_sh2_state->ea); + m_sh2_state->m_fr[n] = RL(m_sh2_state->ea); m_sh2_state->r[m] += 4; } } @@ -903,16 +903,16 @@ inline void sh34_base_device::FMOVFRMR(const uint16_t opcode) m ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_xf[m]); - WL(m_sh2_state->ea + 4, m_xf[m ^ 1]); + WL(m_sh2_state->ea, m_sh2_state->m_xf[m]); + WL(m_sh2_state->ea + 4, m_sh2_state->m_xf[m ^ 1]); } else { #ifdef LSB_FIRST m ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_fr[m]); - WL(m_sh2_state->ea + 4, m_fr[m ^ 1]); + WL(m_sh2_state->ea, m_sh2_state->m_fr[m]); + WL(m_sh2_state->ea + 4, m_sh2_state->m_fr[m ^ 1]); } } else { /* SZ = 0 */ @@ -920,7 +920,7 @@ inline void sh34_base_device::FMOVFRMR(const uint16_t opcode) #ifdef LSB_FIRST m ^= m_fpu_pr; #endif - WL(m_sh2_state->ea, m_fr[m]); + WL(m_sh2_state->ea, m_sh2_state->m_fr[m]); } } @@ -940,8 +940,8 @@ inline void sh34_base_device::FMOVFRMDR(const uint16_t opcode) #endif m_sh2_state->r[n] -= 8; m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_xf[m]); - WL(m_sh2_state->ea + 4, m_xf[m ^ 1]); + WL(m_sh2_state->ea, m_sh2_state->m_xf[m]); + WL(m_sh2_state->ea + 4, m_sh2_state->m_xf[m ^ 1]); } else { #ifdef LSB_FIRST @@ -949,8 +949,8 @@ inline void sh34_base_device::FMOVFRMDR(const uint16_t opcode) #endif m_sh2_state->r[n] -= 8; m_sh2_state->ea = m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_fr[m]); - WL(m_sh2_state->ea + 4, m_fr[m ^ 1]); + WL(m_sh2_state->ea, m_sh2_state->m_fr[m]); + WL(m_sh2_state->ea + 4, m_sh2_state->m_fr[m ^ 1]); } } else { /* SZ = 0 */ @@ -959,7 +959,7 @@ inline void sh34_base_device::FMOVFRMDR(const uint16_t opcode) #ifdef LSB_FIRST m ^= m_fpu_pr; #endif - WL(m_sh2_state->ea, m_fr[m]); + WL(m_sh2_state->ea, m_sh2_state->m_fr[m]); } } @@ -978,16 +978,16 @@ inline void sh34_base_device::FMOVFRS0(const uint16_t opcode) m ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_xf[m]); - WL(m_sh2_state->ea + 4, m_xf[m ^ 1]); + WL(m_sh2_state->ea, m_sh2_state->m_xf[m]); + WL(m_sh2_state->ea + 4, m_sh2_state->m_xf[m ^ 1]); } else { #ifdef LSB_FIRST m ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[n]; - WL(m_sh2_state->ea, m_fr[m]); - WL(m_sh2_state->ea + 4, m_fr[m ^ 1]); + WL(m_sh2_state->ea, m_sh2_state->m_fr[m]); + WL(m_sh2_state->ea + 4, m_sh2_state->m_fr[m ^ 1]); } } else { /* SZ = 0 */ @@ -995,7 +995,7 @@ inline void sh34_base_device::FMOVFRS0(const uint16_t opcode) #ifdef LSB_FIRST m ^= m_fpu_pr; #endif - WL(m_sh2_state->ea, m_fr[m]); + WL(m_sh2_state->ea, m_sh2_state->m_fr[m]); } } @@ -1014,16 +1014,16 @@ inline void sh34_base_device::FMOVS0FR(const uint16_t opcode) n ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[m]; - m_xf[n] = RL(m_sh2_state->ea); - m_xf[n ^ 1] = RL(m_sh2_state->ea + 4); + m_sh2_state->m_xf[n] = RL(m_sh2_state->ea); + m_sh2_state->m_xf[n ^ 1] = RL(m_sh2_state->ea + 4); } else { #ifdef LSB_FIRST n ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[m]; - m_fr[n] = RL(m_sh2_state->ea); - m_fr[n ^ 1] = RL(m_sh2_state->ea + 4); + m_sh2_state->m_fr[n] = RL(m_sh2_state->ea); + m_sh2_state->m_fr[n ^ 1] = RL(m_sh2_state->ea + 4); } } else { /* SZ = 0 */ @@ -1031,7 +1031,7 @@ inline void sh34_base_device::FMOVS0FR(const uint16_t opcode) #ifdef LSB_FIRST n ^= m_fpu_pr; #endif - m_fr[n] = RL(m_sh2_state->ea); + m_sh2_state->m_fr[n] = RL(m_sh2_state->ea); } } @@ -1051,16 +1051,16 @@ inline void sh34_base_device::FMOVMRFR(const uint16_t opcode) n ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[m]; - m_xf[n] = RL(m_sh2_state->ea); - m_xf[n ^ 1] = RL(m_sh2_state->ea + 4); + m_sh2_state->m_xf[n] = RL(m_sh2_state->ea); + m_sh2_state->m_xf[n ^ 1] = RL(m_sh2_state->ea + 4); } else { #ifdef LSB_FIRST n ^= m_fpu_pr; #endif m_sh2_state->ea = m_sh2_state->r[m]; - m_fr[n] = RL(m_sh2_state->ea); - m_fr[n ^ 1] = RL(m_sh2_state->ea + 4); + m_sh2_state->m_fr[n] = RL(m_sh2_state->ea); + m_sh2_state->m_fr[n ^ 1] = RL(m_sh2_state->ea + 4); } } else { /* SZ = 0 */ @@ -1068,7 +1068,7 @@ inline void sh34_base_device::FMOVMRFR(const uint16_t opcode) #ifdef LSB_FIRST n ^= m_fpu_pr; #endif - m_fr[n] = RL(m_sh2_state->ea); + m_sh2_state->m_fr[n] = RL(m_sh2_state->ea); } } @@ -1086,27 +1086,27 @@ inline void sh34_base_device::FMOVFR(const uint16_t opcode) n ^= m_fpu_pr; m ^= m_fpu_pr; #endif - m_fr[n] = m_fr[m]; + m_sh2_state->m_fr[n] = m_sh2_state->m_fr[m]; } else { /* SZ = 1 */ if (m & 1) { if (n & 1) { - m_xf[n & 14] = m_xf[m & 14]; - m_xf[n | 1] = m_xf[m | 1]; + m_sh2_state->m_xf[n & 14] = m_sh2_state->m_xf[m & 14]; + m_sh2_state->m_xf[n | 1] = m_sh2_state->m_xf[m | 1]; } else { - m_fr[n] = m_xf[m & 14]; - m_fr[n | 1] = m_xf[m | 1]; + m_sh2_state->m_fr[n] = m_sh2_state->m_xf[m & 14]; + m_sh2_state->m_fr[n | 1] = m_sh2_state->m_xf[m | 1]; } } else { if (n & 1) { - m_xf[n & 14] = m_fr[m]; - m_xf[n | 1] = m_fr[m | 1]; // (a&14)+1 -> a|1 + m_sh2_state->m_xf[n & 14] = m_sh2_state->m_fr[m]; + m_sh2_state->m_xf[n | 1] = m_sh2_state->m_fr[m | 1]; // (a&14)+1 -> a|1 } else { - m_fr[n] = m_fr[m]; - m_fr[n | 1] = m_fr[m | 1]; + m_sh2_state->m_fr[n] = m_sh2_state->m_fr[m]; + m_sh2_state->m_fr[n | 1] = m_sh2_state->m_fr[m | 1]; } } } @@ -1116,9 +1116,9 @@ inline void sh34_base_device::FMOVFR(const uint16_t opcode) inline void sh34_base_device::FLDI1(const uint16_t opcode) { #ifdef LSB_FIRST - m_fr[Rn ^ m_fpu_pr] = 0x3F800000; + m_sh2_state->m_fr[Rn ^ m_fpu_pr] = 0x3F800000; #else - m_fr[Rn] = 0x3F800000; + m_sh2_state->m_fr[Rn] = 0x3F800000; #endif } @@ -1126,9 +1126,9 @@ inline void sh34_base_device::FLDI1(const uint16_t opcode) inline void sh34_base_device::FLDI0(const uint16_t opcode) { #ifdef LSB_FIRST - m_fr[Rn ^ m_fpu_pr] = 0; + m_sh2_state->m_fr[Rn ^ m_fpu_pr] = 0; #else - m_fr[Rn] = 0; + m_sh2_state->m_fr[Rn] = 0; #endif } @@ -1136,9 +1136,9 @@ inline void sh34_base_device::FLDI0(const uint16_t opcode) inline void sh34_base_device::FLDS(const uint16_t opcode) { #ifdef LSB_FIRST - m_fpul = m_fr[Rn ^ m_fpu_pr]; + m_sh2_state->m_fpul = m_sh2_state->m_fr[Rn ^ m_fpu_pr]; #else - m_fpul = m_fr[Rn]; + m_sh2_state->m_fpul = m_sh2_state->m_fr[Rn]; #endif } @@ -1146,24 +1146,24 @@ inline void sh34_base_device::FLDS(const uint16_t opcode) inline void sh34_base_device::FSTS(const uint16_t opcode) { #ifdef LSB_FIRST - m_fr[Rn ^ m_fpu_pr] = m_fpul; + m_sh2_state->m_fr[Rn ^ m_fpu_pr] = m_sh2_state->m_fpul; #else - m_fr[Rn] = m_fpul; + m_sh2_state->m_fr[Rn] = m_sh2_state->m_fpul; #endif } /* FRCHG 1111101111111101 */ void sh34_base_device::FRCHG() { - m_fpscr ^= FR; + m_sh2_state->m_fpscr ^= FR; sh4_swap_fp_registers(); } /* FSCHG 1111001111111101 */ void sh34_base_device::FSCHG() { - m_fpscr ^= SZ; - m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; + m_sh2_state->m_fpscr ^= SZ; + m_fpu_sz = (m_sh2_state->m_fpscr & SZ) ? 1 : 0; } /* FTRC FRm,FPUL PR=0 1111mmmm00111101 */ @@ -1177,11 +1177,11 @@ inline void sh34_base_device::FTRC(const uint16_t opcode) fatalerror("SH-4: FTRC opcode used with n %d", n); n = n & 14; - *((int32_t *)&m_fpul) = (int32_t)FP_RFD(n); + *((int32_t *)&m_sh2_state->m_fpul) = (int32_t)FP_RFD(n); } else { /* PR = 0 */ - /* read m_fr[n] as float -> truncate -> fpul(32) */ - *((int32_t *)&m_fpul) = (int32_t)FP_RFS(n); + /* read m_sh2_state->m_fr[n] as float -> truncate -> fpul(32) */ + *((int32_t *)&m_sh2_state->m_fpul) = (int32_t)FP_RFS(n); } } @@ -1196,10 +1196,10 @@ inline void sh34_base_device::FLOAT(const uint16_t opcode) fatalerror("SH-4: FLOAT opcode used with n %d", n); n = n & 14; - FP_RFD(n) = (double)*((int32_t *)&m_fpul); + FP_RFD(n) = (double)*((int32_t *)&m_sh2_state->m_fpul); } else { /* PR = 0 */ - FP_RFS(n) = (float)*((int32_t *)&m_fpul); + FP_RFS(n) = (float)*((int32_t *)&m_sh2_state->m_fpul); } } @@ -1226,14 +1226,14 @@ inline void sh34_base_device::FABS(const uint16_t opcode) if (m_fpu_pr) { /* PR = 1 */ #ifdef LSB_FIRST n = n | 1; // n & 14 + 1 - m_fr[n] = m_fr[n] & 0x7fffffff; + m_sh2_state->m_fr[n] = m_sh2_state->m_fr[n] & 0x7fffffff; #else n = n & 14; - m_fr[n] = m_fr[n] & 0x7fffffff; + m_sh2_state->m_fr[n] = m_sh2_state->m_fr[n] & 0x7fffffff; #endif } else { /* PR = 0 */ - m_fr[n] = m_fr[n] & 0x7fffffff; + m_sh2_state->m_fr[n] = m_sh2_state->m_fr[n] & 0x7fffffff; } } @@ -1288,9 +1288,9 @@ inline void sh34_base_device::FCNVDS(const uint16_t opcode) if (m_fpu_pr) { /* PR = 1 */ n = n & 14; - if (m_fpscr & RM) - m_fr[n | NATIVE_ENDIAN_VALUE_LE_BE(0, 1)] &= 0xe0000000; /* round toward zero*/ - *((float *)&m_fpul) = (float)FP_RFD(n); + if (m_sh2_state->m_fpscr & RM) + m_sh2_state->m_fr[n | NATIVE_ENDIAN_VALUE_LE_BE(0, 1)] &= 0xe0000000; /* round toward zero*/ + *((float *)&m_sh2_state->m_fpul) = (float)FP_RFD(n); } } @@ -1301,7 +1301,7 @@ inline void sh34_base_device::FCNVSD(const uint16_t opcode) if (m_fpu_pr) { /* PR = 1 */ n = n & 14; - FP_RFD(n) = (double)*((float *)&m_fpul); + FP_RFD(n) = (double)*((float *)&m_sh2_state->m_fpul); } } @@ -1420,7 +1420,7 @@ void sh34_base_device::FSSCA(const uint16_t opcode) float angle; - angle = (((float)(m_fpul & 0xFFFF)) / 65536.0f) * 2.0f * (float)M_PI; + angle = (((float)(m_sh2_state->m_fpul & 0xFFFF)) / 65536.0f) * 2.0f * (float)M_PI; FP_RFS(n) = sinf(angle); FP_RFS(n + 1) = cosf(angle); } @@ -1521,24 +1521,24 @@ inline void sh34_base_device::op1111_0x13(uint16_t opcode) void sh34_base_device::device_reset() { - m_spc = 0; + m_sh2_state->m_spc = 0; m_sh2_state->pr = 0; m_sh2_state->sr = 0; - m_ssr = 0; + m_sh2_state->m_ssr = 0; m_sh2_state->gbr = 0; m_sh2_state->vbr = 0; m_sh2_state->mach = 0; m_sh2_state->macl = 0; memset(m_sh2_state->r, 0, sizeof(m_sh2_state->r)); - memset(m_rbnk, 0, sizeof(m_rbnk)); - m_sgr = 0; - memset(m_fr, 0, sizeof(m_fr)); - memset(m_xf, 0, sizeof(m_xf)); + memset(m_sh2_state->m_rbnk, 0, sizeof(m_sh2_state->m_rbnk)); + m_sh2_state->m_sgr = 0; + memset(m_sh2_state->m_fr, 0, sizeof(m_sh2_state->m_fr)); + memset(m_sh2_state->m_xf, 0, sizeof(m_sh2_state->m_xf)); m_sh2_state->ea = 0; m_sh2_state->m_delay = 0; - m_cpu_off = 0; - m_pending_irq = 0; - m_test_irq = 0; + m_sh2_state->m_cpu_off = 0; + m_sh2_state->m_pending_irq = 0; + m_sh2_state->m_test_irq = 0; memset(m_exception_priority, 0, sizeof(m_exception_priority)); memset(m_exception_requesting, 0, sizeof(m_exception_requesting)); memset(m_m, 0, sizeof(m_m)); @@ -1577,7 +1577,7 @@ void sh34_base_device::device_reset() m_SH4_DMATCR3 = 0; m_SH4_DMAOR = 0; m_nmi_line_state = 0; - m_frt_input = 0; + m_sh2_state->m_frt_input = 0; m_internal_irq_vector = 0; m_refresh_timer_base = 0; memset(m_dma_timer_active, 0, sizeof(m_dma_timer_active)); @@ -1598,14 +1598,14 @@ void sh34_base_device::device_reset() m_rtc_timer->adjust(attotime::from_hz(128)); m_sh2_state->pc = 0xa0000000; - m_ppc = m_sh2_state->pc & SH34_AM; + m_sh2_state->m_ppc = m_sh2_state->pc & SH34_AM; m_sh2_state->r[15] = RL(4); m_sh2_state->sr = 0x700000f0; - m_fpscr = 0x00040001; - m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; - m_fpu_pr = (m_fpscr & PR) ? 1 : 0; - m_fpul = 0; - m_dbr = 0; + m_sh2_state->m_fpscr = 0x00040001; + m_fpu_sz = (m_sh2_state->m_fpscr & SZ) ? 1 : 0; + m_fpu_pr = (m_sh2_state->m_fpscr & PR) ? 1 : 0; + m_sh2_state->m_fpul = 0; + m_sh2_state->m_dbr = 0; m_internal_irq_level = -1; m_irln = 15; @@ -1871,7 +1871,7 @@ void sh34_base_device::execute_run() return; } - if (m_cpu_off) + if (m_sh2_state->m_cpu_off) { m_sh2_state->icount = 0; return; @@ -1879,7 +1879,7 @@ void sh34_base_device::execute_run() do { - m_ppc = m_sh2_state->pc & SH34_AM; + m_sh2_state->m_ppc = m_sh2_state->pc & SH34_AM; debugger_instruction_hook(m_sh2_state->pc & SH34_AM); uint16_t opcode; @@ -1897,7 +1897,7 @@ void sh34_base_device::execute_run() execute_one(opcode); - if (m_test_irq && !m_sh2_state->m_delay) + if (m_sh2_state->m_test_irq && !m_sh2_state->m_delay) { sh4_check_pending_irq("mame_sh4_execute"); } @@ -1914,7 +1914,7 @@ void sh3be_device::execute_run() return; } - if (m_cpu_off) + if (m_sh2_state->m_cpu_off) { m_sh2_state->icount = 0; return; @@ -1922,7 +1922,7 @@ void sh3be_device::execute_run() do { - m_ppc = m_sh2_state->pc & SH34_AM; + m_sh2_state->m_ppc = m_sh2_state->pc & SH34_AM; debugger_instruction_hook(m_sh2_state->pc & SH34_AM); const uint16_t opcode = m_direct->read_word(m_sh2_state->pc & SH34_AM, WORD_XOR_LE(6)); @@ -1937,7 +1937,7 @@ void sh3be_device::execute_run() execute_one(opcode); - if (m_test_irq && !m_sh2_state->m_delay) + if (m_sh2_state->m_test_irq && !m_sh2_state->m_delay) { sh4_check_pending_irq("mame_sh4_execute"); } @@ -1954,7 +1954,7 @@ void sh4be_device::execute_run() return; } - if (m_cpu_off) + if (m_sh2_state->m_cpu_off) { m_sh2_state->icount = 0; return; @@ -1962,7 +1962,7 @@ void sh4be_device::execute_run() do { - m_ppc = m_sh2_state->pc & SH34_AM; + m_sh2_state->m_ppc = m_sh2_state->pc & SH34_AM; debugger_instruction_hook(m_sh2_state->pc & SH34_AM); const uint16_t opcode = m_direct->read_word(m_sh2_state->pc & SH34_AM, WORD_XOR_LE(6)); @@ -1977,7 +1977,7 @@ void sh4be_device::execute_run() execute_one(opcode); - if (m_test_irq && !m_sh2_state->m_delay) + if (m_sh2_state->m_test_irq && !m_sh2_state->m_delay) { sh4_check_pending_irq("mame_sh4_execute"); } @@ -2059,22 +2059,22 @@ void sh34_base_device::device_start() m_direct = m_program->direct<0>(); sh4_default_exception_priorities(); m_irln = 15; - m_test_irq = 0; - - - save_item(NAME(m_spc)); - save_item(NAME(m_ssr)); - save_item(NAME(m_sgr)); - save_item(NAME(m_fpscr)); - save_item(NAME(m_rbnk)); - save_item(NAME(m_fr)); - save_item(NAME(m_xf)); - - save_item(NAME(m_cpu_off)); - save_item(NAME(m_pending_irq)); - save_item(NAME(m_test_irq)); - save_item(NAME(m_fpul)); - save_item(NAME(m_dbr)); + m_sh2_state->m_test_irq = 0; + + + save_item(NAME(m_sh2_state->m_spc)); + save_item(NAME(m_sh2_state->m_ssr)); + save_item(NAME(m_sh2_state->m_sgr)); + save_item(NAME(m_sh2_state->m_fpscr)); + save_item(NAME(m_sh2_state->m_rbnk)); + save_item(NAME(m_sh2_state->m_fr)); + save_item(NAME(m_sh2_state->m_xf)); + + save_item(NAME(m_sh2_state->m_cpu_off)); + save_item(NAME(m_sh2_state->m_pending_irq)); + save_item(NAME(m_sh2_state->m_test_irq)); + save_item(NAME(m_sh2_state->m_fpul)); + save_item(NAME(m_sh2_state->m_dbr)); save_item(NAME(m_exception_priority)); save_item(NAME(m_exception_requesting)); save_item(NAME(m_irq_line_state)); @@ -2108,7 +2108,7 @@ void sh34_base_device::device_start() save_item(NAME(m_SH4_DMAOR)); save_item(NAME(m_nmi_line_state)); - save_item(NAME(m_frt_input)); + save_item(NAME(m_sh2_state->m_frt_input)); save_item(NAME(m_irln)); save_item(NAME(m_internal_irq_level)); save_item(NAME(m_internal_irq_vector)); @@ -2136,29 +2136,29 @@ void sh34_base_device::device_start() // Debugger state - state_add(SH4_DBR, "DBR", m_dbr).formatstr("%08X"); - - state_add(SH4_R0_BK0, "R0 BK 0", m_rbnk[0][0]).formatstr("%08X"); - state_add(SH4_R1_BK0, "R1 BK 0", m_rbnk[0][1]).formatstr("%08X"); - state_add(SH4_R2_BK0, "R2 BK 0", m_rbnk[0][2]).formatstr("%08X"); - state_add(SH4_R3_BK0, "R3 BK 0", m_rbnk[0][3]).formatstr("%08X"); - state_add(SH4_R4_BK0, "R4 BK 0", m_rbnk[0][4]).formatstr("%08X"); - state_add(SH4_R5_BK0, "R5 BK 0", m_rbnk[0][5]).formatstr("%08X"); - state_add(SH4_R6_BK0, "R6 BK 0", m_rbnk[0][6]).formatstr("%08X"); - state_add(SH4_R7_BK0, "R7 BK 0", m_rbnk[0][7]).formatstr("%08X"); - state_add(SH4_R0_BK1, "R0 BK 1", m_rbnk[1][0]).formatstr("%08X"); - state_add(SH4_R1_BK1, "R1 BK 1", m_rbnk[1][1]).formatstr("%08X"); - state_add(SH4_R2_BK1, "R2 BK 1", m_rbnk[1][2]).formatstr("%08X"); - state_add(SH4_R3_BK1, "R3 BK 1", m_rbnk[1][3]).formatstr("%08X"); - state_add(SH4_R4_BK1, "R4 BK 1", m_rbnk[1][4]).formatstr("%08X"); - state_add(SH4_R5_BK1, "R5 BK 1", m_rbnk[1][5]).formatstr("%08X"); - state_add(SH4_R6_BK1, "R6 BK 1", m_rbnk[1][6]).formatstr("%08X"); - state_add(SH4_R7_BK1, "R7 BK 1", m_rbnk[1][7]).formatstr("%08X"); - state_add(SH4_SPC, "SPC", m_spc).formatstr("%08X"); - state_add(SH4_SSR, "SSR", m_ssr).formatstr("%08X"); - state_add(SH4_SGR, "SGR", m_sgr).formatstr("%08X"); - state_add(SH4_FPSCR, "FPSCR", m_fpscr).formatstr("%08X"); - state_add(SH4_FPUL, "FPUL", m_fpul).formatstr("%08X"); + state_add(SH4_DBR, "DBR", m_sh2_state->m_dbr).formatstr("%08X"); + + state_add(SH4_R0_BK0, "R0 BK 0", m_sh2_state->m_rbnk[0][0]).formatstr("%08X"); + state_add(SH4_R1_BK0, "R1 BK 0", m_sh2_state->m_rbnk[0][1]).formatstr("%08X"); + state_add(SH4_R2_BK0, "R2 BK 0", m_sh2_state->m_rbnk[0][2]).formatstr("%08X"); + state_add(SH4_R3_BK0, "R3 BK 0", m_sh2_state->m_rbnk[0][3]).formatstr("%08X"); + state_add(SH4_R4_BK0, "R4 BK 0", m_sh2_state->m_rbnk[0][4]).formatstr("%08X"); + state_add(SH4_R5_BK0, "R5 BK 0", m_sh2_state->m_rbnk[0][5]).formatstr("%08X"); + state_add(SH4_R6_BK0, "R6 BK 0", m_sh2_state->m_rbnk[0][6]).formatstr("%08X"); + state_add(SH4_R7_BK0, "R7 BK 0", m_sh2_state->m_rbnk[0][7]).formatstr("%08X"); + state_add(SH4_R0_BK1, "R0 BK 1", m_sh2_state->m_rbnk[1][0]).formatstr("%08X"); + state_add(SH4_R1_BK1, "R1 BK 1", m_sh2_state->m_rbnk[1][1]).formatstr("%08X"); + state_add(SH4_R2_BK1, "R2 BK 1", m_sh2_state->m_rbnk[1][2]).formatstr("%08X"); + state_add(SH4_R3_BK1, "R3 BK 1", m_sh2_state->m_rbnk[1][3]).formatstr("%08X"); + state_add(SH4_R4_BK1, "R4 BK 1", m_sh2_state->m_rbnk[1][4]).formatstr("%08X"); + state_add(SH4_R5_BK1, "R5 BK 1", m_sh2_state->m_rbnk[1][5]).formatstr("%08X"); + state_add(SH4_R6_BK1, "R6 BK 1", m_sh2_state->m_rbnk[1][6]).formatstr("%08X"); + state_add(SH4_R7_BK1, "R7 BK 1", m_sh2_state->m_rbnk[1][7]).formatstr("%08X"); + state_add(SH4_SPC, "SPC", m_sh2_state->m_spc).formatstr("%08X"); + state_add(SH4_SSR, "SSR", m_sh2_state->m_ssr).formatstr("%08X"); + state_add(SH4_SGR, "SGR", m_sh2_state->m_sgr).formatstr("%08X"); + state_add(SH4_FPSCR, "FPSCR", m_sh2_state->m_fpscr).formatstr("%08X"); + state_add(SH4_FPUL, "FPUL", m_sh2_state->m_fpul).formatstr("%08X"); state_add(SH4_FR0, "FR0", m_debugger_temp).callimport().formatstr("%25s"); state_add(SH4_FR1, "FR1", m_debugger_temp).callimport().formatstr("%25s"); @@ -2194,9 +2194,18 @@ void sh34_base_device::device_start() state_add(SH4_XF15, "XF15", m_debugger_temp).callimport().formatstr("%25s"); state_add(STATE_GENPC, "GENPC", m_debugger_temp).callimport().callexport().noshow(); - //state_add(STATE_GENPCBASE, "CURPC", m_ppc).noshow(); + //state_add(STATE_GENPCBASE, "CURPC", m_sh2_state->m_ppc).noshow(); state_add( STATE_GENPCBASE, "CURPC", m_sh2_state->pc ).callimport().noshow(); + for (int regnum = 0; regnum < 16; regnum++) + { + m_fs_regmap[regnum] = uml::mem(((float *)(m_sh2_state->m_fr+(regnum)))); + } + + for (int regnum = 0; regnum < 16; regnum+=2) + { + m_fd_regmap[regnum] = uml::mem(((double *)(m_sh2_state->m_fr+(regnum)))); + } drc_start(); } @@ -2223,131 +2232,131 @@ void sh34_base_device::state_import(const device_state_entry &entry) break; case SH4_FR0: - m_fr[0 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[0 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR1: - m_fr[1 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[1 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR2: - m_fr[2 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[2 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR3: - m_fr[3 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[3 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR4: - m_fr[4 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[4 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR5: - m_fr[5 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[5 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR6: - m_fr[6 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[6 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR7: - m_fr[7 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[7 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR8: - m_fr[8 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[8 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR9: - m_fr[9 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[9 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR10: - m_fr[10 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[10 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR11: - m_fr[11 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[11 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR12: - m_fr[12 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[12 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR13: - m_fr[13 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[13 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR14: - m_fr[14 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[14 ^ fpu_xor] = m_debugger_temp; break; case SH4_FR15: - m_fr[15 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_fr[15 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF0: - m_xf[0 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[0 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF1: - m_xf[1 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[1 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF2: - m_xf[2 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[2 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF3: - m_xf[3 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[3 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF4: - m_xf[4 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[4 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF5: - m_xf[5 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[5 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF6: - m_xf[6 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[6 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF7: - m_xf[7 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[7 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF8: - m_xf[8 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[8 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF9: - m_xf[9 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[9 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF10: - m_xf[10 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[10 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF11: - m_xf[11 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[11 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF12: - m_xf[12 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[12 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF13: - m_xf[13 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[13 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF14: - m_xf[14 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[14 ^ fpu_xor] = m_debugger_temp; break; case SH4_XF15: - m_xf[15 ^ fpu_xor] = m_debugger_temp; + m_sh2_state->m_xf[15 ^ fpu_xor] = m_debugger_temp; break; } } @@ -2386,131 +2395,131 @@ void sh34_base_device::state_string_export(const device_state_entry &entry, std: break; case SH4_FR0: - str = string_format("%08X %f", m_fr[0 ^ fpu_xor], (double)FP_RFS(0 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[0 ^ fpu_xor], (double)FP_RFS(0 ^ fpu_xor)); break; case SH4_FR1: - str = string_format("%08X %f", m_fr[1 ^ fpu_xor], (double)FP_RFS(1 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[1 ^ fpu_xor], (double)FP_RFS(1 ^ fpu_xor)); break; case SH4_FR2: - str = string_format("%08X %f", m_fr[2 ^ fpu_xor], (double)FP_RFS(2 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[2 ^ fpu_xor], (double)FP_RFS(2 ^ fpu_xor)); break; case SH4_FR3: - str = string_format("%08X %f", m_fr[3 ^ fpu_xor], (double)FP_RFS(3 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[3 ^ fpu_xor], (double)FP_RFS(3 ^ fpu_xor)); break; case SH4_FR4: - str = string_format("%08X %f", m_fr[4 ^ fpu_xor], (double)FP_RFS(4 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[4 ^ fpu_xor], (double)FP_RFS(4 ^ fpu_xor)); break; case SH4_FR5: - str = string_format("%08X %f", m_fr[5 ^ fpu_xor], (double)FP_RFS(5 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[5 ^ fpu_xor], (double)FP_RFS(5 ^ fpu_xor)); break; case SH4_FR6: - str = string_format("%08X %f", m_fr[6 ^ fpu_xor], (double)FP_RFS(6 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[6 ^ fpu_xor], (double)FP_RFS(6 ^ fpu_xor)); break; case SH4_FR7: - str = string_format("%08X %f", m_fr[7 ^ fpu_xor], (double)FP_RFS(7 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[7 ^ fpu_xor], (double)FP_RFS(7 ^ fpu_xor)); break; case SH4_FR8: - str = string_format("%08X %f", m_fr[8 ^ fpu_xor], (double)FP_RFS(8 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[8 ^ fpu_xor], (double)FP_RFS(8 ^ fpu_xor)); break; case SH4_FR9: - str = string_format("%08X %f", m_fr[9 ^ fpu_xor], (double)FP_RFS(9 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[9 ^ fpu_xor], (double)FP_RFS(9 ^ fpu_xor)); break; case SH4_FR10: - str = string_format("%08X %f", m_fr[10 ^ fpu_xor], (double)FP_RFS(10 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[10 ^ fpu_xor], (double)FP_RFS(10 ^ fpu_xor)); break; case SH4_FR11: - str = string_format("%08X %f", m_fr[11 ^ fpu_xor], (double)FP_RFS(11 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[11 ^ fpu_xor], (double)FP_RFS(11 ^ fpu_xor)); break; case SH4_FR12: - str = string_format("%08X %f", m_fr[12 ^ fpu_xor], (double)FP_RFS(12 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[12 ^ fpu_xor], (double)FP_RFS(12 ^ fpu_xor)); break; case SH4_FR13: - str = string_format("%08X %f", m_fr[13 ^ fpu_xor], (double)FP_RFS(13 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[13 ^ fpu_xor], (double)FP_RFS(13 ^ fpu_xor)); break; case SH4_FR14: - str = string_format("%08X %f", m_fr[14 ^ fpu_xor], (double)FP_RFS(14 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[14 ^ fpu_xor], (double)FP_RFS(14 ^ fpu_xor)); break; case SH4_FR15: - str = string_format("%08X %f", m_fr[15 ^ fpu_xor], (double)FP_RFS(15 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_fr[15 ^ fpu_xor], (double)FP_RFS(15 ^ fpu_xor)); break; case SH4_XF0: - str = string_format("%08X %f", m_xf[0 ^ fpu_xor], (double)FP_XFS(0 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[0 ^ fpu_xor], (double)FP_XFS(0 ^ fpu_xor)); break; case SH4_XF1: - str = string_format("%08X %f", m_xf[1 ^ fpu_xor], (double)FP_XFS(1 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[1 ^ fpu_xor], (double)FP_XFS(1 ^ fpu_xor)); break; case SH4_XF2: - str = string_format("%08X %f", m_xf[2 ^ fpu_xor], (double)FP_XFS(2 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[2 ^ fpu_xor], (double)FP_XFS(2 ^ fpu_xor)); break; case SH4_XF3: - str = string_format("%08X %f", m_xf[3 ^ fpu_xor], (double)FP_XFS(3 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[3 ^ fpu_xor], (double)FP_XFS(3 ^ fpu_xor)); break; case SH4_XF4: - str = string_format("%08X %f", m_xf[4 ^ fpu_xor], (double)FP_XFS(4 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[4 ^ fpu_xor], (double)FP_XFS(4 ^ fpu_xor)); break; case SH4_XF5: - str = string_format("%08X %f", m_xf[5 ^ fpu_xor], (double)FP_XFS(5 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[5 ^ fpu_xor], (double)FP_XFS(5 ^ fpu_xor)); break; case SH4_XF6: - str = string_format("%08X %f", m_xf[6 ^ fpu_xor], (double)FP_XFS(6 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[6 ^ fpu_xor], (double)FP_XFS(6 ^ fpu_xor)); break; case SH4_XF7: - str = string_format("%08X %f", m_xf[7 ^ fpu_xor], (double)FP_XFS(7 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[7 ^ fpu_xor], (double)FP_XFS(7 ^ fpu_xor)); break; case SH4_XF8: - str = string_format("%08X %f", m_xf[8 ^ fpu_xor], (double)FP_XFS(8 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[8 ^ fpu_xor], (double)FP_XFS(8 ^ fpu_xor)); break; case SH4_XF9: - str = string_format("%08X %f", m_xf[9 ^ fpu_xor], (double)FP_XFS(9 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[9 ^ fpu_xor], (double)FP_XFS(9 ^ fpu_xor)); break; case SH4_XF10: - str = string_format("%08X %f", m_xf[10 ^ fpu_xor], (double)FP_XFS(10 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[10 ^ fpu_xor], (double)FP_XFS(10 ^ fpu_xor)); break; case SH4_XF11: - str = string_format("%08X %f", m_xf[11 ^ fpu_xor], (double)FP_XFS(11 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[11 ^ fpu_xor], (double)FP_XFS(11 ^ fpu_xor)); break; case SH4_XF12: - str = string_format("%08X %f", m_xf[12 ^ fpu_xor], (double)FP_XFS(12 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[12 ^ fpu_xor], (double)FP_XFS(12 ^ fpu_xor)); break; case SH4_XF13: - str = string_format("%08X %f", m_xf[13 ^ fpu_xor], (double)FP_XFS(13 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[13 ^ fpu_xor], (double)FP_XFS(13 ^ fpu_xor)); break; case SH4_XF14: - str = string_format("%08X %f", m_xf[14 ^ fpu_xor], (double)FP_XFS(14 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[14 ^ fpu_xor], (double)FP_XFS(14 ^ fpu_xor)); break; case SH4_XF15: - str = string_format("%08X %f", m_xf[15 ^ fpu_xor], (double)FP_XFS(15 ^ fpu_xor)); + str = string_format("%08X %f", m_sh2_state->m_xf[15 ^ fpu_xor], (double)FP_XFS(15 ^ fpu_xor)); break; } @@ -2570,7 +2579,7 @@ void sh3_device::init_drc_frontend() an exception if out -------------------------------------------------*/ -void sh34_base_device::func_CHECKIRQ() { if (m_test_irq) sh4_check_pending_irq("mame_sh4_execute"); } +void sh34_base_device::func_CHECKIRQ() { if (m_sh2_state->m_test_irq) sh4_check_pending_irq("mame_sh4_execute"); } static void cfunc_CHECKIRQ(void *param) { ((sh34_base_device *)param)->func_CHECKIRQ(); }; void sh34_base_device::generate_update_cycles(drcuml_block &block, compiler_state &compiler, uml::parameter param, bool allow_exception) @@ -3465,52 +3474,67 @@ bool sh34_base_device::generate_group_15(drcuml_block &block, compiler_state &co } return false; } - -void sh34_base_device::func_FADD() { FADD(m_sh2_state->arg0); } -static void cfunc_FADD(void *param) { ((sh34_base_device *)param)->func_FADD(); }; - bool sh34_base_device::generate_group_15_FADD(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc) { - save_fast_iregs(block); - UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]); - UML_CALLC(block, cfunc_FADD, this); - load_fast_iregs(block); + UML_TEST(block, m_fpu_pr, 0); + UML_JMPc(block, COND_Z, compiler.labelnum); + + UML_FDADD(block, FPD32(Rn), FPD32(Rn), FPD32(Rm)); + UML_JMP(block, compiler.labelnum+1); + + UML_LABEL(block, compiler.labelnum++); // labelnum: + UML_FSADD(block, FPS32(Rn), FPS32(Rn), FPS32(Rm)); + + UML_LABEL(block, compiler.labelnum++); // labelnum+1: + return true; } -void sh34_base_device::func_FSUB() { FSUB(m_sh2_state->arg0); } -static void cfunc_FSUB(void *param) { ((sh34_base_device *)param)->func_FSUB(); }; - bool sh34_base_device::generate_group_15_FSUB(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc) { - save_fast_iregs(block); - UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]); - UML_CALLC(block, cfunc_FSUB, this); - load_fast_iregs(block); + UML_TEST(block, m_fpu_pr, 0); + UML_JMPc(block, COND_Z, compiler.labelnum); + + UML_FDSUB(block, FPD32(Rn), FPD32(Rn), FPD32(Rm)); + UML_JMP(block, compiler.labelnum+1); + + UML_LABEL(block, compiler.labelnum++); // labelnum: + UML_FSSUB(block, FPS32(Rn), FPS32(Rn), FPS32(Rm)); + + UML_LABEL(block, compiler.labelnum++); // labelnum+1: + return true; } -void sh34_base_device::func_FMUL() { FMUL(m_sh2_state->arg0); } -static void cfunc_FMUL(void *param) { ((sh34_base_device *)param)->func_FMUL(); }; - bool sh34_base_device::generate_group_15_FMUL(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc) { - save_fast_iregs(block); - UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]); - UML_CALLC(block, cfunc_FMUL, this); - load_fast_iregs(block); + UML_TEST(block, m_fpu_pr, 0); + UML_JMPc(block, COND_Z, compiler.labelnum); + + UML_FDMUL(block, FPD32(Rn), FPD32(Rn), FPD32(Rm)); + UML_JMP(block, compiler.labelnum+1); + + UML_LABEL(block, compiler.labelnum++); // labelnum: + UML_FSMUL(block, FPS32(Rn), FPS32(Rn), FPS32(Rm)); + + UML_LABEL(block, compiler.labelnum++); // labelnum+1: + return true; } -void sh34_base_device::func_FDIV() { FDIV(m_sh2_state->arg0); } -static void cfunc_FDIV(void *param) { ((sh34_base_device *)param)->func_FDIV(); }; - bool sh34_base_device::generate_group_15_FDIV(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc) { - save_fast_iregs(block); - UML_MOV(block, mem(&m_sh2_state->arg0), desc->opptr.w[0]); - UML_CALLC(block, cfunc_FDIV, this); - load_fast_iregs(block); + UML_TEST(block, m_fpu_pr, 0); + UML_JMPc(block, COND_Z, compiler.labelnum); + + UML_FDDIV(block, FPD32(Rn), FPD32(Rn), FPD32(Rm)); + UML_JMP(block, compiler.labelnum+1); + + UML_LABEL(block, compiler.labelnum++); // labelnum: + UML_FSDIV(block, FPS32(Rn), FPS32(Rn), FPS32(Rm)); + + UML_LABEL(block, compiler.labelnum++); // labelnum+1: + return true; } diff --git a/src/devices/cpu/sh/sh4.h b/src/devices/cpu/sh/sh4.h index 0f504f9083b..a281676312f 100644 --- a/src/devices/cpu/sh/sh4.h +++ b/src/devices/cpu/sh/sh4.h @@ -240,6 +240,8 @@ public: void func_LDCMRBANK(); void func_PREFM(); void func_FADD(); + void func_FADD_spre(); + void func_FADD_spost(); void func_FSUB(); void func_FMUL(); void func_FDIV(); @@ -322,6 +324,9 @@ protected: address_space_config m_program_config; address_space_config m_io_config; + uml::parameter m_fs_regmap[16]; + uml::parameter m_fd_regmap[16]; + int c_md2; int c_md1; int c_md0; @@ -336,20 +341,6 @@ protected: // hack 1 = Naomi hack, hack 2 = Work in Progress implementation int m_mmuhack; - uint32_t m_ppc; - uint32_t m_spc; - uint32_t m_ssr; - uint32_t m_rbnk[2][8]; - uint32_t m_sgr; - uint32_t m_fr[16]; - uint32_t m_xf[16]; - uint32_t m_cpu_off; - uint32_t m_pending_irq; - uint32_t m_test_irq; - uint32_t m_fpscr; - uint32_t m_fpul; - uint32_t m_dbr; - uint32_t m_exception_priority[128]; int m_exception_requesting[128]; @@ -405,7 +396,6 @@ protected: int8_t m_nmi_line_state; - int m_frt_input; int m_irln; int m_internal_irq_level; int m_internal_irq_vector; diff --git a/src/devices/cpu/sh/sh4comn.cpp b/src/devices/cpu/sh/sh4comn.cpp index 1e7061c7d54..0cdc9b0b994 100644 --- a/src/devices/cpu/sh/sh4comn.cpp +++ b/src/devices/cpu/sh/sh4comn.cpp @@ -240,9 +240,9 @@ void sh34_base_device::sh4_swap_fp_registers() for (s = 0;s <= 15;s++) { - z = m_fr[s]; - m_fr[s] = m_xf[s]; - m_xf[s] = z; + z = m_sh2_state->m_fr[s]; + m_sh2_state->m_fr[s] = m_sh2_state->m_xf[s]; + m_sh2_state->m_xf[s] = z; } } @@ -253,12 +253,12 @@ void sh34_base_device::sh4_swap_fp_couples() for (s = 0;s <= 15;s = s+2) { - z = m_fr[s]; - m_fr[s] = m_fr[s + 1]; - m_fr[s + 1] = z; - z = m_xf[s]; - m_xf[s] = m_xf[s + 1]; - m_xf[s + 1] = z; + z = m_sh2_state->m_fr[s]; + m_sh2_state->m_fr[s] = m_sh2_state->m_fr[s + 1]; + m_sh2_state->m_fr[s + 1] = z; + z = m_sh2_state->m_xf[s]; + m_sh2_state->m_xf[s] = m_sh2_state->m_xf[s + 1]; + m_sh2_state->m_xf[s + 1] = z; } } @@ -271,16 +271,16 @@ void sh34_base_device::sh4_change_register_bank(int to) { for (s = 0;s < 8;s++) { - m_rbnk[0][s] = m_sh2_state->r[s]; - m_sh2_state->r[s] = m_rbnk[1][s]; + m_sh2_state->m_rbnk[0][s] = m_sh2_state->r[s]; + m_sh2_state->r[s] = m_sh2_state->m_rbnk[1][s]; } } else // 1 -> 0 { for (s = 0;s < 8;s++) { - m_rbnk[1][s] = m_sh2_state->r[s]; - m_sh2_state->r[s] = m_rbnk[0][s]; + m_sh2_state->m_rbnk[1][s] = m_sh2_state->r[s]; + m_sh2_state->r[s] = m_sh2_state->m_rbnk[0][s]; } } } @@ -291,7 +291,7 @@ void sh34_base_device::sh4_syncronize_register_bank(int to) for (s = 0;s < 8;s++) { - m_rbnk[to][s] = m_sh2_state->r[s]; + m_sh2_state->m_rbnk[to][s] = m_sh2_state->r[s]; } } @@ -315,8 +315,8 @@ void sh34_base_device::sh4_exception_recompute() // checks if there is any inter { int a,z; - m_test_irq = 0; - if ((!m_pending_irq) || ((m_sh2_state->sr & BL) && (m_exception_requesting[SH4_INTC_NMI] == 0))) + m_sh2_state->m_test_irq = 0; + if ((!m_sh2_state->m_pending_irq) || ((m_sh2_state->sr & BL) && (m_exception_requesting[SH4_INTC_NMI] == 0))) return; z = (m_sh2_state->sr >> 4) & 15; for (a=0;a <= SH4_INTC_ROVI;a++) @@ -328,7 +328,7 @@ void sh34_base_device::sh4_exception_recompute() // checks if there is any inter if (pri > z) { //logerror("will test\n"); - m_test_irq = 1; // will check for exception at end of instructions + m_sh2_state->m_test_irq = 1; // will check for exception at end of instructions break; } } @@ -342,7 +342,7 @@ void sh34_base_device::sh4_exception_request(int exception) // start requesting { //logerror("sh4_exception_request b\n"); m_exception_requesting[exception] = 1; - m_pending_irq++; + m_sh2_state->m_pending_irq++; sh4_exception_recompute(); } } @@ -352,7 +352,7 @@ void sh34_base_device::sh4_exception_unrequest(int exception) // stop requesting if (m_exception_requesting[exception]) { m_exception_requesting[exception] = 0; - m_pending_irq--; + m_sh2_state->m_pending_irq--; sh4_exception_recompute(); } } @@ -371,9 +371,9 @@ void sh34_base_device::sh4_exception_process(int exception, uint32_t vector) { sh4_exception_checkunrequest(exception); - m_spc = m_sh2_state->pc; - m_ssr = m_sh2_state->sr; - m_sgr = m_sh2_state->r[15]; + m_sh2_state->m_spc = m_sh2_state->pc; + m_sh2_state->m_ssr = m_sh2_state->sr; + m_sh2_state->m_sgr = m_sh2_state->r[15]; //printf("stored m_spc %08x m_ssr %08x m_sgr %08x\n", m_spc, m_ssr, m_sgr); @@ -1078,11 +1078,11 @@ void sh34_base_device::sh4_set_frt_input(int state) return; } - if(m_frt_input == state) { + if(m_sh2_state->m_frt_input == state) { return; } - m_frt_input = state; + m_sh2_state->m_frt_input = state; if (m_cpu_type == CPU_TYPE_SH4) { @@ -1218,7 +1218,7 @@ void sh34_base_device::execute_set_input(int irqline, int state) // set state of LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", tag(), m_irln)); } } - if (m_test_irq && (!m_sh2_state->m_delay)) + if (m_sh2_state->m_test_irq && (!m_sh2_state->m_delay)) sh4_check_pending_irq("sh4_set_irq_line"); } } diff --git a/src/devices/cpu/sh/sh4comn.h b/src/devices/cpu/sh/sh4comn.h index ded2e5645f1..d4faa421548 100644 --- a/src/devices/cpu/sh/sh4comn.h +++ b/src/devices/cpu/sh/sh4comn.h @@ -23,19 +23,22 @@ #define NMIPRI() EXPPRI(3,0,16,SH4_INTC_NMI) #define INTPRI(p,n) EXPPRI(4,2,p,n) -#define FP_RS(r) m_fr[(r)] // binary representation of single precision floating point register r -#define FP_RFS(r) *( (float *)(m_fr+(r)) ) // single precision floating point register r -#define FP_RFD(r) *( (double *)(m_fr+(r)) ) // double precision floating point register r -#define FP_XS(r) m_xf[(r)] // binary representation of extended single precision floating point register r -#define FP_XFS(r) *( (float *)(m_xf+(r)) ) // single precision extended floating point register r -#define FP_XFD(r) *( (double *)(m_xf+(r)) ) // double precision extended floating point register r +#define FP_RS(r) m_sh2_state->m_fr[(r)] // binary representation of single precision floating point register r +#define FP_RFS(r) *( (float *)(m_sh2_state->m_fr+(r)) ) // single precision floating point register r +#define FP_RFD(r) *( (double *)(m_sh2_state->m_fr+(r)) ) // double precision floating point register r +#define FP_XS(r) m_sh2_state->m_xf[(r)] // binary representation of extended single precision floating point register r +#define FP_XFS(r) *( (float *)(m_sh2_state->m_xf+(r)) ) // single precision extended floating point register r +#define FP_XFD(r) *( (double *)(m_sh2_state->m_xf+(r)) ) // double precision extended floating point register r #ifdef LSB_FIRST -#define FP_RS2(r) m_fr[(r) ^ m_fpu_pr] -#define FP_RFS2(r) *( (float *)(m_fr+((r) ^ m_fpu_pr)) ) -#define FP_XS2(r) m_xf[(r) ^ m_fpu_pr] -#define FP_XFS2(r) *( (float *)(m_xf+((r) ^ m_fpu_pr)) ) +#define FP_RS2(r) m_sh2_state->m_fr[(r) ^ m_sh2_state->m_fpu_pr] +#define FP_RFS2(r) *( (float *)(m_sh2_state->m_fr+((r) ^ m_sh2_state->m_fpu_pr)) ) +#define FP_XS2(r) m_sh2_state->m_xf[(r) ^ m_sh2_state->m_fpu_pr] +#define FP_XFS2(r) *( (float *)(m_sh2_state->m_xf+((r) ^ m_sh2_state->m_fpu_pr)) ) #endif +#define FPSCR mem(&m_sh2_state->m_fpscr) +#define FPS32(reg) m_fs_regmap[reg] +#define FPD32(reg) m_fd_regmap[reg & 14] enum { ICF = 0x00800000, -- cgit v1.2.3