From ae850a9d66a596458138dae80d93f94da5af7537 Mon Sep 17 00:00:00 2001 From: Ted Green Date: Mon, 5 Jun 2017 11:52:50 -0600 Subject: z80scc: Move rearming of tx interrupt from tx buffer write to transmit complete when using WR0_RESET_TX_INT. (nw) --- src/devices/machine/z80scc.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/devices/machine/z80scc.cpp b/src/devices/machine/z80scc.cpp index cc4792193d1..fc795d688a9 100644 --- a/src/devices/machine/z80scc.cpp +++ b/src/devices/machine/z80scc.cpp @@ -1149,6 +1149,9 @@ void z80scc_channel::tra_complete() m_uart->trigger_interrupt(m_index, INT_TRANSMIT); // Set TXIP bit } } + /* Arm interrupts since we completed another data byte, however it may be set by the reset tx int pending + command before the shifter is done and the disarm flag is evaluated again in tra_complete() */ + m_tx_int_disarm = 0; } else if (m_wr5 & WR5_SEND_BREAK) { @@ -2435,9 +2438,6 @@ void z80scc_channel::data_write(uint8_t data) // check if to fire interrupt LOG("- TX interrupt are %s\n", (m_wr1 & WR1_TX_INT_ENABLE) ? "enabled" : "disabled" ); - /* Arm interrupts since we wrote another data byte, however it may be set by the reset tx int pending - command before the shifter is done and the disarm flag is evaluated again in tra_complete() */ - m_tx_int_disarm = 0; if (m_wr1 & WR1_TX_INT_ENABLE) { if ((m_uart->m_variant & z80scc_device::SET_ESCC) && -- cgit v1.2.3