From a36a9bef31fa70ead2f7f4ac6e67b265d98b7704 Mon Sep 17 00:00:00 2001 From: hap Date: Sat, 7 Mar 2015 20:59:59 +0100 Subject: moved i/o handling to the c file --- src/emu/cpu/hmcs40/hmcs40.c | 151 ++++++++++++++++++++++++++++++++++++++++ src/emu/cpu/hmcs40/hmcs40op.inc | 150 --------------------------------------- 2 files changed, 151 insertions(+), 150 deletions(-) diff --git a/src/emu/cpu/hmcs40/hmcs40.c b/src/emu/cpu/hmcs40/hmcs40.c index 9422ce7db07..098f80a3ef6 100644 --- a/src/emu/cpu/hmcs40/hmcs40.c +++ b/src/emu/cpu/hmcs40/hmcs40.c @@ -280,6 +280,157 @@ void hmcs40_cpu_device::device_reset() +//------------------------------------------------- +// i/o handling +//------------------------------------------------- + +UINT8 hmcs40_cpu_device::read_r(int index) +{ + index &= 7; + UINT8 inp = 0xf; + + switch (index) + { + case 0: inp = m_read_r0(index, 0xff); break; + case 1: inp = m_read_r1(index, 0xff); break; + case 2: inp = m_read_r2(index, 0xff); break; + case 3: inp = m_read_r3(index, 0xff); break; + case 4: inp = m_read_r4(index, 0xff); break; + case 5: inp = m_read_r5(index, 0xff); break; + case 6: inp = m_read_r6(index, 0xff); break; + case 7: inp = m_read_r7(index, 0xff); break; + } + + if (m_is_cmos) + return (inp & m_r[index]) & 0xf; + else + return (inp | m_r[index]) & 0xf; +} + +void hmcs40_cpu_device::write_r(int index, UINT8 data) +{ + index &= 7; + data &= 0xf; + m_r[index] = data; + + switch (index) + { + case 0: m_write_r0(index, m_r[index], 0xff); break; + case 1: m_write_r1(index, m_r[index], 0xff); break; + case 2: m_write_r2(index, m_r[index], 0xff); break; + case 3: m_write_r3(index, m_r[index], 0xff); break; + case 4: m_write_r4(index, m_r[index], 0xff); break; + case 5: m_write_r5(index, m_r[index], 0xff); break; + case 6: m_write_r6(index, m_r[index], 0xff); break; + case 7: m_write_r7(index, m_r[index], 0xff); break; + } +} + +int hmcs40_cpu_device::read_d(int index) +{ + index &= 15; + + if (m_is_cmos) + return (m_read_d(index, 0xffff) & m_d) >> index & 1; + else + return (m_read_d(index, 0xffff) | m_d) >> index & 1; +} + +void hmcs40_cpu_device::write_d(int index, int state) +{ + index &= 15; + + m_d = (m_d & ~(1 << index)) | (((state) ? 1 : 0) << index); + m_write_d(index, m_d, 0xffff); +} + +// HMCS43: +// R0 is input-only, R1 is i/o, R2,R3 are output-only, no R4-R7 +// D0-D3 are i/o, D4-D15 are output-only + +UINT8 hmcs43_cpu_device::read_r(int index) +{ + index &= 7; + + if (index >= 2) + logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc << 1); + + return hmcs40_cpu_device::read_r(index); +} + +void hmcs43_cpu_device::write_r(int index, UINT8 data) +{ + index &= 7; + + if (index != 0 && index < 4) + hmcs40_cpu_device::write_r(index, data); + else + logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1); +} + +int hmcs43_cpu_device::read_d(int index) +{ + index &= 15; + + if (index >= 4) + { + logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc << 1); + return m_d >> index & 1; + } + else + return hmcs40_cpu_device::read_d(index); +} + +// HMCS44: +// R0-R3 are i/o, R4,R5 are extra registers, no R6,R7 +// D0-D15 are i/o + +UINT8 hmcs44_cpu_device::read_r(int index) +{ + index &= 7; + + if (index >= 6) + logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc << 1); + + return hmcs40_cpu_device::read_r(index); +} + +void hmcs44_cpu_device::write_r(int index, UINT8 data) +{ + index &= 7; + + if (index < 6) + hmcs40_cpu_device::write_r(index, data); + else + logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1); +} + +// HMCS45: +// R0-R5 are i/o, R6 is output-only, no R7 +// D0-D15 are i/o + +UINT8 hmcs45_cpu_device::read_r(int index) +{ + index &= 7; + + if (index >= 6) + logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc << 1); + + return hmcs40_cpu_device::read_r(index); +} + +void hmcs45_cpu_device::write_r(int index, UINT8 data) +{ + index &= 7; + + if (index != 7) + hmcs40_cpu_device::write_r(index, data); + else + logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1); +} + + + //------------------------------------------------- // execute //------------------------------------------------- diff --git a/src/emu/cpu/hmcs40/hmcs40op.inc b/src/emu/cpu/hmcs40/hmcs40op.inc index c7fec314064..bdcba20c658 100644 --- a/src/emu/cpu/hmcs40/hmcs40op.inc +++ b/src/emu/cpu/hmcs40/hmcs40op.inc @@ -29,156 +29,6 @@ void hmcs40_cpu_device::push_stack() } -// i/o - -UINT8 hmcs40_cpu_device::read_r(int index) -{ - index &= 7; - UINT8 inp = 0xf; - - switch (index) - { - case 0: inp = m_read_r0(index, 0xff); break; - case 1: inp = m_read_r1(index, 0xff); break; - case 2: inp = m_read_r2(index, 0xff); break; - case 3: inp = m_read_r3(index, 0xff); break; - case 4: inp = m_read_r4(index, 0xff); break; - case 5: inp = m_read_r5(index, 0xff); break; - case 6: inp = m_read_r6(index, 0xff); break; - case 7: inp = m_read_r7(index, 0xff); break; - } - - if (m_is_cmos) - return (inp & m_r[index]) & 0xf; - else - return (inp | m_r[index]) & 0xf; -} - -void hmcs40_cpu_device::write_r(int index, UINT8 data) -{ - index &= 7; - data &= 0xf; - m_r[index] = data; - - switch (index) - { - case 0: m_write_r0(index, m_r[index], 0xff); break; - case 1: m_write_r1(index, m_r[index], 0xff); break; - case 2: m_write_r2(index, m_r[index], 0xff); break; - case 3: m_write_r3(index, m_r[index], 0xff); break; - case 4: m_write_r4(index, m_r[index], 0xff); break; - case 5: m_write_r5(index, m_r[index], 0xff); break; - case 6: m_write_r6(index, m_r[index], 0xff); break; - case 7: m_write_r7(index, m_r[index], 0xff); break; - } -} - -int hmcs40_cpu_device::read_d(int index) -{ - index &= 15; - - if (m_is_cmos) - return (m_read_d(index, 0xffff) & m_d) >> index & 1; - else - return (m_read_d(index, 0xffff) | m_d) >> index & 1; -} - -void hmcs40_cpu_device::write_d(int index, int state) -{ - index &= 15; - - m_d = (m_d & ~(1 << index)) | (((state) ? 1 : 0) << index); - m_write_d(index, m_d, 0xffff); -} - -// HMCS43: -// R0 is input-only, R1 is i/o, R2,R3 are output-only, no R4-R7 -// D0-D3 are i/o, D4-D15 are output-only - -UINT8 hmcs43_cpu_device::read_r(int index) -{ - index &= 7; - - if (index >= 2) - logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc << 1); - - return hmcs40_cpu_device::read_r(index); -} - -void hmcs43_cpu_device::write_r(int index, UINT8 data) -{ - index &= 7; - - if (index != 0 && index < 4) - hmcs40_cpu_device::write_r(index, data); - else - logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1); -} - -int hmcs43_cpu_device::read_d(int index) -{ - index &= 15; - - if (index >= 4) - { - logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc << 1); - return m_d >> index & 1; - } - else - return hmcs40_cpu_device::read_d(index); -} - -// HMCS44: -// R0-R3 are i/o, R4,R5 are extra registers, no R6,R7 -// D0-D15 are i/o - -UINT8 hmcs44_cpu_device::read_r(int index) -{ - index &= 7; - - if (index >= 6) - logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc << 1); - - return hmcs40_cpu_device::read_r(index); -} - -void hmcs44_cpu_device::write_r(int index, UINT8 data) -{ - index &= 7; - - if (index < 6) - hmcs40_cpu_device::write_r(index, data); - else - logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1); -} - -// HMCS45: -// R0-R5 are i/o, R6 is output-only, no R7 -// D0-D15 are i/o - -UINT8 hmcs45_cpu_device::read_r(int index) -{ - index &= 7; - - if (index >= 6) - logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc << 1); - - return hmcs40_cpu_device::read_r(index); -} - -void hmcs45_cpu_device::write_r(int index, UINT8 data) -{ - index &= 7; - - if (index != 7) - hmcs40_cpu_device::write_r(index, data); - else - logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1); -} - - - - // instruction set -- cgit v1.2.3