From 86b12e10d804bc2613b7535f3d9ed33c97c1078a Mon Sep 17 00:00:00 2001 From: mamehaze Date: Mon, 26 Jan 2015 00:26:25 +0000 Subject: refactor funkball.c flash access to use intelfsh.c via bankdev, doesn't improve anything tho (nw) --- src/emu/machine/intelfsh.c | 14 ++++++ src/emu/machine/intelfsh.h | 11 +++++ src/mame/drivers/funkball.c | 105 +++++++++++++++++--------------------------- 3 files changed, 65 insertions(+), 65 deletions(-) diff --git a/src/emu/machine/intelfsh.c b/src/emu/machine/intelfsh.c index 8d15e34ff2c..8cf6f54cb6b 100644 --- a/src/emu/machine/intelfsh.c +++ b/src/emu/machine/intelfsh.c @@ -102,6 +102,8 @@ const device_type INTEL_E28F008SA = &device_creator; const device_type INTEL_TE28F160 = &device_creator; const device_type SHARP_UNK128MBIT = &device_creator; const device_type INTEL_28F320J3D = &device_creator; +const device_type INTEL_28F320J5 = &device_creator; + const device_type SST_39VF400A = &device_creator; static ADDRESS_MAP_START( memory_map8_512Kb, AS_PROGRAM, 8, intelfsh_device ) @@ -246,6 +248,14 @@ intelfsh_device::intelfsh_device(const machine_config &mconfig, device_type type m_sector_is_4k = true; map = ADDRESS_MAP_NAME( memory_map16_32Mb ); break; + case FLASH_INTEL_28F320J5: // funkball + m_bits = 16; + m_size = 0x400000; + m_maker_id = MFG_INTEL; + m_device_id = 0x14; +// m_sector_is_4k = true; 128kb? + map = ADDRESS_MAP_NAME( memory_map16_32Mb ); + break; case FLASH_SST_39VF020: m_bits = 8; m_size = 0x40000; @@ -446,6 +456,10 @@ sharp_unk128mbit_device::sharp_unk128mbit_device(const machine_config &mconfig, intel_28f320j3d_device::intel_28f320j3d_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : intelfsh16_device(mconfig, INTEL_28F320J3D, "Intel 28F320J3D Flash", tag, owner, clock, FLASH_INTEL_28F320J3D, "intel_28f320j3d", __FILE__) { } +intel_28f320j5_device::intel_28f320j5_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : intelfsh16_device(mconfig, INTEL_28F320J5, "Intel 28F320J3D_a Flash", tag, owner, clock, FLASH_INTEL_28F320J5, "intel_28f320j5", __FILE__) { } + + sst_39vf400a_device::sst_39vf400a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : intelfsh16_device(mconfig, SST_39VF400A, "SST 39VF400A Flash", tag, owner, clock, FLASH_SST_39VF400A, "sst_39vf400a", __FILE__) { } diff --git a/src/emu/machine/intelfsh.h b/src/emu/machine/intelfsh.h index 95fce17b2ee..41719cdbfc8 100644 --- a/src/emu/machine/intelfsh.h +++ b/src/emu/machine/intelfsh.h @@ -82,6 +82,9 @@ #define MCFG_INTEL_28F320J3D_ADD(_tag) \ MCFG_DEVICE_ADD(_tag, INTEL_28F320J3D, 0) +#define MCFG_INTEL_28F320J5_ADD(_tag) \ + MCFG_DEVICE_ADD(_tag, INTEL_28F320J5, 0) + #define MCFG_SST_39VF400A_ADD(_tag) \ MCFG_DEVICE_ADD(_tag, SST_39VF400A, 0) @@ -128,6 +131,7 @@ public: FLASH_INTEL_TE28F160, FLASH_SHARP_UNK128MBIT, FLASH_INTEL_28F320J3D, + FLASH_INTEL_28F320J5, FLASH_SST_39VF400A }; @@ -363,6 +367,12 @@ public: intel_28f320j3d_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); }; +class intel_28f320j5_device : public intelfsh16_device +{ +public: + intel_28f320j5_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + class sst_39vf400a_device : public intelfsh16_device { public: @@ -397,6 +407,7 @@ extern const device_type INTEL_E28F008SA; extern const device_type INTEL_TE28F160; extern const device_type SHARP_UNK128MBIT; extern const device_type INTEL_28F320J3D; +extern const device_type INTEL_28F320J5; extern const device_type SST_39VF400A; #endif diff --git a/src/mame/drivers/funkball.c b/src/mame/drivers/funkball.c index d96872f921c..b5fc7b1cdf7 100644 --- a/src/mame/drivers/funkball.c +++ b/src/mame/drivers/funkball.c @@ -76,6 +76,8 @@ Notes: #include "machine/idectrl.h" #include "video/voodoo.h" #include "machine/pcshare.h" +#include "machine/bankdev.h" +#include "machine/intelfsh.h" class funkball_state : public pcat_base_state @@ -84,27 +86,27 @@ public: funkball_state(const machine_config &mconfig, device_type type, const char *tag) : pcat_base_state(mconfig, type, tag), m_voodoo(*this, "voodoo_0"), - m_unk_ram(*this, "unk_ram"){ } + m_unk_ram(*this, "unk_ram"), + m_flashbank(*this, "flashbank") + { } UINT8 m_funkball_config_reg_sel; UINT8 m_funkball_config_regs[256]; UINT32 m_cx5510_regs[256/4]; - UINT16 m_flash_addr; UINT8 *m_bios_ram; - UINT8 m_flash_cmd; - UINT8 m_flash_data_cmd; UINT32 m_biu_ctrl_reg[256/4]; + UINT32 flashbank_addr; + // devices required_device m_voodoo; required_shared_ptr m_unk_ram; + required_device m_flashbank; DECLARE_READ8_MEMBER( get_slave_ack ); - DECLARE_WRITE8_MEMBER( flash_w ); - DECLARE_READ8_MEMBER( flash_data_r ); - DECLARE_WRITE8_MEMBER( flash_data_w ); + DECLARE_WRITE32_MEMBER( flash_w ); // DECLARE_WRITE8_MEMBER( bios_ram_w ); DECLARE_READ8_MEMBER( test_r ); DECLARE_READ8_MEMBER( serial_r ); @@ -272,63 +274,16 @@ WRITE8_MEMBER(funkball_state::io20_w) } } -WRITE8_MEMBER( funkball_state::flash_w ) -{ - if(!(offset & 0x2)) - { - m_flash_addr = (offset & 1) ? ((m_flash_addr & 0xff) | (data << 8)) : ((m_flash_addr & 0xff00) | (data)); - //printf("%08x ADDR\n",m_flash_addr << 16); - } - else if(offset == 2) - { - /* 0x83: read from u29/u30 - 0x03: read from u3 - 0x81: init device - */ - m_flash_cmd = data; - printf("%02x CMD\n",data); - } - else - printf("%02x %02x\n",offset,data); -} - -READ8_MEMBER( funkball_state::flash_data_r ) +WRITE32_MEMBER(funkball_state::flash_w) { - if(m_flash_data_cmd == 0x90) - { - if(offset == 0 && (m_flash_addr == 0)) - return 0x89; // manufacturer code - - if(offset == 2 && (m_flash_addr == 0)) - return (m_flash_cmd & 0x80) ? 0x15 : 0x14; // device code, 32 MBit in both cases - - if(offset > 3) - printf("%02x FLASH DATA 0x90\n",offset); - - return 0; - } - - if(m_flash_data_cmd == 0xff) - { - UINT8 *ROM = memregion(m_flash_cmd & 0x80 ? "data_flash" : "prg_flash")->base(); - - return ROM[offset + (m_flash_addr << 16)]; - } + COMBINE_DATA(&flashbank_addr); + int tempbank = (flashbank_addr & 0x7fff) | ((flashbank_addr & 0x00800000) >> 8); + m_flashbank->set_bank(tempbank); - printf("%02x %08x %02x %02x\n",offset,m_flash_addr << 16,m_flash_cmd,m_flash_data_cmd); + // note, other bits get used, but ignoring to keep the virtual bank space size sane. - return 0; } -WRITE8_MEMBER( funkball_state::flash_data_w ) -{ - if(offset == 0) - { - m_flash_data_cmd = data; - } - else - printf("%08x %02x FLASH DATA W %08x\n",offset,data,m_flash_addr << 16); -} READ32_MEMBER(funkball_state::biu_ctrl_r) { @@ -378,7 +333,7 @@ READ8_MEMBER( funkball_state::test_r ) static ADDRESS_MAP_START(funkball_map, AS_PROGRAM, 32, funkball_state) AM_RANGE(0x00000000, 0x0009ffff) AM_RAM AM_RANGE(0x000a0000, 0x000affff) AM_RAM - AM_RANGE(0x000b0000, 0x000bffff) AM_READWRITE8(flash_data_r,flash_data_w,0xffffffff) + AM_RANGE(0x000b0000, 0x000bffff) AM_DEVICE("flashbank", address_map_bank_device, amap32) AM_RANGE(0x000c0000, 0x000cffff) AM_RAM AM_RANGE(0x000d0000, 0x000dffff) AM_RAM AM_RANGE(0x000e0000, 0x000e3fff) AM_ROMBANK("bios_ext1") @@ -398,6 +353,13 @@ static ADDRESS_MAP_START(funkball_map, AS_PROGRAM, 32, funkball_state) AM_RANGE(0xfffe0000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */ ADDRESS_MAP_END +static ADDRESS_MAP_START( flashbank_map, AS_PROGRAM, 32, funkball_state ) + AM_RANGE(0x00000000, 0x003fffff) AM_DEVREADWRITE16("u29", intel_28f320j5_device, read, write, 0xffffffff ) + AM_RANGE(0x00400000, 0x007fffff) AM_DEVREADWRITE16("u30", intel_28f320j5_device, read, write, 0xffffffff ) + AM_RANGE(0x00800000, 0x00bfffff) AM_DEVREADWRITE16("u3", intel_28f320j5_device, read, write, 0xffffffff ) + /* it checks for 64MBit chips at 0x80000000 the way things are set up, they must return an intel Flash ID of 0x15 */ +ADDRESS_MAP_END + static ADDRESS_MAP_START(funkball_io, AS_IO, 32, funkball_state) AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000) AM_IMPORT_FROM(pcat32_io_common) @@ -409,7 +371,7 @@ static ADDRESS_MAP_START(funkball_io, AS_IO, 32, funkball_state) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) - AM_RANGE(0x0360, 0x0363) AM_WRITE8(flash_w,0xffffffff) + AM_RANGE(0x0360, 0x0363) AM_WRITE(flash_w) // AM_RANGE(0x0320, 0x0323) AM_READ(test_r) AM_RANGE(0x0360, 0x036f) AM_READ8(test_r,0xffffffff) // inputs @@ -862,6 +824,13 @@ static MACHINE_CONFIG_START( funkball, funkball_state ) MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true) MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w)) + MCFG_DEVICE_ADD("flashbank", ADDRESS_MAP_BANK, 0) + MCFG_DEVICE_PROGRAM_MAP(flashbank_map) + MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) + MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32) + MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(64) + MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000) + /* video hardware */ MCFG_DEVICE_ADD("voodoo_0", VOODOO_1, STD_VOODOO_1_CLOCK) MCFG_VOODOO_FBMEM(2) @@ -875,18 +844,24 @@ static MACHINE_CONFIG_START( funkball, funkball_state ) MCFG_SCREEN_UPDATE_DRIVER(funkball_state, screen_update) MCFG_SCREEN_SIZE(1024, 1024) MCFG_SCREEN_VISIBLE_AREA(0, 511, 16, 447) + + MCFG_INTEL_28F320J5_ADD("u29") + MCFG_INTEL_28F320J5_ADD("u30") + MCFG_INTEL_28F320J5_ADD("u3") MACHINE_CONFIG_END ROM_START( funkball ) ROM_REGION32_LE(0x20000, "bios", ROMREGION_ERASEFF) ROM_LOAD( "512k-epr.u62", 0x010000, 0x010000, CRC(cced894a) SHA1(298c81716e375da4b7215f3e588a45ca3ea7e35c) ) - ROM_REGION(0x8000000, "prg_flash", ROMREGION_ERASE00) + ROM_REGION(0x4000000, "u3", ROMREGION_ERASE00) ROM_LOAD16_WORD_SWAP( "flash.u3", 0x0000000, 0x400000, CRC(fb376abc) SHA1(ea4c48bb6cd2055431a33f5c426e52c7af6997eb) ) - ROM_REGION(0x8000000, "data_flash", ROMREGION_ERASE00) - ROM_LOAD( "flash.u29",0x0000000, 0x400000, CRC(7cf6ff4b) SHA1(4ccdd4864ad92cc218998f3923997119a1a9dd1d) ) - ROM_LOAD( "flash.u30",0x0400000, 0x400000, CRC(1d46717a) SHA1(acfbd0a2ccf4d717779733c4a9c639296c3bbe0e) ) + ROM_REGION(0x8000000, "u29", ROMREGION_ERASE00) + ROM_LOAD16_WORD_SWAP( "flash.u29",0x0000000, 0x400000, CRC(7cf6ff4b) SHA1(4ccdd4864ad92cc218998f3923997119a1a9dd1d) ) + + ROM_REGION(0x4000000, "u30", ROMREGION_ERASE00) + ROM_LOAD16_WORD_SWAP( "flash.u30",0x0400000, 0x400000, CRC(1d46717a) SHA1(acfbd0a2ccf4d717779733c4a9c639296c3bbe0e) ) ROM_END -- cgit v1.2.3