From 82c1756aa3c81e28d0a0d72d635350683cae1981 Mon Sep 17 00:00:00 2001 From: Olivier Galibert Date: Wed, 17 May 2023 12:28:01 +0200 Subject: h8: Make fully wait-states compatible --- src/devices/cpu/h8/gt913.lst | 49 ++- src/devices/cpu/h8/h8.cpp | 11 +- src/devices/cpu/h8/h8.h | 7 +- src/devices/cpu/h8/h8.lst | 771 ++++++++++++++++++++++--------------------- src/devices/cpu/h8/h8make.py | 32 +- 5 files changed, 455 insertions(+), 415 deletions(-) diff --git a/src/devices/cpu/h8/gt913.lst b/src/devices/cpu/h8/gt913.lst index 7365bd2d3e1..9489496c0cf 100644 --- a/src/devices/cpu/h8/gt913.lst +++ b/src/devices/cpu/h8/gt913.lst @@ -1,6 +1,19 @@ # license:BSD-3-Clause # copyright-holders:Olivier Galibert, Devin Acker +macro prefetch_start + NPC = PC & 0xffffff; + PIR = read16i(PC); + PC += 2; + +macro prefetch + prefetch_start + prefetch_done(); + +macro prefetch_noirq + prefetch_start + prefetch_done_noirq(); + 10000 reset 10001 irq @@ -12,12 +25,12 @@ 0380 fff0 0 ldbank r8l bankl g TMP1 = r8_r(IR[0]) & 0x3f; m_banknum = (m_banknum & 0xffc0) | TMP1; - prefetch(); + prefetch 03c0 fff0 0 ldbank r8l bankh g TMP1 = r8_r(IR[0]) & 0x3f; m_banknum = (TMP1 << 6) | (m_banknum & 0x3f); - prefetch(); + prefetch 0400 ff00 0 orc imm8 ccr 0500 ff00 0 xorc imm8 ccr @@ -26,15 +39,15 @@ 0740 ffc0 0 ldc imm6l ccr g CCR = IR[0] & 0x3f; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 0780 ffc0 0 ldbank imm6l bankl g m_banknum = (m_banknum & 0xffc0) | (IR[0] & 0x3f); - prefetch(); + prefetch 07c0 ffc0 0 ldbank imm6l bankh g m_banknum = ((IR[0] & 0x3f) << 6) | (m_banknum & 0x3f); - prefetch(); + prefetch 0800 ff00 0 add.b r8h r8l 0900 ff00 0 add.w r16h r16l @@ -114,7 +127,7 @@ internal(1); m_banknum = ((IR[0] & 0x3f) << 2) | (IR[1] >> 14); PC = 0x8000 | (IR[1] & 0x3fff); - prefetch(); + prefetch 5c00 ff8f 0 jsr r16h - 5c80 ffff 0 jsr abs16e - @@ -131,7 +144,7 @@ 67000000 ff8fff0f 0 btst r8h r16ihh 6800 ff80 0 mov.b r16ih r8l g - prefetch_start(); + prefetch_start internal(1); TMP1 = read8ib(r16_r(IR[0] >> 4)); set_nzv8(TMP1); @@ -139,7 +152,7 @@ prefetch_done(); 6900 ff88 0 mov.w r16ih r16l g - prefetch_start(); + prefetch_start internal(1); TMP1 = read16ib(r16_r(IR[0] >> 4)); set_nzv16(TMP1); @@ -148,7 +161,7 @@ 6a00 ff80 0 mov.b r16ph r8l g TMP2 = r16_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(2); TMP1 = read8ib(TMP2); TMP2 += 1; @@ -159,7 +172,7 @@ 6b00 ff88 0 mov.w r16ph r16l g TMP2 = r16_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(2); TMP1 = read16ib(TMP2); TMP2 += 2; @@ -172,7 +185,7 @@ 6d00 fff0 0 mov.w abs16 r16l 6e00 ff80 0 mov.b r16d16h r8l g - prefetch_start(); + prefetch_start TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); internal(1); TMP2 = read8ib(TMP1); @@ -181,7 +194,7 @@ prefetch_done(); 6f00 ff80 0 mov.w r16d16h r16l g - prefetch_start(); + prefetch_start TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); internal(1); TMP2 = read16ib(TMP1); @@ -199,7 +212,7 @@ 77000000 ff00ff0f 0 btst r8h abs8 7800 ff80 0 mov.b r8l r16ih g - prefetch_start(); + prefetch_start TMP1 = r8_r(IR[0]); set_nzv8(TMP1); internal(1); @@ -207,7 +220,7 @@ prefetch_done(); 7900 ff88 0 mov.w r16l r16ih g - prefetch_start(); + prefetch_start TMP1 = r16_r(IR[0]); set_nzv16(TMP1); internal(1); @@ -217,7 +230,7 @@ 7a00 ff80 0 mov.b r8l pr16h g TMP1 = r8_r(IR[0]); TMP2 = r16_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(1); TMP2 -= 1; r16_w(IR[0] >> 4, TMP2); @@ -229,7 +242,7 @@ 7b00 ff88 0 mov.w r16l pr16h g TMP1 = r16_r(IR[0]); TMP2 = r16_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(1); TMP2 -= 2; r16_w(IR[0] >> 4, TMP2); @@ -242,7 +255,7 @@ 7d00 fff0 0 mov.w r16l abs16 7e00 ff80 0 mov.b r8l r16d16h g - prefetch_start(); + prefetch_start TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); TMP2 = r8_r(IR[0]); set_nzv8(TMP2); @@ -251,7 +264,7 @@ prefetch_done(); 7f00 ff80 0 mov.w r16l r16d16h g - prefetch_start(); + prefetch_start TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); TMP2 = r16_r(IR[0]); set_nzv16(TMP2); diff --git a/src/devices/cpu/h8/h8.cpp b/src/devices/cpu/h8/h8.cpp index b66033059e3..32526652b1c 100644 --- a/src/devices/cpu/h8/h8.cpp +++ b/src/devices/cpu/h8/h8.cpp @@ -46,11 +46,11 @@ void h8_device::device_start() uint32_t pcmask = mode_advanced ? 0xffffff : 0xffff; state_add(H8_PC, "PC", [this]() { return NPC; }, - [this](uint32_t pc) { PC = PPC = NPC = pc; prefetch_noirq_notrace(); } + [this](uint32_t pc) { PC = PPC = NPC = pc; PIR = read16i(PC); PC += 2; prefetch_done_noirq_notrace(); } ).mask(pcmask); state_add(STATE_GENPC, "GENPC", [this]() { return NPC; }, - [this](uint32_t pc) { PC = PPC = NPC = pc; prefetch_noirq_notrace(); } + [this](uint32_t pc) { PC = PPC = NPC = pc; PIR = read16i(PC); PC += 2; prefetch_done_noirq_notrace(); } ).mask(pcmask).noshow(); state_add(STATE_GENPCBASE, "CURPC", PPC).mask(pcmask).noshow(); state_add(H8_CCR, "CCR", CCR); @@ -361,13 +361,6 @@ uint16_t h8_device::read16i(uint32_t adr) return cache.read_word(adr & ~1); } -uint16_t h8_device::fetch() -{ - uint16_t res = read16i(PC); - PC += 2; - return res; -} - uint8_t h8_device::read8(uint32_t adr) { icount--; diff --git a/src/devices/cpu/h8/h8.h b/src/devices/cpu/h8/h8.h index 78ee9425142..773867a5802 100644 --- a/src/devices/cpu/h8/h8.h +++ b/src/devices/cpu/h8/h8.h @@ -95,6 +95,7 @@ protected: virtual void device_reset() override; // device_execute_interface overrides + virtual bool cpu_is_interruptible() const override { return true; } virtual uint32_t execute_min_cycles() const noexcept override; virtual uint32_t execute_max_cycles() const noexcept override; virtual uint32_t execute_input_lines() const noexcept override; @@ -156,17 +157,11 @@ protected: virtual void irq_setup() = 0; uint16_t read16i(uint32_t adr); - uint16_t fetch(); - inline void fetch(int slot) { IR[slot] = fetch(); } uint8_t read8(uint32_t adr); void write8(uint32_t adr, uint8_t data); uint16_t read16(uint32_t adr); void write16(uint32_t adr, uint16_t data); void internal(int cycles); - inline void prefetch() { prefetch_start(); prefetch_done(); } - inline void prefetch_noirq() { prefetch_start(); prefetch_done_noirq(); } - inline void prefetch_noirq_notrace() { prefetch_start(); prefetch_done_noirq_notrace(); } - void prefetch_start() { NPC = PC & 0xffffff; PIR = fetch(); } void prefetch_switch(uint32_t pc, uint16_t ir) { NPC = pc & 0xffffff; PC = pc+2; PIR = ir; } void prefetch_done(); void prefetch_done_noirq(); diff --git a/src/devices/cpu/h8/h8.lst b/src/devices/cpu/h8/h8.lst index 6c0cd069c11..9e2a67f0cc9 100644 --- a/src/devices/cpu/h8/h8.lst +++ b/src/devices/cpu/h8/h8.lst @@ -1,7 +1,28 @@ # license:BSD-3-Clause # copyright-holders:Olivier Galibert + +macro fetch + PIR = read16i(PC); + PC += 2; + +macro prefetch_start + NPC = PC & 0xffffff; + fetch + +macro prefetch + prefetch_start + prefetch_done(); + +macro prefetch_noirq + prefetch_start + prefetch_done_noirq(); + +macro prefetch_noirq_notrace + prefetch_start + prefetch_done_noirq_notrace(); + macro bxx_any %cond - prefetch_start(); + prefetch_start TMP2 = read16i(TMP1); if(%cond) prefetch_switch(TMP1, TMP2); @@ -79,14 +100,14 @@ macro bist %bit TMP1 &= ~(1 << ((%bit) & 7)); macro jsr16 %opc %spreg - prefetch_start(); + prefetch_start %spreg = r16_r(7) - 2; r16_w(7, %spreg); write16(%spreg, %opc); prefetch_done(); macro jsr32 %opc %spreg - prefetch_start(); + prefetch_start if(mode_advanced) { %spreg = r32_r(7) - 4; r32_w(7, %spreg); @@ -110,7 +131,7 @@ macro jsr32 %opc %spreg PC = read16i(0); } update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 10001 irq o internal(1); @@ -126,7 +147,7 @@ macro jsr32 %opc %spreg irq_setup(); update_irq_filter(); interrupt_taken(); - prefetch_noirq(); + prefetch_noirq 10001 irq h internal(1); @@ -153,7 +174,7 @@ macro jsr32 %opc %spreg irq_setup(); update_irq_filter(); interrupt_taken(); - prefetch_noirq(); + prefetch_noirq 10002 trace s20 internal(1); @@ -176,7 +197,7 @@ macro jsr32 %opc %spreg PC = read16i(2*taken_irq_vector); } internal(1); - prefetch_noirq(); + prefetch_noirq 10003 dma if(current_dma->count == 1) @@ -252,10 +273,10 @@ macro jsr32 %opc %spreg prefetch_done(); 0000 ffff 0 nop - - - prefetch(); + prefetch 01006900 ffffff88 0 mov.l r32ih r32l h - prefetch_start(); + prefetch_start TMP2 = r32_r(IR[1] >> 4); TMP1 = read16(TMP2) << 16; TMP1 |= read16(TMP2+2); @@ -264,7 +285,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01006980 ffffff88 0 mov.l r32l r32ih h - prefetch_start(); + prefetch_start TMP2 = r32_r(IR[1] >> 4); TMP1 = r32_r(IR[1]); set_nzv32(TMP1); @@ -273,7 +294,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01006b00 fffffff8 0 mov.l abs16 r32l h - prefetch_start(); + prefetch_start TMP2 = int16_t(IR[2]); TMP1 = read16(TMP2) << 16; TMP1 |= read16(TMP2+2); @@ -282,7 +303,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01006b20 fffffff8 0 mov.l abs32 r32l h - prefetch_start(); + prefetch_start TMP2 = (IR[2] << 16) | IR[3]; TMP1 = read16(TMP2) << 16; TMP1 |= read16(TMP2+2); @@ -291,7 +312,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01006b80 fffffff8 0 mov.l r32l abs16 h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1]); TMP2 = int16_t(IR[2]); set_nzv32(TMP1); @@ -300,7 +321,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01006ba0 fffffff8 0 mov.l r32l abs32 h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1]); TMP2 = (IR[2] << 16) | IR[3]; set_nzv32(TMP1); @@ -309,7 +330,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01006d00 ffffff88 0 mov.l r32ph r32l h - prefetch_start(); + prefetch_start internal(1); TMP2 = r32_r(IR[1] >> 4); TMP1 = read16(TMP2) << 16; @@ -321,7 +342,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01006d80 ffffff88 0 mov.l r32l pr32h h - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(IR[1]); TMP2 = r32_r(IR[1] >> 4); @@ -333,7 +354,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01006f00 ffffff88 0 mov.l r32d16h r32l h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); TMP2 = read16(TMP1) << 16; TMP2 |= read16(TMP1+2); @@ -342,7 +363,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01006f80 ffffff88 0 mov.l r32l r32d16h h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); TMP2 = r32_r(IR[1]); set_nzv32(TMP2); @@ -351,7 +372,7 @@ macro jsr32 %opc %spreg prefetch_done(); 010078006b20 ffffff0ffff8 0 mov.l r32d32hh r32l h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; TMP2 = read16(TMP1) << 16; TMP2 |= read16(TMP1+2); @@ -360,7 +381,7 @@ macro jsr32 %opc %spreg prefetch_done(); 010078006ba0 ffffff0ffff8 0 mov.l r32l r32d32hh h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; TMP2 = r32_r(IR[2]); set_nzv32(TMP2); @@ -369,7 +390,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01106d71 fffffff9 0 ldm.l spp r32n2l s20 - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(7); TMP2 = read16(TMP1) << 16; @@ -387,7 +408,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01106df0 fffffff9 0 stm.l r32n2l psp s20 - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(7); TMP1 -= 4; @@ -403,7 +424,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01206d72 fffffffb 0 ldm.l spp r32n3l s20 - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(7); TMP2 = read16(TMP1) << 16; @@ -424,7 +445,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01206df0 fffffffb 0 stm.l r32n3l psp s20 - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(7); TMP1 -= 4; @@ -445,7 +466,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01306d73 fffffffb 0 ldm.l spp r32n4l s20 - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(7); TMP2 = read16(TMP1) << 16; @@ -473,7 +494,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01306df0 fffffffb 0 stm.l r32n4l psp s20 - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(7); TMP1 -= 4; @@ -499,46 +520,46 @@ macro jsr32 %opc %spreg prefetch_done(); 01406900 ffffff8f 0 ldc.w r32ih ccr h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4); CCR = read16(TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 01406980 ffffff8f 0 stc.w ccr r32ih h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4); write16(TMP1, (CCR << 8) | CCR); prefetch_done(); 01406b00 ffffffff 0 ldc.w abs16 ccr h - prefetch_start(); + prefetch_start TMP1 = int16_t(IR[2]); CCR = read16(TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 01406b20 ffffffff 0 ldc.w abs32 ccr h - prefetch_start(); + prefetch_start TMP1 = (IR[2] << 16) | IR[3]; CCR = read16(TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 01406b80 ffffffff 0 stc.w ccr abs16 h - prefetch_start(); + prefetch_start TMP1 = int16_t(IR[2]); write16(TMP1, (CCR << 8) | CCR); prefetch_done(); 01406ba0 ffffffff 0 stc.w ccr abs32 h - prefetch_start(); + prefetch_start TMP1 = (IR[2] << 16) | IR[3]; write16(TMP1, (CCR << 8) | CCR); prefetch_done(); 01406d00 ffffff8f 0 ldc.w r32ph ccr h - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(IR[1] >> 4); r32_w(IR[1] >> 4, TMP1+2); @@ -547,7 +568,7 @@ macro jsr32 %opc %spreg prefetch_done_noirq(); 01406d80 ffffff8f 0 stc.w ccr pr32h h - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(IR[1] >> 4) - 2; r32_w(IR[1] >> 4, TMP1); @@ -555,27 +576,27 @@ macro jsr32 %opc %spreg prefetch_done(); 01406f00 ffffff8f 0 ldc.w r32d16h ccr h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); CCR = read16(TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 01406f80 ffffff8f 0 stc.w ccr r32d16h h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); write16(TMP1, (CCR << 8) | CCR); prefetch_done(); 014078006b20 ffffff8fffff 0 ldc.w r32d32hh ccr h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; CCR = read16(TMP1) >> 8; update_irq_filter(); prefetch_done_noirq(); 014078806ba0 ffffff8fffff 0 stc.w ccr r32d32hh h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; write16(TMP1, (CCR << 8) | CCR); prefetch_done(); @@ -583,64 +604,64 @@ macro jsr32 %opc %spreg 01410400 ffffff00 0 orc imm8 exr s20 EXR |= IR[1]; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 01410500 ffffff00 0 xorc imm8 exr s20 EXR ^= IR[1] & ~EXR_NC; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 01410600 ffffff00 0 andc imm8 exr s20 EXR &= IR[1] | EXR_NC; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 01410700 ffffff00 0 ldc imm8 exr s20 EXR = IR[1] | EXR_NC; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 01416900 ffffff8f 0 ldc.w r32ih exr s20 - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4); EXR = (read16(TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 01416980 ffffff8f 0 stc.w exr r32ih s20 - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4); write16(TMP1, (EXR << 8) | EXR); prefetch_done(); 01416b00 ffffffff 0 ldc.w abs16 exr s20 - prefetch_start(); + prefetch_start TMP1 = int16_t(IR[2]); EXR = (read16(TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 01416b20 ffffffff 0 ldc.w abs32 exr s20 - prefetch_start(); + prefetch_start TMP1 = (IR[2] << 16) | IR[3]; EXR = (read16(TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 01416b80 ffffffff 0 stc.w exr abs16 s20 - prefetch_start(); + prefetch_start TMP1 = int16_t(IR[2]); write16(TMP1, (EXR << 8) | EXR); prefetch_done(); 01416ba0 ffffffff 0 stc.w exr abs32 s20 - prefetch_start(); + prefetch_start TMP1 = (IR[2] << 16) | IR[3]; write16(TMP1, (EXR << 8) | EXR); prefetch_done(); 01416d00 ffffff8f 0 ldc.w r32ph exr s20 - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(IR[1] >> 4); r32_w(IR[1] >> 4, TMP1+2); @@ -649,7 +670,7 @@ macro jsr32 %opc %spreg prefetch_done_noirq(); 01416d80 ffffff8f 0 stc.w exr pr32h s20 - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(IR[1] >> 4) - 2; r32_w(IR[1] >> 4, TMP1); @@ -657,33 +678,33 @@ macro jsr32 %opc %spreg prefetch_done(); 01416f00 ffffff8f 0 ldc.w r32d16h exr s20 - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); EXR = (read16(TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 01416f80 ffffff8f 0 stc.w exr r32d16h s20 - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + int16_t(IR[2]); write16(TMP1, (EXR << 8) | EXR); prefetch_done(); 014178006b20 ffffff8fffff 0 ldc.w r32d32hh exr s20 - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; EXR = (read16(TMP1) >> 8) | EXR_NC; update_irq_filter(); prefetch_done_noirq(); 014178806ba0 ffffff8fffff 0 stc.w exr r32d32hh s20 - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4) + (IR[3] << 16) + IR[4]; write16(TMP1, (EXR << 8) | EXR); prefetch_done(); 01606d00 ffffff88 0 mac r32ph r32pl s26 - prefetch_start(); + prefetch_start TMP1 = read16(r32_r(IR[1])); r32_w(IR[1], r32_r(IR[1]) + 2); TMP2 = read16(r32_r(IR[1] >> 4)); @@ -714,21 +735,21 @@ macro jsr32 %opc %spreg prefetch_done(); 0180 ffff 0 sleep - - - prefetch_start(); + prefetch_start while(!irq_vector) { eat-all-cycles; } prefetch_done(); 01a0 ffff 0 clrmac - - s26 - prefetch_start(); + prefetch_start internal(1); MAC = 0; MACF &= ~F_V; prefetch_done(); 01c05000 ffffff00 0 mulxs.b r8h r16l h - prefetch_start(); + prefetch_start TMP1 = int8_t(r16_r(IR[1])) * int8_t(r8_r(IR[1] >> 4)); set_nz16(TMP1); r16_w(IR[1], TMP1); @@ -736,7 +757,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01c05200 ffffff08 0 mulxs.w r16h r32l h - prefetch_start(); + prefetch_start TMP1 = int16_t(r32_r(IR[1])) * int16_t(r16_r(IR[1] >> 4)); set_nz32(TMP1); r32_w(IR[1], TMP1); @@ -744,7 +765,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01d05100 ffffff00 0 divxs.b r8h r16l h - prefetch_start(); + prefetch_start internal(11); TMP1 = int16_t(r16_r(IR[1])); TMP2 = int8_t(r8_r(IR[1] >> 4)); @@ -793,7 +814,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01d05300 ffffff08 0 divxs.w r16h r32l h - prefetch_start(); + prefetch_start internal(19); TMP1 = r32_r(IR[1]); TMP2 = int16_t(r16_r(IR[1] >> 4)); @@ -842,7 +863,7 @@ macro jsr32 %opc %spreg prefetch_done(); 01e07b0c ffffffaf 0 tas r32ih - s20 - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[1] >> 4); TMP2 = read8(TMP1); set_nzv8(TMP2); @@ -853,50 +874,50 @@ macro jsr32 %opc %spreg TMP1 = r32_r(IR[1] >> 4) | r32_r(IR[1]); set_nzv32(TMP1); r32_w(IR[1], TMP1); - prefetch(); + prefetch 01f06500 ffffff88 0 xor.l r32h r32l h TMP1 = r32_r(IR[1] >> 4) ^ r32_r(IR[1]); set_nzv32(TMP1); r32_w(IR[1], TMP1); - prefetch(); + prefetch 01f06600 ffffff88 0 and.l r32h r32l h TMP1 = r32_r(IR[1] >> 4) & r32_r(IR[1]); set_nzv32(TMP1); r32_w(IR[1], TMP1); - prefetch(); + prefetch 0200 fff0 0 stc ccr r8l r8_w(IR[0], CCR); - prefetch(); + prefetch 0210 fff0 0 stc exr r8l s20 r8_w(IR[0], EXR); - prefetch(); + prefetch 0220 fff8 0 stmac mach r32l s26 r32_w(IR[0], MAC >> 32); CCR = (CCR & ~(F_V|F_N|F_Z)) | MACF; - prefetch(); + prefetch 0230 fff8 0 stmac macl r32l s26 r32_w(IR[0], MAC); CCR = (CCR & ~(F_V|F_N|F_Z)) | MACF; - prefetch(); + prefetch 0300 fff0 0 ldc r8l ccr CCR = r8_r(IR[0]); update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 0310 fff0 0 ldc r8l exr s20 EXR = r8_r(IR[0]) | EXR_NC; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 0320 fff8 0 ldmac r32l mach s26 - prefetch_start(); + prefetch_start internal(1); TMP1 = r32_r(IR[0]); if(TMP1 & 0x200) @@ -908,7 +929,7 @@ macro jsr32 %opc %spreg prefetch_done(); 0330 fff8 0 ldmac r32l macl s26 - prefetch_start(); + prefetch_start internal(1); MAC = (MAC & 0xffffffff00000000ULL) | r32_r(IR[0]); MACF &= ~F_V; @@ -917,94 +938,94 @@ macro jsr32 %opc %spreg 0400 ff00 0 orc imm8 ccr CCR |= IR[0]; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 0500 ff00 0 xorc imm8 ccr CCR ^= IR[0]; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 0600 ff00 0 andc imm8 ccr CCR &= IR[0]; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 0700 ff00 0 ldc imm8 ccr CCR = IR[0]; update_irq_filter(); - prefetch_noirq(); + prefetch_noirq 0800 ff00 0 add.b r8h r8l r8_w(IR[0], do_add8(r8_r(IR[0]), r8_r(IR[0] >> 4))); - prefetch(); + prefetch 0900 ff00 0 add.w r16h r16l r16_w(IR[0], do_add16(r16_r(IR[0]), r16_r(IR[0] >> 4))); - prefetch(); + prefetch 0a00 fff0 0 inc.b one r8l r8_w(IR[0], do_inc8(r8_r(IR[0]), 1)); - prefetch(); + prefetch 0a80 ff88 0 add.l r32h r32l h r32_w(IR[0], do_add32(r32_r(IR[0]), r32_r(IR[0] >> 4))); - prefetch(); + prefetch 0b00 fff8 0 adds.l one r16l o r16_w(IR[0], r16_r(IR[0])+1); - prefetch(); + prefetch 0b00 fff8 0 adds.l one r32l h r32_w(IR[0], r32_r(IR[0])+1); - prefetch(); + prefetch 0b50 fff0 0 inc.w one r16l h r16_w(IR[0], do_inc16(r16_r(IR[0]), 1)); - prefetch(); + prefetch 0b70 fff8 0 inc.l one r32l h r32_w(IR[0], do_inc32(r32_r(IR[0]), 1)); - prefetch(); + prefetch 0b80 fff8 0 adds.l two r16l o r16_w(IR[0], r16_r(IR[0])+2); - prefetch(); + prefetch 0b80 fff8 0 adds.l two r32l h r32_w(IR[0], r32_r(IR[0])+2); - prefetch(); + prefetch 0b90 fff8 0 adds.l four r16l o r16_w(IR[0], r16_r(IR[0])+4); - prefetch(); + prefetch 0b90 fff8 0 adds.l four r32l h r32_w(IR[0], r32_r(IR[0])+4); - prefetch(); + prefetch 0bd0 fff0 0 inc.w two r16l h r16_w(IR[0], do_inc16(r16_r(IR[0]), 2)); - prefetch(); + prefetch 0bf0 fff8 0 inc.l two r32l h r32_w(IR[0], do_inc32(r32_r(IR[0]), 2)); - prefetch(); + prefetch 0c00 ff00 0 mov.b r8h r8l TMP1 = r8_r(IR[0] >> 4); set_nzv8(TMP1); r8_w(IR[0], TMP1); - prefetch(); + prefetch 0d00 ff00 0 mov.w r16h r16l TMP1 = r16_r(IR[0] >> 4); set_nzv16(TMP1); r16_w(IR[0], TMP1); - prefetch(); + prefetch 0e00 ff00 0 addx.b r8h r8l r8_w(IR[0], do_addx8(r8_r(IR[0]), r8_r(IR[0] >> 4))); - prefetch(); + prefetch 0f00 fff0 0 daa.b r8l - TMP1 = r8_r(IR[0]); @@ -1029,241 +1050,241 @@ macro jsr32 %opc %spreg } } r8_w(IR[0], do_add8(TMP1, TMP2)); - prefetch(); + prefetch 0f80 ff88 0 mov.l r32h r32l h TMP1 = r32_r(IR[0] >> 4); set_nzv32(TMP1); r32_w(IR[0], TMP1); - prefetch(); + prefetch 1000 fff0 0 shll.b r8l - r8_w(IR[0], do_shll8(r8_r(IR[0]))); - prefetch(); + prefetch 1010 fff0 0 shll.w r16l - h r16_w(IR[0], do_shll16(r16_r(IR[0]))); - prefetch(); + prefetch 1030 fff8 0 shll.l r32l - h r32_w(IR[0], do_shll32(r32_r(IR[0]))); - prefetch(); + prefetch 1040 fff0 0 shll.b two r8l s20 r8_w(IR[0], do_shll2_8(r8_r(IR[0]))); - prefetch(); + prefetch 1050 fff0 0 shll.w two r16l s20 r16_w(IR[0], do_shll2_16(r16_r(IR[0]))); - prefetch(); + prefetch 1070 fff8 0 shll.l two r32l s20 r32_w(IR[0], do_shll2_32(r32_r(IR[0]))); - prefetch(); + prefetch 1080 fff0 0 shal.b r8l - r8_w(IR[0], do_shal8(r8_r(IR[0]))); - prefetch(); + prefetch 1090 fff0 0 shal.w r16l - h r16_w(IR[0], do_shal16(r16_r(IR[0]))); - prefetch(); + prefetch 10b0 fff8 0 shal.l r32l - h r32_w(IR[0], do_shal32(r32_r(IR[0]))); - prefetch(); + prefetch 10c0 fff0 0 shal.b two r8l s20 r8_w(IR[0], do_shal2_8(r8_r(IR[0]))); - prefetch(); + prefetch 10d0 fff0 0 shal.w two r16l s20 r16_w(IR[0], do_shal2_16(r16_r(IR[0]))); - prefetch(); + prefetch 10f0 fff8 0 shal.l two r32l s20 r32_w(IR[0], do_shal2_32(r32_r(IR[0]))); - prefetch(); + prefetch 1100 fff0 0 shlr.b r8l - r8_w(IR[0], do_shlr8(r8_r(IR[0]))); - prefetch(); + prefetch 1110 fff0 0 shlr.w r16l - h r16_w(IR[0], do_shlr16(r16_r(IR[0]))); - prefetch(); + prefetch 1130 fff8 0 shlr.l r32l - h r32_w(IR[0], do_shlr32(r32_r(IR[0]))); - prefetch(); + prefetch 1140 fff0 0 shlr.b two r8l s20 r8_w(IR[0], do_shlr2_8(r8_r(IR[0]))); - prefetch(); + prefetch 1150 fff0 0 shlr.w two r16l s20 r16_w(IR[0], do_shlr2_16(r16_r(IR[0]))); - prefetch(); + prefetch 1170 fff8 0 shlr.l two r32l s20 r32_w(IR[0], do_shlr2_32(r32_r(IR[0]))); - prefetch(); + prefetch 1180 fff0 0 shar.b r8l - r8_w(IR[0], do_shar8(r8_r(IR[0]))); - prefetch(); + prefetch 1190 fff0 0 shar.w r16l - h r16_w(IR[0], do_shar16(r16_r(IR[0]))); - prefetch(); + prefetch 11b0 fff8 0 shar.l r32l - h r32_w(IR[0], do_shar32(r32_r(IR[0]))); - prefetch(); + prefetch 11c0 fff0 0 shar.b two r8l s20 r8_w(IR[0], do_shar2_8(r8_r(IR[0]))); - prefetch(); + prefetch 11d0 fff0 0 shar.w two r16l s20 r16_w(IR[0], do_shar2_16(r16_r(IR[0]))); - prefetch(); + prefetch 11f0 fff8 0 shar.l two r32l s20 r32_w(IR[0], do_shar2_32(r32_r(IR[0]))); - prefetch(); + prefetch 1200 fff0 0 rotxl.b r8l - r8_w(IR[0], do_rotxl8(r8_r(IR[0]))); - prefetch(); + prefetch 1210 fff0 0 rotxl.w r16l - h r16_w(IR[0], do_rotxl16(r16_r(IR[0]))); - prefetch(); + prefetch 1230 fff8 0 rotxl.l r32l - h r32_w(IR[0], do_rotxl32(r32_r(IR[0]))); - prefetch(); + prefetch 1240 fff0 0 rotxl.b two r8l s20 r8_w(IR[0], do_rotxl2_8(r8_r(IR[0]))); - prefetch(); + prefetch 1250 fff0 0 rotxl.w two r16l s20 r16_w(IR[0], do_rotxl2_16(r16_r(IR[0]))); - prefetch(); + prefetch 1270 fff8 0 rotxl.l two r32l s20 r32_w(IR[0], do_rotxl2_32(r32_r(IR[0]))); - prefetch(); + prefetch 1280 fff0 0 rotl.b r8l - r8_w(IR[0], do_rotl8(r8_r(IR[0]))); - prefetch(); + prefetch 1290 fff0 0 rotl.w r16l - h r16_w(IR[0], do_rotl16(r16_r(IR[0]))); - prefetch(); + prefetch 12b0 fff8 0 rotl.l r32l - h r32_w(IR[0], do_rotl32(r32_r(IR[0]))); - prefetch(); + prefetch 12c0 fff0 0 rotl.b two r8l s20 r8_w(IR[0], do_rotl2_8(r8_r(IR[0]))); - prefetch(); + prefetch 12d0 fff0 0 rotl.w two r16l s20 r16_w(IR[0], do_rotl2_16(r16_r(IR[0]))); - prefetch(); + prefetch 12f0 fff8 0 rotl.l two r32l s20 r32_w(IR[0], do_rotl2_32(r32_r(IR[0]))); - prefetch(); + prefetch 1300 fff0 0 rotxr.b r8l - r8_w(IR[0], do_rotxr8(r8_r(IR[0]))); - prefetch(); + prefetch 1310 fff0 0 rotxr.w r16l - h r16_w(IR[0], do_rotxr16(r16_r(IR[0]))); - prefetch(); + prefetch 1330 fff8 0 rotxr.l r32l - h r32_w(IR[0], do_rotxr32(r32_r(IR[0]))); - prefetch(); + prefetch 1340 fff0 0 rotxr.b two r8l s20 r8_w(IR[0], do_rotxr2_8(r8_r(IR[0]))); - prefetch(); + prefetch 1350 fff0 0 rotxr.w two r16l s20 r16_w(IR[0], do_rotxr2_16(r16_r(IR[0]))); - prefetch(); + prefetch 1370 fff8 0 rotxr.l two r32l s20 r32_w(IR[0], do_rotxr2_32(r32_r(IR[0]))); - prefetch(); + prefetch 1380 fff0 0 rotr.b r8l - r8_w(IR[0], do_rotr8(r8_r(IR[0]))); - prefetch(); + prefetch 1390 fff0 0 rotr.w r16l - h r16_w(IR[0], do_rotr16(r16_r(IR[0]))); - prefetch(); + prefetch 13b0 fff8 0 rotr.l r32l - h r32_w(IR[0], do_rotr32(r32_r(IR[0]))); - prefetch(); + prefetch 13c0 fff0 0 rotr.b two r8l s20 r8_w(IR[0], do_rotr2_8(r8_r(IR[0]))); - prefetch(); + prefetch 13d0 fff0 0 rotr.w two r16l s20 r16_w(IR[0], do_rotr2_16(r16_r(IR[0]))); - prefetch(); + prefetch 13f0 fff8 0 rotr.l two r32l s20 r32_w(IR[0], do_rotr2_32(r32_r(IR[0]))); - prefetch(); + prefetch 1400 ff00 0 or.b r8h r8l TMP1 = r8_r(IR[0] >> 4) | r8_r(IR[0]); set_nzv8(TMP1); r8_w(IR[0], TMP1); - prefetch(); + prefetch 1500 ff00 0 xor.b r8h r8l TMP1 = r8_r(IR[0] >> 4) ^ r8_r(IR[0]); set_nzv8(TMP1); r8_w(IR[0], TMP1); - prefetch(); + prefetch 1600 ff00 0 and.b r8h r8l TMP1 = r8_r(IR[0] >> 4) & r8_r(IR[0]); set_nzv8(TMP1); r8_w(IR[0], TMP1); - prefetch(); + prefetch 1700 fff0 0 not.b r8l - TMP1 = ~r8_r(IR[0]); set_nzv8(TMP1); r8_w(IR[0], TMP1); - prefetch(); + prefetch 1710 fff0 0 not.w r16l - h TMP1 = ~r16_r(IR[0]); set_nzv16(TMP1); r16_w(IR[0], TMP1); - prefetch(); + prefetch 1730 fff8 0 not.l r32l - h TMP1 = ~r32_r(IR[0]); set_nzv32(TMP1); r32_w(IR[0], TMP1); - prefetch(); + prefetch 1750 fff0 0 extu.w r16l - h CCR &= ~(F_N|F_Z|F_V); @@ -1271,7 +1292,7 @@ macro jsr32 %opc %spreg if(!TMP1) CCR |= F_Z; r16_w(IR[0], TMP1); - prefetch(); + prefetch 1770 fff8 0 extu.l r32l - h CCR &= ~(F_N|F_Z|F_V); @@ -1279,19 +1300,19 @@ macro jsr32 %opc %spreg if(!TMP1) CCR |= F_Z; r32_w(IR[0], TMP1); - prefetch(); + prefetch 1780 fff0 0 neg.b r8l - r8_w(IR[0], do_sub8(0, r8_r(IR[0]))); - prefetch(); + prefetch 1790 fff0 0 neg.w r16l - h r16_w(IR[0], do_sub16(0, r16_r(IR[0]))); - prefetch(); + prefetch 17b0 fff8 0 neg.l r32l - h r32_w(IR[0], do_sub32(0, r32_r(IR[0]))); - prefetch(); + prefetch 17d0 fff0 0 exts.w r16l - h CCR &= ~(F_N|F_Z|F_V); @@ -1299,7 +1320,7 @@ macro jsr32 %opc %spreg if(!TMP1) CCR |= F_Z; r16_w(IR[0], TMP1); - prefetch(); + prefetch 17f0 fff8 0 exts.l r32l - h CCR &= ~(F_N|F_Z|F_V); @@ -1307,75 +1328,75 @@ macro jsr32 %opc %spreg if(!TMP1) CCR |= F_Z; r32_w(IR[0], TMP1); - prefetch(); + prefetch 1800 ff00 0 sub.b r8h r8l r8_w(IR[0], do_sub8(r8_r(IR[0]), r8_r(IR[0] >> 4))); - prefetch(); + prefetch 1900 ff00 0 sub.w r16h r16l r16_w(IR[0], do_sub16(r16_r(IR[0]), r16_r(IR[0] >> 4))); - prefetch(); + prefetch 1a00 fff0 0 dec.b one r8l r8_w(IR[0], do_dec8(r8_r(IR[0]), 1)); - prefetch(); + prefetch 1a80 ff88 0 sub.l r32h r32l h r32_w(IR[0], do_sub32(r32_r(IR[0]), r32_r(IR[0] >> 4))); - prefetch(); + prefetch 1b00 fff8 0 subs.l one r16l o r16_w(IR[0], r16_r(IR[0])-1); - prefetch(); + prefetch 1b00 fff8 0 subs.l one r32l h r32_w(IR[0], r32_r(IR[0])-1); - prefetch(); + prefetch 1b50 fff0 0 dec.w one r16l r16_w(IR[0], do_dec16(r16_r(IR[0]), 1)); - prefetch(); + prefetch 1b70 fff8 0 dec.l one r32l h r32_w(IR[0], do_dec32(r32_r(IR[0]), 1)); - prefetch(); + prefetch 1b80 fff8 0 subs.l two r16l o r16_w(IR[0], r16_r(IR[0])-2); - prefetch(); + prefetch 1b80 fff8 0 subs.l two r32l h r32_w(IR[0], r32_r(IR[0])-2); - prefetch(); + prefetch 1b90 fff8 0 subs.l four r16l o r16_w(IR[0], r16_r(IR[0])-4); - prefetch(); + prefetch 1b90 fff8 0 subs.l four r32l h r32_w(IR[0], r32_r(IR[0])-4); - prefetch(); + prefetch 1bd0 fff0 0 dec.w two r16l r16_w(IR[0], do_dec16(r16_r(IR[0]), 2)); - prefetch(); + prefetch 1bf0 fff8 0 dec.l two r32l h r32_w(IR[0], do_dec32(r32_r(IR[0]), 2)); - prefetch(); + prefetch 1c00 ff00 0 cmp.b r8h r8l do_sub8(r8_r(IR[0]), r8_r(IR[0] >> 4)); - prefetch(); + prefetch 1d00 ff00 0 cmp.w r16h r16l do_sub16(r16_r(IR[0]), r16_r(IR[0] >> 4)); - prefetch(); + prefetch 1e00 ff00 0 subx.b r8h r8l r8_w(IR[0], do_subx8(r8_r(IR[0]), r8_r(IR[0] >> 4))); - prefetch(); + prefetch 1f00 fff0 0 das.b r8l - TMP1 = r8_r(IR[0]); @@ -1395,21 +1416,21 @@ macro jsr32 %opc %spreg } } r8_w(IR[0], do_add8(TMP1, TMP2)); - prefetch(); + prefetch 1f80 ff88 0 cmp.l r32h r32l h do_sub32(r32_r(IR[0]), r32_r(IR[0] >> 4)); - prefetch(); + prefetch 2000 f000 0 mov.b abs8 r8u - prefetch_start(); + prefetch_start TMP1 = read8(0xffffff00 | IR[0]); set_nzv8(TMP1); r8_w(IR[0] >> 8, TMP1); prefetch_done(); 3000 f000 0 mov.b r8u abs8 - prefetch_start(); + prefetch_start TMP1 = r8_r(IR[0] >> 8); set_nzv8(TMP1); write8(0xffffff00 | IR[0], TMP1); @@ -1464,13 +1485,13 @@ macro jsr32 %opc %spreg bxx_8 (CCR & F_Z) || (CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V 5000 ff00 0 mulxu.b r8h r16l - prefetch_start(); + prefetch_start r16_w(IR[0], uint8_t(r16_r(IR[0])) * r8_r(IR[0] >> 4)); internal(has_mac ? 2 : 11); prefetch_done(); 5100 ff00 0 divxu.b r8h r16l - prefetch_start(); + prefetch_start internal(11); TMP1 = r16_r(IR[0]); TMP2 = r8_r(IR[0] >> 4); @@ -1487,13 +1508,13 @@ macro jsr32 %opc %spreg prefetch_done(); 5200 ff08 0 mulxu.w r16h r32l h - prefetch_start(); + prefetch_start r32_w(IR[0], uint16_t(r32_r(IR[0])) * r16_r(IR[0] >> 4)); internal(has_mac ? 3 : 19); prefetch_done(); 5300 ff08 0 divxu.w r16h r32l h - prefetch_start(); + prefetch_start internal(11); TMP1 = r32_r(IR[0]); TMP2 = r16_r(IR[0] >> 4); @@ -1510,16 +1531,16 @@ macro jsr32 %opc %spreg prefetch_done(); 5470 ffff 0 rts - - o - fetch(); + fetch TMP1 = r16_r(7); TMP2 = read16(TMP1); r16_w(7, TMP1+2); internal(1); PC = TMP2; - prefetch(); + prefetch 5470 ffff 0 rts - - h - fetch(); + fetch TMP1 = r32_r(7); if(mode_advanced) { TMP2 = read16(TMP1) << 16; @@ -1531,7 +1552,7 @@ macro jsr32 %opc %spreg } internal(1); PC = TMP2; - prefetch(); + prefetch 5500 ff00 0 bsr rel8 - o TMP2 = PC; @@ -1544,7 +1565,7 @@ macro jsr32 %opc %spreg jsr32 TMP2 TMP1 5670 ffff 0 rte - - o - fetch(); + fetch TMP1 = r16_r(7); CCR = read16(TMP1) >> 8; TMP1 = r16_r(7); @@ -1553,10 +1574,10 @@ macro jsr32 %opc %spreg internal(1); PC = TMP2; update_irq_filter(); - prefetch_noirq_notrace(); + prefetch_noirq_notrace 5670 ffff 0 rte - - h - fetch(); + fetch TMP1 = r32_r(7); if(mode_advanced) { if(exr_in_stack()) { @@ -1575,7 +1596,7 @@ macro jsr32 %opc %spreg internal(1); PC = TMP2; update_irq_filter(); - prefetch_noirq_notrace(); + prefetch_noirq_notrace 5700 ffcf 0 trapa imm2 - h internal(1); @@ -1601,7 +1622,7 @@ macro jsr32 %opc %spreg } internal(1); update_irq_filter(); - prefetch(); + prefetch 5800 ffff 0 bt rel16 - h bxx_16 true @@ -1652,33 +1673,33 @@ macro jsr32 %opc %spreg bxx_16 (CCR & F_Z) || (CCR & (F_N|F_V)) == F_N || (CCR & (F_N|F_V)) == F_V 5900 ff8f 0 jmp r16h - o - fetch(); + fetch PC = r16_r(IR[0] >> 4); - prefetch(); + prefetch 5900 ff8f 0 jmp r32h - h - fetch(); + fetch PC = r32_r(IR[0] >> 4); - prefetch(); + prefetch 5a00 ffff 0 jmp abs16e - o internal(1); PC = IR[1]; - prefetch(); + prefetch 5a00 ff00 0 jmp abs24e - h internal(1); PC = ((IR[0] & 0xff) << 16) | IR[1]; - prefetch(); + prefetch 5b00 ff00 0 jmp abs8i - o - fetch(); + fetch PC = read16(IR[0] & 0xff); internal(1); - prefetch(); + prefetch 5b00 ff00 0 jmp abs8i - h - fetch(); + fetch if(mode_advanced) { TMP1 = read16(IR[0] & 0xff) << 16; TMP1 |= read16((IR[0] & 0xff) + 2); @@ -1687,7 +1708,7 @@ macro jsr32 %opc %spreg PC = read16(IR[0] & 0xff); } internal(1); - prefetch(); + prefetch 5c00 ffff 0 bsr rel16 - h internal(1); @@ -1718,13 +1739,13 @@ macro jsr32 %opc %spreg jsr32 TMP2 TMP1 5f00 ff00 0 jsr abs8i - o - fetch(); + fetch TMP2 = PC; PC = read16(IR[0] & 0xff); jsr16 TMP2 TMP1 5f00 ff00 0 jsr abs8i - h - fetch(); + fetch TMP2 = PC; if(mode_advanced) { TMP1 = read16(IR[0] & 0xff) << 16; @@ -1739,113 +1760,113 @@ macro jsr32 %opc %spreg TMP1 = r8_r(IR[0]); bset r8_r(IR[0] >> 4) r8_w(IR[0], TMP1); - prefetch(); + prefetch 6100 ff00 0 bnot r8h r8l TMP1 = r8_r(IR[0]); bnot r8_r(IR[0] >> 4) r8_w(IR[0], TMP1); - prefetch(); + prefetch 6200 ff00 0 bclr r8h r8l TMP1 = r8_r(IR[0]); bclr r8_r(IR[0] >> 4) r8_w(IR[0], TMP1); - prefetch(); + prefetch 6300 ff00 0 btst r8h r8l TMP1 = r8_r(IR[0]); btst r8_r(IR[0] >> 4) - prefetch(); + prefetch 6400 ff00 0 or.w r16h r16l h TMP1 = r16_r(IR[0] >> 4) | r16_r(IR[0]); set_nzv16(TMP1); r16_w(IR[0], TMP1); - prefetch(); + prefetch 6500 ff00 0 xor.w r16h r16l h TMP1 = r16_r(IR[0] >> 4) ^ r16_r(IR[0]); set_nzv16(TMP1); r16_w(IR[0], TMP1); - prefetch(); + prefetch 6600 ff00 0 and.w r16h r16l h TMP1 = r16_r(IR[0] >> 4) & r16_r(IR[0]); set_nzv16(TMP1); r16_w(IR[0], TMP1); - prefetch(); + prefetch 6700 ff80 0 bst imm3 r8l TMP1 = r8_r(IR[0]); bst IR[0] >> 4 r8_w(IR[0], TMP1); - prefetch(); + prefetch 6780 ff80 0 bist imm3 r8l TMP1 = r8_r(IR[0]); bist IR[0] >> 4 r8_w(IR[0], TMP1); - prefetch(); + prefetch 6800 ff80 0 mov.b r16ih r8l o - prefetch_start(); + prefetch_start TMP1 = read8(r16_r(IR[0] >> 4)); set_nzv8(TMP1); r8_w(IR[0], TMP1); prefetch_done(); 6800 ff80 0 mov.b r32ih r8l h - prefetch_start(); + prefetch_start TMP1 = read8(r32_r(IR[0] >> 4)); set_nzv8(TMP1); r8_w(IR[0], TMP1); prefetch_done(); 6880 ff80 0 mov.b r8l r16ih o - prefetch_start(); + prefetch_start TMP1 = r8_r(IR[0]); set_nzv8(TMP1); write8(r16_r((IR[0] >> 4) & 7), TMP1); prefetch_done(); 6880 ff80 0 mov.b r8l r32ih h - prefetch_start(); + prefetch_start TMP1 = r8_r(IR[0]); set_nzv8(TMP1); write8(r32_r(IR[0] >> 4), TMP1); prefetch_done(); 6900 ff88 0 mov.w r16ih r16l o - prefetch_start(); + prefetch_start TMP1 = read16(r16_r(IR[0] >> 4)); set_nzv16(TMP1); r16_w(IR[0], TMP1); prefetch_done(); 6900 ff80 0 mov.w r32ih r16l h - prefetch_start(); + prefetch_start TMP1 = read16(r32_r(IR[0] >> 4)); set_nzv16(TMP1); r16_w(IR[0], TMP1); prefetch_done(); 6980 ff88 0 mov.w r16l r16ih o - prefetch_start(); + prefetch_start TMP1 = r16_r(IR[0]); set_nzv16(TMP1); write16(r16_r((IR[0] >> 4) & 7), TMP1); prefetch_done(); 6980 ff80 0 mov.w r16l r32ih h - prefetch_start(); + prefetch_start TMP1 = r16_r(IR[0]); set_nzv16(TMP1); write16(r32_r(IR[0] >> 4), TMP1); prefetch_done(); 6a00 fff0 0 mov.b abs16 r8l - prefetch_start(); + prefetch_start TMP1 = read8(int16_t(IR[1])); set_nzv8(TMP1); r8_w(IR[0], TMP1); @@ -1855,66 +1876,66 @@ macro jsr32 %opc %spreg TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); btst r8_r(IR[2] >> 4) - prefetch(); + prefetch 6a107300 ffffff8f 1 btst imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); btst IR[2] >> 4 - prefetch(); + prefetch 6a107400 ffffff8f 1 bor imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); bor IR[2] >> 4 - prefetch(); + prefetch 6a107480 ffffff8f 1 bior imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); bior IR[2] >> 4 - prefetch(); + prefetch 6a107500 ffffff8f 1 bxor imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); bxor IR[2] >> 4 - prefetch(); + prefetch 6a107580 ffffff8f 1 bixor imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); bixor IR[2] >> 4 - prefetch(); + prefetch 6a107600 ffffff8f 1 band imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); band IR[2] >> 4 - prefetch(); + prefetch 6a107680 ffffff8f 1 biand imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); biand IR[2] >> 4 - prefetch(); + prefetch 6a107700 ffffff8f 1 bld imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); bld IR[2] >> 4 - prefetch(); + prefetch 6a107780 ffffff8f 1 bild imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); bild IR[2] >> 4 - prefetch(); + prefetch 6a186000 ffffff0f 1 bset r8h abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bset r8_r(IR[2] >> 4) write8(TMP2, TMP1); prefetch_done(); @@ -1922,7 +1943,7 @@ macro jsr32 %opc %spreg 6a186100 ffffff0f 1 bnot r8h abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bnot r8_r(IR[2] >> 4) write8(TMP2, TMP1); prefetch_done(); @@ -1930,7 +1951,7 @@ macro jsr32 %opc %spreg 6a186200 ffffff0f 1 bclr r8h abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bclr r8_r(IR[2] >> 4) write8(TMP2, TMP1); prefetch_done(); @@ -1938,7 +1959,7 @@ macro jsr32 %opc %spreg 6a186700 ffffff8f 1 bst imm3 abs16 TMP2 = int16_t(IR[2]); TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bst IR[2] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -1946,7 +1967,7 @@ macro jsr32 %opc %spreg 6a186780 ffffff8f 1 bist imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bist IR[2] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -1954,7 +1975,7 @@ macro jsr32 %opc %spreg 6a187000 ffffff8f 1 bset imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bset IR[2] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -1962,7 +1983,7 @@ macro jsr32 %opc %spreg 6a187100 ffffff8f 1 bnot imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bnot IR[2] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -1970,13 +1991,13 @@ macro jsr32 %opc %spreg 6a187200 ffffff8f 1 bclr imm3 abs16 TMP2 = int16_t(IR[1]); TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bclr IR[2] >> 4 write8(TMP2, TMP1); prefetch_done(); 6a20 fff0 0 mov.b abs32 r8l h - prefetch_start(); + prefetch_start TMP1 = read8((IR[1] << 16) | IR[2]); set_nzv8(TMP1); r8_w(IR[0], TMP1); @@ -1986,66 +2007,66 @@ macro jsr32 %opc %spreg TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); btst r8_r(IR[3] >> 4) - prefetch(); + prefetch 6a307300 ffffff8f 2 btst imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); btst IR[3] >> 4 - prefetch(); + prefetch 6a307400 ffffff8f 2 bor imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); bor IR[3] >> 4 - prefetch(); + prefetch 6a307480 ffffff8f 2 bior imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); bior IR[3] >> 4 - prefetch(); + prefetch 6a307500 ffffff8f 2 bxor imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); bxor IR[3] >> 4 - prefetch(); + prefetch 6a307580 ffffff8f 2 bixor imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); bixor IR[3] >> 4 - prefetch(); + prefetch 6a307600 ffffff8f 2 band imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); band IR[3] >> 4 - prefetch(); + prefetch 6a307680 ffffff8f 2 biand imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); biand IR[3] >> 4 - prefetch(); + prefetch 6a307700 ffffff8f 2 bld imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); bld IR[3] >> 4 - prefetch(); + prefetch 6a307780 ffffff8f 2 bild imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); bild IR[3] >> 4 - prefetch(); + prefetch 6a386000 ffffff0f 2 bset r8h abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bset r8_r(IR[3] >> 4) write8(TMP2, TMP1); prefetch_done(); @@ -2053,7 +2074,7 @@ macro jsr32 %opc %spreg 6a386100 ffffff0f 2 bnot r8h abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bnot r8_r(IR[3] >> 4) write8(TMP2, TMP1); prefetch_done(); @@ -2061,7 +2082,7 @@ macro jsr32 %opc %spreg 6a386200 ffffff0f 2 bclr r8h abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bclr r8_r(IR[3] >> 4) write8(TMP2, TMP1); prefetch_done(); @@ -2069,7 +2090,7 @@ macro jsr32 %opc %spreg 6a386700 ffffff8f 2 bst imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bst IR[3] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -2077,7 +2098,7 @@ macro jsr32 %opc %spreg 6a386780 ffffff8f 2 bist imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bist IR[3] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -2085,7 +2106,7 @@ macro jsr32 %opc %spreg 6a387000 ffffff8f 2 bset imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bset IR[3] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -2093,7 +2114,7 @@ macro jsr32 %opc %spreg 6a387100 ffffff8f 2 bnot imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bnot IR[3] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -2101,21 +2122,21 @@ macro jsr32 %opc %spreg 6a387200 ffffff8f 2 bclr imm3 abs32 h TMP2 = (IR[1] << 16) | IR[2]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bclr IR[3] >> 4 write8(TMP2, TMP1); prefetch_done(); 6a40 fff0 0 movfpe abs16 r8l 6a80 fff0 0 mov.b r8l abs16 - prefetch_start(); + prefetch_start TMP1 = r8_r(IR[0]); set_nzv8(TMP1); write8(int16_t(IR[1]), TMP1); prefetch_done(); 6aa0 fff0 0 mov.b r8l abs32 h - prefetch_start(); + prefetch_start TMP1 = r8_r(IR[0]); set_nzv8(TMP1); write8((IR[1] << 16) | IR[2], TMP1); @@ -2123,28 +2144,28 @@ macro jsr32 %opc %spreg 6ac0 fff0 0 movtpe r8l abs16 6b00 fff0 0 mov.w abs16 r16l - prefetch_start(); + prefetch_start TMP1 = read16(int16_t(IR[1])); set_nzv16(TMP1); r16_w(IR[0], TMP1); prefetch_done(); 6b20 fff0 0 mov.w abs32 r16l h - prefetch_start(); + prefetch_start TMP1 = read16((IR[1] << 16) | IR[2]); set_nzv16(TMP1); r16_w(IR[0], TMP1); prefetch_done(); 6b80 fff0 0 mov.w r16l abs16 - prefetch_start(); + prefetch_start TMP1 = r16_r(IR[0]); set_nzv16(TMP1); write16(int16_t(IR[1]), TMP1); prefetch_done(); 6ba0 fff0 0 mov.w r16l abs32 h - prefetch_start(); + prefetch_start TMP1 = r16_r(IR[0]); set_nzv16(TMP1); write16((IR[1] << 16) | IR[2], TMP1); @@ -2152,7 +2173,7 @@ macro jsr32 %opc %spreg 6c00 ff80 0 mov.b r16ph r8l o TMP2 = r16_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(1); TMP1 = read8(TMP2); TMP2 += 1; @@ -2163,7 +2184,7 @@ macro jsr32 %opc %spreg 6c00 ff80 0 mov.b r32ph r8l h TMP2 = r32_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(1); TMP1 = read8(TMP2); TMP2 += 1; @@ -2175,7 +2196,7 @@ macro jsr32 %opc %spreg 6c80 ff80 0 mov.b r8l pr16h o TMP1 = r8_r(IR[0]); TMP2 = r16_r((IR[0] >> 4) & 7); - prefetch_start(); + prefetch_start internal(1); TMP2 -= 1; r16_w((IR[0] >> 4) & 7, TMP2); @@ -2186,7 +2207,7 @@ macro jsr32 %opc %spreg 6c80 ff80 0 mov.b r8l pr32h h TMP1 = r8_r(IR[0]); TMP2 = r32_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(1); TMP2 -= 1; r32_w(IR[0] >> 4, TMP2); @@ -2196,7 +2217,7 @@ macro jsr32 %opc %spreg 6d00 ff88 0 mov.w r16ph r16l o TMP2 = r16_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(1); TMP1 = read16(TMP2); TMP2 += 2; @@ -2207,7 +2228,7 @@ macro jsr32 %opc %spreg 6d00 ff80 0 mov.w r32ph r16l h TMP2 = r32_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(1); TMP1 = read16(TMP2); TMP2 += 2; @@ -2219,7 +2240,7 @@ macro jsr32 %opc %spreg 6d80 ff88 0 mov.w r16l pr16h o TMP1 = r16_r(IR[0]); TMP2 = r16_r((IR[0] >> 4) & 7); - prefetch_start(); + prefetch_start internal(1); TMP2 -= 2; r16_w((IR[0] >> 4) & 7, TMP2); @@ -2230,7 +2251,7 @@ macro jsr32 %opc %spreg 6d80 ff80 0 mov.w r16l pr32h h TMP1 = r16_r(IR[0]); TMP2 = r32_r(IR[0] >> 4); - prefetch_start(); + prefetch_start internal(1); TMP2 -= 2; r32_w(IR[0] >> 4, TMP2); @@ -2239,7 +2260,7 @@ macro jsr32 %opc %spreg prefetch_done(); 6e00 ff80 0 mov.b r16d16h r8l o - prefetch_start(); + prefetch_start TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); TMP2 = read8(TMP1); set_nzv8(TMP2); @@ -2247,7 +2268,7 @@ macro jsr32 %opc %spreg prefetch_done(); 6e00 ff80 0 mov.b r32d16h r8l h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[0] >> 4) + int16_t(IR[1]); TMP2 = read8(TMP1); set_nzv8(TMP2); @@ -2255,7 +2276,7 @@ macro jsr32 %opc %spreg prefetch_done(); 6e80 ff80 0 mov.b r8l r16d16h o - prefetch_start(); + prefetch_start TMP1 = uint16_t(r16_r((IR[0] >> 4) & 7) + IR[1]); TMP2 = r8_r(IR[0]); set_nzv8(TMP2); @@ -2263,7 +2284,7 @@ macro jsr32 %opc %spreg prefetch_done(); 6e80 ff80 0 mov.b r8l r32d16h h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[0] >> 4) + int16_t(IR[1]); TMP2 = r8_r(IR[0]); set_nzv8(TMP2); @@ -2271,7 +2292,7 @@ macro jsr32 %opc %spreg prefetch_done(); 6f00 ff80 0 mov.w r16d16h r16l o - prefetch_start(); + prefetch_start TMP1 = uint16_t(r16_r(IR[0] >> 4) + IR[1]); TMP2 = read16(TMP1); set_nzv16(TMP2); @@ -2279,7 +2300,7 @@ macro jsr32 %opc %spreg prefetch_done(); 6f00 ff80 0 mov.w r32d16h r16l h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[0] >> 4) + int16_t(IR[1]); TMP2 = read16(TMP1); set_nzv16(TMP2); @@ -2287,7 +2308,7 @@ macro jsr32 %opc %spreg prefetch_done(); 6f80 ff80 0 mov.w r16l r16d16h o - prefetch_start(); + prefetch_start TMP1 = uint16_t(r16_r((IR[0] >> 4) & 7) + IR[1]); TMP2 = r16_r(IR[0]); set_nzv16(TMP2); @@ -2295,7 +2316,7 @@ macro jsr32 %opc %spreg prefetch_done(); 6f80 ff80 0 mov.w r16l r32d16h h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[0] >> 4) + int16_t(IR[1]); TMP2 = r16_r(IR[0]); set_nzv16(TMP2); @@ -2306,67 +2327,67 @@ macro jsr32 %opc %spreg TMP1 = r8_r(IR[0]); bset IR[0] >> 4 r8_w(IR[0], TMP1); - prefetch(); + prefetch 7100 ff80 0 bnot imm3 r8l TMP1 = r8_r(IR[0]); bnot IR[0] >> 4 r8_w(IR[0], TMP1); - prefetch(); + prefetch 7200 ff80 0 bclr imm3 r8l TMP1 = r8_r(IR[0]); bclr IR[0] >> 4 r8_w(IR[0], TMP1); - prefetch(); + prefetch 7300 ff80 0 btst imm3 r8l TMP1 = r8_r(IR[0]); btst IR[0] >> 4 - prefetch(); + prefetch 7400 ff80 0 bor imm3 r8l TMP1 = r8_r(IR[0]); bor IR[0] >> 4 - prefetch(); + prefetch 7480 ff80 0 bior imm3 r8l TMP1 = r8_r(IR[0]); bior IR[0] >> 4 - prefetch(); + prefetch 7500 ff80 0 bxor imm3 r8l TMP1 = r8_r(IR[0]); bxor IR[0] >> 4 - prefetch(); + prefetch 7580 ff80 0 bixor imm3 r8l TMP1 = r8_r(IR[0]); bixor IR[0] >> 4 - prefetch(); + prefetch 7600 ff80 0 band imm3 r8l TMP1 = r8_r(IR[0]); band IR[0] >> 4 - prefetch(); + prefetch 7680 ff80 0 biand imm3 r8l TMP1 = r8_r(IR[0]); biand IR[0] >> 4 - prefetch(); + prefetch 7700 ff80 0 bld imm3 r8l TMP1 = r8_r(IR[0]); bld IR[0] >> 4 - prefetch(); + prefetch 7780 ff80 0 bild imm3 r8l TMP1 = r8_r(IR[0]); bild IR[0] >> 4 - prefetch(); + prefetch 78006a20 ff8ffff0 0 mov.b r32d32hh r8l h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[0] >> 4) + (IR[2] << 16) + IR[3]; TMP2 = read8(TMP1); set_nzv8(TMP2); @@ -2374,7 +2395,7 @@ macro jsr32 %opc %spreg prefetch_done(); 78006aa0 ff8ffff0 0 mov.b r8l r32d32hh h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[0] >> 4) + (IR[2] << 16) + IR[3]; TMP2 = r8_r(IR[1]); set_nzv8(TMP2); @@ -2382,7 +2403,7 @@ macro jsr32 %opc %spreg prefetch_done(); 78006b20 ff8ffff0 0 mov.w r32d32hh r16l h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[0] >> 4) + (IR[2] << 16) + IR[3]; TMP2 = read16(TMP1); set_nzv16(TMP2); @@ -2390,7 +2411,7 @@ macro jsr32 %opc %spreg prefetch_done(); 78006ba0 ff8ffff0 0 mov.w r16l r32d32hh h - prefetch_start(); + prefetch_start TMP1 = r32_r(IR[0] >> 4) + (IR[2] << 16) + IR[3]; TMP2 = r16_r(IR[1]); set_nzv16(TMP2); @@ -2400,73 +2421,73 @@ macro jsr32 %opc %spreg 7900 fff0 0 mov.w imm16 r16l set_nzv16(IR[1]); r16_w(IR[0], IR[1]); - prefetch(); + prefetch 7910 fff0 0 add.w imm16 r16l r16_w(IR[0], do_add16(r16_r(IR[0]), IR[1])); - prefetch(); + prefetch 7920 fff0 0 cmp.w imm16 r16l do_sub16(r16_r(IR[0]), IR[1]); - prefetch(); + prefetch 7930 fff0 0 sub.w imm16 r16l r16_w(IR[0], do_sub16(r16_r(IR[0]), IR[1])); - prefetch(); + prefetch 7940 fff0 0 or.w imm16 r16l TMP1 = IR[1] | r16_r(IR[0]); set_nzv16(TMP1); r16_w(IR[0], TMP1); - prefetch(); + prefetch 7950 fff0 0 xor.w imm16 r16l TMP1 = IR[1] ^ r16_r(IR[0]); set_nzv16(TMP1); r16_w(IR[0], TMP1); - prefetch(); + prefetch 7960 fff0 0 and.w imm16 r16l TMP1 = IR[1] & r16_r(IR[0]); set_nzv16(TMP1); r16_w(IR[0], TMP1); - prefetch(); + prefetch 7a00 fff8 0 mov.l imm32 r32l h TMP1 = (IR[1] << 16) | IR[2]; set_nzv32(TMP1); r32_w(IR[0], TMP1); - prefetch(); + prefetch 7a10 fff8 0 add.l imm32 r32l h r32_w(IR[0], do_add32(r32_r(IR[0]), (IR[1] << 16) | IR[2])); - prefetch(); + prefetch 7a20 fff8 0 cmp.l imm32 r32l h do_sub32(r32_r(IR[0]), (IR[1] << 16) | IR[2]); - prefetch(); + prefetch 7a30 fff8 0 sub.l imm32 r32l h r32_w(IR[0], do_sub32(r32_r(IR[0]), (IR[1] << 16) | IR[2])); - prefetch(); + prefetch 7a40 fff8 0 or.l imm32 r32l h TMP1 = r32_r(IR[0]) | ((IR[1] << 16) | IR[2]); set_nzv32(TMP1); r32_w(IR[0], TMP1); - prefetch(); + prefetch 7a50 fff8 0 xor.l imm32 r32l h TMP1 = r32_r(IR[0]) ^ ((IR[1] << 16) | IR[2]); set_nzv32(TMP1); r32_w(IR[0], TMP1); - prefetch(); + prefetch 7a60 fff8 0 and.l imm32 r32l h TMP1 = r32_r(IR[0]) & ((IR[1] << 16) | IR[2]); set_nzv32(TMP1); r32_w(IR[0], TMP1); - prefetch(); + prefetch 7b5c598f ffffffff 0 eepmov.b - - o while(r8_r(4+8)) { @@ -2476,7 +2497,7 @@ macro jsr32 %opc %spreg r16_w(6, r16_r(6)+1); r8_w(4+8, r8_r(4+8)-1); } - prefetch(); + prefetch 7b5c598f ffffffff 0 eepmov.b - - h while(r8_r(4+8)) { @@ -2486,7 +2507,7 @@ macro jsr32 %opc %spreg r32_w(6, r32_r(6)+1); r8_w(4+8, r8_r(4+8)-1); } - prefetch(); + prefetch 7bd4598f ffffffff 0 eepmov.w - - h while(r16_r(4)) { @@ -2496,133 +2517,133 @@ macro jsr32 %opc %spreg r32_w(6, r32_r(6)+1); r16_w(4, r16_r(4)-1); } - prefetch(); + prefetch 7c006300 ff8fff0f 0 btst r8h r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); btst r8_r(IR[1] >> 4) - prefetch(); + prefetch 7c006300 ff8fff0f 0 btst r8h r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); btst r8_r(IR[1] >> 4) - prefetch(); + prefetch 7c007300 ff8fff8f 0 btst imm3 r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); btst IR[1] >> 4 - prefetch(); + prefetch 7c007300 ff8fff8f 0 btst imm3 r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); btst IR[1] >> 4 - prefetch(); + prefetch 7c007400 ff8fff8f 0 bor imm3 r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bor IR[1] >> 4 - prefetch(); + prefetch 7c007400 ff8fff8f 0 bor imm3 r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bor IR[1] >> 4 - prefetch(); + prefetch 7c007480 ff8fff8f 0 bior imm3 r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bior IR[1] >> 4 - prefetch(); + prefetch 7c007480 ff8fff8f 0 bior imm3 r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bior IR[1] >> 4 - prefetch(); + prefetch 7c007500 ff8fff8f 0 bxor imm3 r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bxor IR[1] >> 4 - prefetch(); + prefetch 7c007500 ff8fff8f 0 bxor imm3 r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bxor IR[1] >> 4 - prefetch(); + prefetch 7c007580 ff8fff8f 0 bixor imm3 r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bixor IR[1] >> 4 - prefetch(); + prefetch 7c007580 ff8fff8f 0 bixor imm3 r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bixor IR[1] >> 4 - prefetch(); + prefetch 7c007600 ff8fff8f 0 band imm3 r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); band IR[1] >> 4 - prefetch(); + prefetch 7c007600 ff8fff8f 0 band imm3 r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); band IR[1] >> 4 - prefetch(); + prefetch 7c007680 ff8fff8f 0 biand imm3 r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); biand IR[1] >> 4 - prefetch(); + prefetch 7c007680 ff8fff8f 0 biand imm3 r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); biand IR[1] >> 4 - prefetch(); + prefetch 7c007700 ff8fff8f 0 bld imm3 r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bld IR[1] >> 4 - prefetch(); + prefetch 7c007700 ff8fff8f 0 bld imm3 r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bld IR[1] >> 4 - prefetch(); + prefetch 7c007780 ff8fff8f 0 bild imm3 r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bild IR[1] >> 4 - prefetch(); + prefetch 7c007780 ff8fff8f 0 bild imm3 r32ihh h TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bild IR[1] >> 4 - prefetch(); + prefetch 7d006000 ff8fff0f 0 bset r8h r16ihh o TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bset r8_r(IR[1] >> 4) - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2630,7 +2651,7 @@ macro jsr32 %opc %spreg TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bset r8_r(IR[1] >> 4) - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2638,7 +2659,7 @@ macro jsr32 %opc %spreg TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bnot r8_r(IR[1] >> 4) - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2646,7 +2667,7 @@ macro jsr32 %opc %spreg TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bnot r8_r(IR[1] >> 4) - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2654,7 +2675,7 @@ macro jsr32 %opc %spreg TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bclr r8_r(IR[1] >> 4) - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2662,7 +2683,7 @@ macro jsr32 %opc %spreg TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bclr r8_r(IR[1] >> 4) - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2670,7 +2691,7 @@ macro jsr32 %opc %spreg TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bst IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2678,7 +2699,7 @@ macro jsr32 %opc %spreg TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bst IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2686,7 +2707,7 @@ macro jsr32 %opc %spreg TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bist IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2694,7 +2715,7 @@ macro jsr32 %opc %spreg TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bist IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2702,7 +2723,7 @@ macro jsr32 %opc %spreg TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bset IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2710,7 +2731,7 @@ macro jsr32 %opc %spreg TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bset IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2718,7 +2739,7 @@ macro jsr32 %opc %spreg TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bnot IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2726,7 +2747,7 @@ macro jsr32 %opc %spreg TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bnot IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2734,7 +2755,7 @@ macro jsr32 %opc %spreg TMP2 = r16_r(IR[0] >> 4); TMP1 = read8(TMP2); bclr IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2742,7 +2763,7 @@ macro jsr32 %opc %spreg TMP2 = r32_r(IR[0] >> 4); TMP1 = read8(TMP2); bclr IR[1] >> 4 - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2750,67 +2771,67 @@ macro jsr32 %opc %spreg TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); btst r8_r(IR[1] >> 4) - prefetch(); + prefetch 7e007300 ff00ff8f 0 btst imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); btst IR[1] >> 4 - prefetch(); + prefetch 7e007400 ff00ff8f 0 bor imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); bor IR[1] >> 4 - prefetch(); + prefetch 7e007480 ff00ff8f 0 bior imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); bior IR[1] >> 4 - prefetch(); + prefetch 7e007500 ff00ff8f 0 bxor imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); bxor IR[1] >> 4 - prefetch(); + prefetch 7e007580 ff00ff8f 0 bixor imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); bixor IR[1] >> 4 - prefetch(); + prefetch 7e007600 ff00ff8f 0 band imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); band IR[1] >> 4 - prefetch(); + prefetch 7e007680 ff00ff8f 0 biand imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); biand IR[1] >> 4 - prefetch(); + prefetch 7e007700 ff00ff8f 0 bld imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); bld IR[1] >> 4 - prefetch(); + prefetch 7e007780 ff00ff8f 0 bild imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); bild IR[1] >> 4 - prefetch(); + prefetch 7f006000 ff00ff0f 0 bset r8h abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); bset r8_r(IR[1] >> 4) - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2818,7 +2839,7 @@ macro jsr32 %opc %spreg TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); bnot r8_r(IR[1] >> 4) - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); @@ -2826,14 +2847,14 @@ macro jsr32 %opc %spreg TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); bclr r8_r(IR[1] >> 4) - prefetch_start(); + prefetch_start write8(TMP2, TMP1); prefetch_done(); 7f006700 ff00ff8f 0 bst imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bst IR[0] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -2841,7 +2862,7 @@ macro jsr32 %opc %spreg 7f006780 ff00ff8f 0 bist imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bist IR[0] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -2849,7 +2870,7 @@ macro jsr32 %opc %spreg 7f007000 ff00ff8f 0 bset imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bset IR[1] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -2857,7 +2878,7 @@ macro jsr32 %opc %spreg 7f007100 ff00ff8f 0 bnot imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bnot IR[1] >> 4 write8(TMP2, TMP1); prefetch_done(); @@ -2865,46 +2886,46 @@ macro jsr32 %opc %spreg 7f007200 ff00ff8f 0 bclr imm3 abs8 TMP2 = 0xffffff00 | IR[0]; TMP1 = read8(TMP2); - prefetch_start(); + prefetch_start bclr IR[1] >> 4 write8(TMP2, TMP1); prefetch_done(); 8000 f000 0 add.b imm8 r8u r8_w(IR[0] >> 8, do_add8(r8_r(IR[0] >> 8), IR[0])); - prefetch(); + prefetch 9000 f000 0 addx.b imm8 r8u r8_w(IR[0] >> 8, do_addx8(r8_r(IR[0] >> 8), IR[0])); - prefetch(); + prefetch a000 f000 0 cmp.b imm8 r8u do_sub8(r8_r(IR[0]>>8), IR[0]); - prefetch(); + prefetch b000 f000 0 subx.b imm8 r8u r8_w(IR[0] >> 8, do_subx8(r8_r(IR[0] >> 8), IR[0])); - prefetch(); + prefetch c000 f000 0 or.b imm8 r8u TMP1 = IR[0] | r8_r(IR[0] >> 8); set_nzv8(TMP1); r8_w(IR[0] >> 8, TMP1); - prefetch(); + prefetch d000 f000 0 xor.b imm8 r8u TMP1 = IR[0] ^ r8_r(IR[0] >> 8); set_nzv8(TMP1); r8_w(IR[0] >> 8, TMP1); - prefetch(); + prefetch e000 f000 0 and.b imm8 r8u TMP1 = IR[0] & r8_r(IR[0] >> 8); set_nzv8(TMP1); r8_w(IR[0] >> 8, TMP1); - prefetch(); + prefetch f000 f000 0 mov.b imm8 r8u set_nzv8(IR[0]); r8_w(IR[0] >> 8, IR[0]); - prefetch(); + prefetch diff --git a/src/devices/cpu/h8/h8make.py b/src/devices/cpu/h8/h8make.py index a2d131bcfa1..0d09dbf3b9f 100644 --- a/src/devices/cpu/h8/h8make.py +++ b/src/devices/cpu/h8/h8make.py @@ -52,7 +52,7 @@ def hexsplit(str): return res def has_memory(ins): - for s in ["read", "write", "sp_push", "sp_pop", "sp32_push", "sp32_pop", "fetch(", "prefetch_start(", "prefetch(", "prefetch_noirq("]: + for s in ["read", "write"]: if s in ins: return True return False @@ -68,9 +68,16 @@ def save_full_one(f, t, name, source): substate = 1 for line in source: if has_memory(line): - print("\tif(icount <= bcount) { inst_substate = %d; return; }" % substate, file=f) print(line, file=f) - substate += 1 + print("\tif(icount <= bcount) {", file=f) + print("\t\tif(access_to_be_redone()) {", file=f) + print("\t\t\ticount++;", file=f) + print("\t\t\tinst_substate = %d;" % substate, file=f) + print("\t\t} else", file=f) + print("\t\t\tinst_substate = %d;" % (substate+1), file=f) + print("\t\treturn;", file=f) + print("\t}", file=f) + substate += 2 elif has_eat(line): print("\tif(icount) { icount = bcount; } inst_substate = %d; return;" % substate, file=f) substate += 1 @@ -87,11 +94,20 @@ def save_partial_one(f, t, name, source): substate = 1 for line in source: if has_memory(line): - print("\tif(icount <= bcount) { inst_substate = %d; return; }" % substate, file=f) print("\t[[fallthrough]];", file=f) print("case %d:;" % substate, file=f) print(line, file=f) - substate += 1 + print("\tif(icount <= bcount) {", file=f) + print("\t\tif(access_to_be_redone()) {", file=f) + print("\t\t\ticount++;", file=f) + print("\t\t\tinst_substate = %d;" % substate, file=f) + print("\t\t} else", file=f) + print("\t\t\tinst_substate = %d;" % (substate+1), file=f) + print("\t\treturn;", file=f) + print("\t}", file=f) + print("\t[[fallthrough]];", file=f) + print("case %d:;" % (substate+1), file=f) + substate += 2 elif has_eat(line): print("\tif(icount) { icount = bcount; } inst_substate = %d; return;" % substate, file=f) print("case %d:;" % substate, file=f) @@ -156,7 +172,8 @@ class Opcode: self.extra_words = extra_words base_offset = len(self.val)/2 + self.skip for i in range(0, extra_words): - self.source.append("\tfetch(%d);\n" % (i+base_offset)) + self.source.append("\tIR[%d] = read16i(PC);" % (i+base_offset)) + self.source.append("\tPC += 2;") def description(self): return "%s %s %s" % (self.name, self.am1, self.am2) @@ -269,7 +286,8 @@ class DispatchStep: end = start + self.skip s = [] for i in range(start, end+1): - s.append("\tIR[%d] = fetch();" % i) + s.append("\tIR[%d] = read16i(PC);" % i) + s.append("\tPC += 2;") s.append("\tinst_state = 0x%x0000 | IR[%d];" % (self.id, end)) return s -- cgit v1.2.3