From 79ca73c7c31ed23f09f0c4e55bd4361ca09b0d8f Mon Sep 17 00:00:00 2001 From: jbu Date: Sun, 14 Dec 2014 13:56:06 +0100 Subject: Add preliminary emulation of the Rockwell A17XX chips --- src/emu/machine/ra17xx.c | 133 +++++++++++++++++++++++++++++++++++++++++++++++ src/emu/machine/ra17xx.h | 58 +++++++++++++++++++++ 2 files changed, 191 insertions(+) create mode 100644 src/emu/machine/ra17xx.c create mode 100644 src/emu/machine/ra17xx.h diff --git a/src/emu/machine/ra17xx.c b/src/emu/machine/ra17xx.c new file mode 100644 index 00000000000..59b35ecb982 --- /dev/null +++ b/src/emu/machine/ra17xx.c @@ -0,0 +1,133 @@ +/********************************************************************** + + Rockwell A17XX ROM, RAM and I/O chip + + Copyright Nicola Salmoria and the MAME Team. + Visit http://mamedev.org for licensing and usage restrictions. + + A ROM of 2048 x 8 bits is addressed whenever the RRSEL line + (ROM/RAM select) is 0. A RAM of 128 x 4 bit is addressed when + RRSEL is 1. The 16 I/O ports are addressed when the WI/O line + is 1, i.e. whenever the CPU executes an IOL instruction. + There are two basic I/O instructions: + SES = Select Enable Status and SOS = Select Output Status + The lower 4 bits of the I/O address select one of 16 I/O lines. + + There are at most two A17XX per system, one for the lower + ROM and RAM portion and one for the higher. + + I/O section instructions + + Menmonic I/O bus Accu Description + ------------------------------------------------------------------ + SES 0 S S 0 X X X 0 1 X X X Enable all outputs + Acuu:3 <- I/O(BL) + ------------------------------------------------------------------ + SES 0 S S 0 X X X 0 0 X X X Disable all outputs + Acuu:3 <- I/O(BL) + ------------------------------------------------------------------ + SOS 0 S S 0 X X X 1 1 X X X I/O(BL) <- 1 + Acuu:3 <- I/O(BL) + ------------------------------------------------------------------ + SOS 0 S S 0 X X X 1 0 X X X I/O(BL) <- 0 + Acuu:3 <- I/O(BL) + + This device emulation takes care of the I/O commands, not the + ROM and RAM, because these are emulated using the generic MAME + memory system. +**********************************************************************/ + +#include "emu.h" +#include "machine/ra17xx.h" + +#define VERBOSE 1 +#if VERBOSE +#define LOG(x) logerror x +#else +#define LOG(x) +#endif + +/************************************* + * + * Device interface + * + *************************************/ + +const device_type RA17XX = &device_creator; + +ra17xx_device::ra17xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : device_t(mconfig, RA17XX, "Rockwell A17XX", tag, owner, clock, "ra17xx", __FILE__), + m_line(), + m_enable(false), + m_iord(*this), + m_iowr(*this) +{ +} + +/** + * @brief ra17xx_device::device_start device-specific startup + */ +void ra17xx_device::device_start() +{ + m_iord.resolve(); + m_iowr.resolve(); + + save_item(NAME(m_line)); +} + +/** + * @brief ra17xx_device::device_reset device-specific reset + */ +void ra17xx_device::device_reset() +{ + memset(m_line, 0, sizeof(m_line)); +} + + +/************************************* + * + * Constants + * + *************************************/ + +/************************************* + * + * Command access handlers + * + *************************************/ + +WRITE8_MEMBER( ra17xx_device::io_w ) +{ + assert(offset < 16); + m_bl = (data >> 4) & 15; // BL on the data bus most significant bits + if (offset & 1) { + // SOS command + if (data & (1 << 3)) { + m_line[m_bl] = 1; // enable output + if (m_enable) + m_iowr(m_bl, 1); + } else { + m_line[m_bl] = 0; // disable output + if (m_enable) + m_iowr(m_bl, 0); + } + } else { + // SES command + if (data & (1 << 3)) { + // enable all outputs + m_enable = true; + for (int i = 0; i < 16; i++) + m_iowr(i, m_line[i], 1); + } else { + // disable all outputs + m_enable = false; + } + } +} + + +READ8_MEMBER( ra17xx_device::io_r ) +{ + assert(offset < 16); + return (m_iord(m_bl) & 1) ? 0x0f : 0x07; +} diff --git a/src/emu/machine/ra17xx.h b/src/emu/machine/ra17xx.h new file mode 100644 index 00000000000..4833f5cb7c5 --- /dev/null +++ b/src/emu/machine/ra17xx.h @@ -0,0 +1,58 @@ +/********************************************************************** + + Rockwell RA17xx (e.g. A1752, A1753) ROM, RAM and I/O chip + + Juergen Buchmueller + + The device integrates a 2048 x 8 ROM, a 128 x 4 RAM and + and 16 I/O ports at one of the port ranges 00 ... 0f, + 20 ... 2f, 40 ... 4f or 60 ... 6f. + +**********************************************************************/ + +#ifndef __RA17XX_H__ +#define __RA17XX_H__ + +#include "device.h" + +/************************************* + * + * Device configuration macros + * + *************************************/ + +/* Set the read line handler */ +#define MCFG_RA17XX_READ(_devcb) \ + ra17xx_device::set_iord(*device, DEVCB_##_devcb); \ + +/* Set the write line handler */ +#define MCFG_RA17XX_WRITE(_devcb) \ + ra17xx_device::set_iowr(*device, DEVCB_##_devcb); \ + +class ra17xx_device : public device_t +{ +public: + ra17xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + ~ra17xx_device() {} + + DECLARE_READ8_MEMBER ( io_r ); + DECLARE_WRITE8_MEMBER( io_w ); + + template static devcb_base &set_iord(device_t &device, _Object object) { return downcast(device).m_iord.set_callback(object); } + template static devcb_base &set_iowr(device_t &device, _Object object) { return downcast(device).m_iowr.set_callback(object); } +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + +private: + UINT8 m_line[16]; //!< input/output flip-flops for 16 I/O lines + UINT8 m_bl; //!< value of BL during the most recent output + bool m_enable; //!< true if outputs are enabled + devcb_read8 m_iord; //!< input line (read, offset = line, data = 0/1) + devcb_write8 m_iowr; //!< output line (write, offset = line, data = 0/1) +}; + +extern const device_type RA17XX; + +#endif /* __RA17XX_H__ */ -- cgit v1.2.3