From 72a70602d7efc1239257a8dce9f98b6325aa8fbc Mon Sep 17 00:00:00 2001 From: Brice Onken <32155223+briceonk@users.noreply.github.com> Date: Fri, 13 May 2022 02:30:24 -0500 Subject: cpu/mips/r4000.cpp: Added TimerIntDis mux to IPEX5. (#9718) --- src/devices/cpu/mips/r4000.cpp | 9 +++++++-- src/devices/cpu/mips/r4000.h | 39 ++++++++++++++++++++++++++++++--------- 2 files changed, 37 insertions(+), 11 deletions(-) diff --git a/src/devices/cpu/mips/r4000.cpp b/src/devices/cpu/mips/r4000.cpp index 5f34864c0d1..5cd174d48d5 100644 --- a/src/devices/cpu/mips/r4000.cpp +++ b/src/devices/cpu/mips/r4000.cpp @@ -90,13 +90,14 @@ DEFINE_DEVICE_TYPE(R5000, r5000_device, "r5000", "MIPS R5000") u32 const r5000_device::s_fcc_masks[8] = { (1U << 23), (1U << 25), (1U << 26), (1U << 27), (1U << 28), (1U << 29), (1U << 30), (1U << 31) }; u32 const r5000_device::s_fcc_shifts[8] = { 23, 25, 26, 27, 28, 29, 30, 31 }; -r4000_base_device::r4000_base_device(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size icache_size, cache_size dcache_size, unsigned m32, unsigned m64, unsigned d32, unsigned d64) +r4000_base_device::r4000_base_device(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size icache_size, cache_size dcache_size, unsigned m32, unsigned m64, unsigned d32, unsigned d64, bool timer_interrupt_disabled) : cpu_device(mconfig, type, tag, owner, clock) , m_program_config_le("program", ENDIANNESS_LITTLE, 64, 32) , m_program_config_be("program", ENDIANNESS_BIG, 64, 32) , m_hilo_cycles{ m32, m64, d32, d64 } , m_r{} , m_cp0{} + , m_timer_interrupt_disabled(timer_interrupt_disabled) , m_f{} , m_fcr0(fcr) { @@ -1437,7 +1438,8 @@ void r4000_base_device::cp0_set(unsigned const reg, u64 const data) break; case CP0_Compare: m_cp0[CP0_Compare] = u32(data); - CAUSE &= ~CAUSE_IPEX5; + if (!m_timer_interrupt_disabled) + CAUSE &= ~CAUSE_IPEX5; cp0_update_timer(true); break; @@ -1577,6 +1579,9 @@ void r4000_base_device::cp0_tlbp() void r4000_base_device::cp0_update_timer(bool start) { + if (m_timer_interrupt_disabled) + return; + if (start || m_cp0_timer->enabled()) { u32 const count = (total_cycles() - m_cp0_timer_zero) / 2; diff --git a/src/devices/cpu/mips/r4000.h b/src/devices/cpu/mips/r4000.h index 90398b15803..f4a015e9c77 100644 --- a/src/devices/cpu/mips/r4000.h +++ b/src/devices/cpu/mips/r4000.h @@ -57,7 +57,7 @@ protected: CACHE_256K = 6, CACHE_512K = 7, }; - r4000_base_device(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size icache_size, cache_size dcache_size, unsigned m32, unsigned m64, unsigned d32, unsigned d64); + r4000_base_device(machine_config const &mconfig, device_type type, char const *tag, device_t *owner, u32 clock, u32 prid, u32 fcr, cache_size icache_size, cache_size dcache_size, unsigned m32, unsigned m64, unsigned d32, unsigned d64, bool timer_interrupt_disabled); enum cp0_reg : int { @@ -432,6 +432,7 @@ protected: bool m_hard_reset; bool m_ll_active; bool m_bus_error; + bool m_timer_interrupt_disabled; struct tlb_entry { u64 mask; @@ -468,46 +469,66 @@ class r4000_device : public r4000_base_device { public: // NOTE: R4000 chips prior to 3.0 have an xtlb bug - r4000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) - : r4000_base_device(mconfig, R4000, tag, owner, clock, 0x0430, 0x0500, CACHE_8K, CACHE_8K, 10, 20, 69, 133) + r4000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock, bool timer_interrupt_disabled) + : r4000_base_device(mconfig, R4000, tag, owner, clock, 0x0430, 0x0500, CACHE_8K, CACHE_8K, 10, 20, 69, 133, timer_interrupt_disabled) { // no secondary cache m_cp0[CP0_Config] |= CONFIG_SC; } + + r4000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : r4000_device(mconfig, tag, owner, clock, false) + { + } }; class r4400_device : public r4000_base_device { public: - r4400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) - : r4000_base_device(mconfig, R4400, tag, owner, clock, 0x0440, 0x0500, CACHE_16K, CACHE_16K, 10, 20, 69, 133) + r4400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock, bool timer_interrupt_disabled) + : r4000_base_device(mconfig, R4400, tag, owner, clock, 0x0440, 0x0500, CACHE_16K, CACHE_16K, 10, 20, 69, 133, timer_interrupt_disabled) { // no secondary cache m_cp0[CP0_Config] |= CONFIG_SC; } + + r4400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : r4400_device(mconfig, tag, owner, clock, false) + { + } }; class r4600_device : public r4000_base_device { public: - r4600_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) - : r4000_base_device(mconfig, R4600, tag, owner, clock, 0x2020, 0x2020, CACHE_16K, CACHE_16K, 10, 12, 42, 74) + r4600_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock, bool timer_interrupt_disabled) + : r4000_base_device(mconfig, R4600, tag, owner, clock, 0x2020, 0x2020, CACHE_16K, CACHE_16K, 10, 12, 42, 74, timer_interrupt_disabled) { // no secondary cache m_cp0[CP0_Config] |= CONFIG_SC; } + + r4600_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : r4600_device(mconfig, tag, owner, clock, false) + { + } }; class r5000_device : public r4000_base_device { public: - r5000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) - : r4000_base_device(mconfig, R5000, tag, owner, clock, 0x2320, 0x2320, CACHE_32K, CACHE_32K, 5, 9, 36, 68) + r5000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock, bool timer_interrupt_disabled) + : r4000_base_device(mconfig, R5000, tag, owner, clock, 0x2320, 0x2320, CACHE_32K, CACHE_32K, 5, 9, 36, 68, timer_interrupt_disabled) { // no secondary cache m_cp0[CP0_Config] |= CONFIG_SC; } + r5000_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : r5000_device(mconfig, tag, owner, clock, false) + { + } + private: virtual void handle_reserved_instruction(u32 const op) override; virtual void cp1_execute(u32 const op) override; -- cgit v1.2.3