From 7131463c210cf150c64cdf44054583c6b573c342 Mon Sep 17 00:00:00 2001 From: Patrick Mackinlay Date: Mon, 13 May 2019 12:31:06 +0700 Subject: r4000: housekeeping (nw) --- src/devices/cpu/mips/r4000.cpp | 43 +++++++++++++++++++++--------------------- src/devices/cpu/mips/r4000.h | 1 - 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/src/devices/cpu/mips/r4000.cpp b/src/devices/cpu/mips/r4000.cpp index dac528ee1e6..0fb9dfc60e8 100644 --- a/src/devices/cpu/mips/r4000.cpp +++ b/src/devices/cpu/mips/r4000.cpp @@ -16,7 +16,6 @@ * - reworked address translation logic, including 64-bit modes * - reworked softfloat3-based floating point * - experimental primary instruction cache - * - memory tap based ll/sc * - configurable endianness * - it's very very very slow * @@ -91,7 +90,6 @@ r4000_base_device::r4000_base_device(const machine_config &mconfig, device_type : cpu_device(mconfig, type, tag, owner, clock) , m_program_config_le("program", ENDIANNESS_LITTLE, 64, 32) , m_program_config_be("program", ENDIANNESS_BIG, 64, 32) - , m_ll_active(false) , m_fcr0(0x00000500U) { m_cp0[CP0_PRId] = prid; @@ -880,14 +878,14 @@ void r4000_base_device::cpu_execute(u32 const op) //case 0x1e: // * //case 0x1f: // * case 0x20: // LB - load(ADDR(m_r[RSREG], s16(op)), + load(ADDR(m_r[RSREG], s16(op)), [this, op](s8 data) { m_r[RTREG] = data; }); break; case 0x21: // LH - load(ADDR(m_r[RSREG], s16(op)), + load(ADDR(m_r[RSREG], s16(op)), [this, op](s16 data) { m_r[RTREG] = data; @@ -897,14 +895,14 @@ void r4000_base_device::cpu_execute(u32 const op) cpu_lwl(op); break; case 0x23: // LW - load(ADDR(m_r[RSREG], s16(op)), + load(ADDR(m_r[RSREG], s16(op)), [this, op](s32 data) { m_r[RTREG] = data; }); break; case 0x24: // LBU - load(ADDR(m_r[RSREG], s16(op)), + load(ADDR(m_r[RSREG], s16(op)), [this, op](u8 data) { m_r[RTREG] = data; @@ -1026,14 +1024,12 @@ void r4000_base_device::cpu_execute(u32 const op) } break; case 0x30: // LL - load_linked(ADDR(m_r[RSREG], s16(op)), + load_linked(ADDR(m_r[RSREG], s16(op)), [this, op](u64 address, s32 data) { - m_r[RTREG] = data; + m_r[RTREG] = s64(data); m_cp0[CP0_LLAddr] = u32(address >> 4); - m_ll_active = true; - m_ll_addr = ADDR(m_r[RSREG], s16(op)); }); break; case 0x31: // LWC1 @@ -1047,12 +1043,9 @@ void r4000_base_device::cpu_execute(u32 const op) load_linked(ADDR(m_r[RSREG], s16(op)), [this, op](u64 address, u64 data) { - // remove existing tap m_r[RTREG] = data; m_cp0[CP0_LLAddr] = u32(address >> 4); - m_ll_active = true; - m_ll_addr = ADDR(m_r[RSREG], s16(op)); }); break; case 0x35: // LDC1 @@ -1069,12 +1062,14 @@ void r4000_base_device::cpu_execute(u32 const op) }); break; case 0x38: // SC - if (m_ll_active && m_ll_addr == ADDR(m_r[RSREG], s16(op))) + if (m_ll_active) { - m_ll_active = false; + if (store(ADDR(m_r[RSREG], s16(op)), u32(m_r[RTREG]))) + m_r[RTREG] = 1; + else + m_r[RTREG] = 0; - store(ADDR(m_r[RSREG], s16(op)), u32(m_r[RTREG])); - m_r[RTREG] = 1; + m_ll_active = false; } else m_r[RTREG] = 0; @@ -1087,10 +1082,14 @@ void r4000_base_device::cpu_execute(u32 const op) break; //case 0x3b: // * case 0x3c: // SCD - if (m_ll_active && m_ll_addr == ADDR(m_r[RSREG], s16(op))) + if (m_ll_active) { - store(ADDR(m_r[RSREG], s16(op)), m_r[RTREG]); - m_r[RTREG] = 1; + if (store(ADDR(m_r[RSREG], s16(op)), m_r[RTREG])) + m_r[RTREG] = 1; + else + m_r[RTREG] = 0; + + m_ll_active = false; } else m_r[RTREG] = 0; @@ -2982,14 +2981,14 @@ std::string r4000_base_device::debug_string_array(u64 array_pointer) while (!done) { done = true; - load(array_pointer, [this, &done, &result](u64 string_pointer) + load(array_pointer, [this, &done, &result](s32 string_pointer) { if (string_pointer != 0) { if (!result.empty()) result += ", "; - result += '\"' + debug_string(string_pointer) + '\"'; + result += '\"' + debug_string(s64(string_pointer)) + '\"'; done = false; } diff --git a/src/devices/cpu/mips/r4000.h b/src/devices/cpu/mips/r4000.h index 156af91eb41..bbab6289ef8 100644 --- a/src/devices/cpu/mips/r4000.h +++ b/src/devices/cpu/mips/r4000.h @@ -395,7 +395,6 @@ protected: u64 m_cp0_timer_zero; emu_timer *m_cp0_timer; bool m_ll_active; - u64 m_ll_addr; struct tlb_entry_t { u64 mask; -- cgit v1.2.3