From 6d56aa957cbe4fba97189195f46028140d226997 Mon Sep 17 00:00:00 2001 From: mamehaze Date: Tue, 10 Mar 2015 21:48:56 +0000 Subject: expose some more V53 pins for the internal peripherals to the outside world (nw) timers seem very active, does some DMA ops (transfering a big block of 0 data) a few times on startup, then stops.. maybe because no interrupts happen. interrupt table looks.. weird, need to understand how it configures the interrupt controller and what that means. there are port writes to low port numbers, writes to port 0x0000 in the format with data in the format 0x??00 0x??01 0x??02 0x??03 0x??04 0x??05 0x??06 0x??07 0x??08 0x??09 0x??0a 0x??0b 0x??0c 0x??0d 0x??0e 0x??0f 0x??10 0x??11 0x??12 0x??13 0x??14 0x??15 0x??16 0x??17 0x??18 0x??19 0x??1a 0x??1b 0x??1c 0x??1d 0x??1e 0x??1f and after each write to port 0 with those values it writes some other data to ports 2,4,6. if the information is correct, and this is a 32-channel based sound system, then that could well be some kind of configuration for the channels. --- src/emu/cpu/nec/v53.c | 135 +++++++++++++++++---------------------- src/emu/cpu/nec/v53.h | 157 ++++++++++++++++++++++++++++++++++++++-------- src/mame/audio/hng64.c | 49 ++++++++++++++- src/mame/includes/hng64.h | 9 ++- 4 files changed, 244 insertions(+), 106 deletions(-) diff --git a/src/emu/cpu/nec/v53.c b/src/emu/cpu/nec/v53.c index 6dd857f5a58..feae9eb20f6 100644 --- a/src/emu/cpu/nec/v53.c +++ b/src/emu/cpu/nec/v53.c @@ -198,6 +198,23 @@ void v53_base_device::device_start() m_out0_handler.resolve_safe(); m_out1_handler.resolve_safe(); m_out2_handler.resolve_safe(); + + m_out_hreq_cb.resolve_safe(); + m_out_eop_cb.resolve_safe(); + m_in_memr_cb.resolve_safe(0); + m_out_memw_cb.resolve_safe(); + m_in_ior_0_cb.resolve_safe(0); + m_in_ior_1_cb.resolve_safe(0); + m_in_ior_2_cb.resolve_safe(0); + m_in_ior_3_cb.resolve_safe(0); + m_out_iow_0_cb.resolve_safe(); + m_out_iow_1_cb.resolve_safe(); + m_out_iow_2_cb.resolve_safe(); + m_out_iow_3_cb.resolve_safe(); + m_out_dack_0_cb.resolve_safe(); + m_out_dack_1_cb.resolve_safe(); + m_out_dack_2_cb.resolve_safe(); + m_out_dack_3_cb.resolve_safe(); } void v53_base_device::install_peripheral_io() @@ -304,42 +321,6 @@ WRITE8_MEMBER(v53_base_device::scu_simk_w) printf("v53: scu_simk_w %02x\n", data); } -WRITE_LINE_MEMBER(v53_base_device::scu_txd_trampoline_cb) -{ - m_txd_handler(state); -} - -WRITE_LINE_MEMBER(v53_base_device::scu_dtr_trampoline_cb) -{ - m_dtr_handler(state); -} - -WRITE_LINE_MEMBER(v53_base_device::scu_rts_trampoline_cb) -{ - m_rts_handler(state); -} - -WRITE_LINE_MEMBER(v53_base_device::scu_rxrdy_trampoline_cb) -{ - // should we mask this here based on m_simk? it can mask the interrupt - m_rxrdy_handler(state); -} - -WRITE_LINE_MEMBER(v53_base_device::scu_txrdy_trampoline_cb) -{ - // should we mask this here based on m_simk? it can mask the interrupt - m_txrdy_handler(state); -} - -WRITE_LINE_MEMBER(v53_base_device::scu_txempty_trampoline_cb) -{ - m_txempty_handler(state); -} - -WRITE_LINE_MEMBER(v53_base_device::scu_syndet_trampoline_cb) -{ - m_syndet_handler(state); -} /*** TCU ***/ @@ -355,27 +336,13 @@ READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(space, 1); } READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); } -WRITE_LINE_MEMBER(v53_base_device::tcu_out0_trampoline_cb) -{ - m_out0_handler(state); -} - -WRITE_LINE_MEMBER(v53_base_device::tcu_out1_trampoline_cb) -{ - m_out1_handler(state); -} - -WRITE_LINE_MEMBER(v53_base_device::tcu_out2_trampoline_cb) -{ - m_out2_handler(state); -} /*** DMA ***/ // could be wrong / nonexistent -WRITE_LINE_MEMBER(v53_base_device::dreq0_trampoline_w) +WRITE_LINE_MEMBER(v53_base_device::dreq0_w) { if (!(m_SCTL & 0x02)) { @@ -387,7 +354,7 @@ WRITE_LINE_MEMBER(v53_base_device::dreq0_trampoline_w) } } -WRITE_LINE_MEMBER(v53_base_device::dreq1_trampoline_w) +WRITE_LINE_MEMBER(v53_base_device::dreq1_w) { if (!(m_SCTL & 0x02)) { @@ -399,7 +366,7 @@ WRITE_LINE_MEMBER(v53_base_device::dreq1_trampoline_w) } } -WRITE_LINE_MEMBER(v53_base_device::dreq2_trampoline_w) +WRITE_LINE_MEMBER(v53_base_device::dreq2_w) { if (!(m_SCTL & 0x02)) { @@ -411,7 +378,7 @@ WRITE_LINE_MEMBER(v53_base_device::dreq2_trampoline_w) } } -WRITE_LINE_MEMBER(v53_base_device::dreq3_trampoline_w) +WRITE_LINE_MEMBER(v53_base_device::dreq3_w) { if (!(m_SCTL & 0x02)) { @@ -423,7 +390,7 @@ WRITE_LINE_MEMBER(v53_base_device::dreq3_trampoline_w) } } -WRITE_LINE_MEMBER(v53_base_device::hack_trampoline_w) +WRITE_LINE_MEMBER(v53_base_device::hack_w) { if (!(m_SCTL & 0x02)) { @@ -431,7 +398,7 @@ WRITE_LINE_MEMBER(v53_base_device::hack_trampoline_w) } else { - printf("v53: hack_trampoline_w not in 71071mode\n"); + printf("v53: hack_w not in 71071mode\n"); } } @@ -472,23 +439,8 @@ static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device ) // AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff ADDRESS_MAP_END -WRITE_LINE_MEMBER(v53_base_device::dma_hrq_changed) -{ - // pass this back to the driver? / expose externally? - m_v53dmau->hack_w(state); -} -WRITE8_MEMBER(v53_base_device::dma_io_3_w) -{ -// logerror("dma_io_3_w %02x\n", data); -} -READ8_MEMBER(v53_base_device::dma_memin_r) -{ - UINT8 ret = rand(); -// logerror("dma_memin_r offset %08x %02x\n", offset, ret); - return ret; -} READ8_MEMBER(v53_base_device::get_pic_ack) { @@ -510,12 +462,24 @@ static MACHINE_CONFIG_FRAGMENT( v53 ) MCFG_PIT8253_OUT1_HANDLER(WRITELINE( v53_base_device, tcu_out1_trampoline_cb )) MCFG_PIT8253_OUT2_HANDLER(WRITELINE( v53_base_device, tcu_out2_trampoline_cb )) - MCFG_DEVICE_ADD("upd71071dma", V53_DMAU, 4000000) - MCFG_I8237_OUT_HREQ_CB(WRITELINE(v53_base_device, dma_hrq_changed)) - MCFG_I8237_OUT_IOW_3_CB(WRITE8(v53_base_device, dma_io_3_w)) - MCFG_I8237_IN_MEMR_CB(READ8(v53_base_device, dma_memin_r)) - + MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(v53_base_device, hreq_trampoline_cb)) + MCFG_AM9517A_OUT_EOP_CB(WRITELINE(v53_base_device, eop_trampoline_cb)) + MCFG_AM9517A_IN_MEMR_CB(READ8(v53_base_device, dma_memr_trampoline_r)) + MCFG_AM9517A_OUT_MEMW_CB(WRITE8(v53_base_device, dma_memw_trampoline_w)) + MCFG_AM9517A_IN_IOR_0_CB(READ8(v53_base_device, dma_io_0_trampoline_r)) + MCFG_AM9517A_IN_IOR_1_CB(READ8(v53_base_device, dma_io_1_trampoline_r)) + MCFG_AM9517A_IN_IOR_2_CB(READ8(v53_base_device, dma_io_2_trampoline_r)) + MCFG_AM9517A_IN_IOR_3_CB(READ8(v53_base_device, dma_io_3_trampoline_r)) + MCFG_AM9517A_OUT_IOW_0_CB(WRITE8(v53_base_device, dma_io_0_trampoline_w)) + MCFG_AM9517A_OUT_IOW_1_CB(WRITE8(v53_base_device, dma_io_1_trampoline_w)) + MCFG_AM9517A_OUT_IOW_2_CB(WRITE8(v53_base_device, dma_io_2_trampoline_w)) + MCFG_AM9517A_OUT_IOW_3_CB(WRITE8(v53_base_device, dma_io_3_trampoline_w)) + MCFG_AM9517A_OUT_DACK_0_CB(WRITELINE(v53_base_device, dma_dack0_trampoline_w)) + MCFG_AM9517A_OUT_DACK_1_CB(WRITELINE(v53_base_device, dma_dack1_trampoline_w)) + MCFG_AM9517A_OUT_DACK_2_CB(WRITELINE(v53_base_device, dma_dack2_trampoline_w)) + MCFG_AM9517A_OUT_DACK_3_CB(WRITELINE(v53_base_device, dma_dack3_trampoline_w)) + MCFG_PIC8259_ADD( "upd71059pic", WRITELINE(v53_base_device, upd71059_irq_w), VCC, READ8(v53_base_device,get_pic_ack)) @@ -554,7 +518,24 @@ v53_base_device::v53_base_device(const machine_config &mconfig, device_type type // TCU m_out0_handler(*this), m_out1_handler(*this), - m_out2_handler(*this) + m_out2_handler(*this), + // DMAU + m_out_hreq_cb(*this), + m_out_eop_cb(*this), + m_in_memr_cb(*this), + m_out_memw_cb(*this), + m_in_ior_0_cb(*this), + m_in_ior_1_cb(*this), + m_in_ior_2_cb(*this), + m_in_ior_3_cb(*this), + m_out_iow_0_cb(*this), + m_out_iow_1_cb(*this), + m_out_iow_2_cb(*this), + m_out_iow_3_cb(*this), + m_out_dack_0_cb(*this), + m_out_dack_1_cb(*this), + m_out_dack_2_cb(*this), + m_out_dack_3_cb(*this) { } diff --git a/src/emu/cpu/nec/v53.h b/src/emu/cpu/nec/v53.h index ec9d82ed262..3eec840fcd8 100644 --- a/src/emu/cpu/nec/v53.h +++ b/src/emu/cpu/nec/v53.h @@ -50,6 +50,56 @@ #define MCFG_V53_TCU_OUT2_HANDLER(_devcb) \ devcb = &v53_base_device::set_out2_handler(*device, DEVCB_##_devcb); +// DMAU + +#define MCFG_V53_DMAU_OUT_HREQ_CB(_devcb) \ + devcb = &v53_base_device::set_out_hreq_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_EOP_CB(_devcb) \ + devcb = &v53_base_device::set_out_eop_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_IN_MEMR_CB(_devcb) \ + devcb = &v53_base_device::set_in_memr_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_MEMW_CB(_devcb) \ + devcb = &v53_base_device::set_out_memw_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_IN_IOR_0_CB(_devcb) \ + devcb = &v53_base_device::set_in_ior_0_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_IN_IOR_1_CB(_devcb) \ + devcb = &v53_base_device::set_in_ior_1_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_IN_IOR_2_CB(_devcb) \ + devcb = &v53_base_device::set_in_ior_2_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_IN_IOR_3_CB(_devcb) \ + devcb = &v53_base_device::set_in_ior_3_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_IOW_0_CB(_devcb) \ + devcb = &v53_base_device::set_out_iow_0_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_IOW_1_CB(_devcb) \ + devcb = &v53_base_device::set_out_iow_1_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_IOW_2_CB(_devcb) \ + devcb = &v53_base_device::set_out_iow_2_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_IOW_3_CB(_devcb) \ + devcb = &v53_base_device::set_out_iow_3_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_DACK_0_CB(_devcb) \ + devcb = &v53_base_device::set_out_dack_0_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_DACK_1_CB(_devcb) \ + devcb = &v53_base_device::set_out_dack_1_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_DACK_2_CB(_devcb) \ + devcb = &v53_base_device::set_out_dack_2_callback(*device, DEVCB_##_devcb); + +#define MCFG_V53_DMAU_OUT_DACK_3_CB(_devcb) \ + devcb = &v53_base_device::set_out_dack_3_callback(*device, DEVCB_##_devcb); + class v53_base_device : public nec_common_device @@ -88,9 +138,6 @@ public: UINT8 m_DULA; UINT8 m_OPHA; - // TCU - - // SCU DECLARE_READ8_MEMBER(scu_simk_r); DECLARE_WRITE8_MEMBER(scu_simk_w); @@ -102,13 +149,13 @@ public: template static devcb_base &set_txrdy_handler(device_t &device, _Object object) { return downcast(device).m_txrdy_handler.set_callback(object); } template static devcb_base &set_txempty_handler(device_t &device, _Object object) { return downcast(device).m_txempty_handler.set_callback(object); } template static devcb_base &set_syndet_handler(device_t &device, _Object object) { return downcast(device).m_syndet_handler.set_callback(object); } - DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb); - DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb); - DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb); - DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb); - DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb); - DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb); - DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb); + DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb) { m_txd_handler(state); } + DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb) { m_dtr_handler(state); } + DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); } + DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb) { m_rxrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */ + DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb) { m_txrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */ + DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); } + DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb) { m_syndet_handler(state); } // TCU DECLARE_READ8_MEMBER(tmu_tst0_r); @@ -124,11 +171,53 @@ public: template static devcb_base &set_out0_handler(device_t &device, _Object object) { return downcast(device).m_out0_handler.set_callback(object); } template static devcb_base &set_out1_handler(device_t &device, _Object object) { return downcast(device).m_out1_handler.set_callback(object); } template static devcb_base &set_out2_handler(device_t &device, _Object object) { return downcast(device).m_out2_handler.set_callback(object); } - DECLARE_WRITE_LINE_MEMBER(tcu_out0_trampoline_cb); - DECLARE_WRITE_LINE_MEMBER(tcu_out1_trampoline_cb); - DECLARE_WRITE_LINE_MEMBER(tcu_out2_trampoline_cb); + DECLARE_WRITE_LINE_MEMBER(tcu_out0_trampoline_cb){ m_out0_handler(state); } + DECLARE_WRITE_LINE_MEMBER(tcu_out1_trampoline_cb){ m_out1_handler(state); } + DECLARE_WRITE_LINE_MEMBER(tcu_out2_trampoline_cb){ m_out2_handler(state); } + + // DMAU + template static devcb_base &set_out_hreq_callback(device_t &device, _Object object) { return downcast(device).m_out_hreq_cb.set_callback(object); } + template static devcb_base &set_out_eop_callback(device_t &device, _Object object) { return downcast(device).m_out_eop_cb.set_callback(object); } + template static devcb_base &set_in_memr_callback(device_t &device, _Object object) { return downcast(device).m_in_memr_cb.set_callback(object); } + template static devcb_base &set_out_memw_callback(device_t &device, _Object object) { return downcast(device).m_out_memw_cb.set_callback(object); } + template static devcb_base &set_in_ior_0_callback(device_t &device, _Object object) { return downcast(device).m_in_ior_0_cb.set_callback(object); } + template static devcb_base &set_in_ior_1_callback(device_t &device, _Object object) { return downcast(device).m_in_ior_1_cb.set_callback(object); } + template static devcb_base &set_in_ior_2_callback(device_t &device, _Object object) { return downcast(device).m_in_ior_2_cb.set_callback(object); } + template static devcb_base &set_in_ior_3_callback(device_t &device, _Object object) { return downcast(device).m_in_ior_3_cb.set_callback(object); } + template static devcb_base &set_out_iow_0_callback(device_t &device, _Object object) { return downcast(device).m_out_iow_0_cb.set_callback(object); } + template static devcb_base &set_out_iow_1_callback(device_t &device, _Object object) { return downcast(device).m_out_iow_1_cb.set_callback(object); } + template static devcb_base &set_out_iow_2_callback(device_t &device, _Object object) { return downcast(device).m_out_iow_2_cb.set_callback(object); } + template static devcb_base &set_out_iow_3_callback(device_t &device, _Object object) { return downcast(device).m_out_iow_3_cb.set_callback(object); } + template static devcb_base &set_out_dack_0_callback(device_t &device, _Object object) { return downcast(device).m_out_dack_0_cb.set_callback(object); } + template static devcb_base &set_out_dack_1_callback(device_t &device, _Object object) { return downcast(device).m_out_dack_1_cb.set_callback(object); } + template static devcb_base &set_out_dack_2_callback(device_t &device, _Object object) { return downcast(device).m_out_dack_2_cb.set_callback(object); } + template static devcb_base &set_out_dack_3_callback(device_t &device, _Object object) { return downcast(device).m_out_dack_3_cb.set_callback(object); } + DECLARE_WRITE_LINE_MEMBER(hreq_trampoline_cb) { m_out_hreq_cb(state); } + DECLARE_WRITE_LINE_MEMBER(eop_trampoline_cb) { m_out_eop_cb(state); } + DECLARE_READ8_MEMBER(dma_memr_trampoline_r) { return m_in_memr_cb(space, offset); } + DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) { m_out_memw_cb(space, offset, data); } + DECLARE_READ8_MEMBER(dma_io_0_trampoline_r) { return m_in_ior_0_cb(space, offset); } + DECLARE_READ8_MEMBER(dma_io_1_trampoline_r) { return m_in_ior_1_cb(space, offset); } + DECLARE_READ8_MEMBER(dma_io_2_trampoline_r) { return m_in_ior_2_cb(space, offset); } + DECLARE_READ8_MEMBER(dma_io_3_trampoline_r) { return m_in_ior_3_cb(space, offset); } + DECLARE_WRITE8_MEMBER(dma_io_0_trampoline_w) { m_out_iow_0_cb(space, offset, data); } + DECLARE_WRITE8_MEMBER(dma_io_1_trampoline_w) { m_out_iow_1_cb(space, offset, data); } + DECLARE_WRITE8_MEMBER(dma_io_2_trampoline_w) { m_out_iow_2_cb(space, offset, data); } + DECLARE_WRITE8_MEMBER(dma_io_3_trampoline_w) { m_out_iow_3_cb(space, offset, data); } + DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) { m_out_dack_0_cb(state); } + DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) { m_out_dack_1_cb(state); } + DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) { m_out_dack_2_cb(state); } + DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) { m_out_dack_3_cb(state); } + + + DECLARE_WRITE_LINE_MEMBER(dreq0_w); + DECLARE_WRITE_LINE_MEMBER(dreq1_w); + DECLARE_WRITE_LINE_MEMBER(dreq2_w); + DECLARE_WRITE_LINE_MEMBER(dreq3_w); + DECLARE_WRITE_LINE_MEMBER(hack_w); + + - void install_peripheral_io(); const address_space_config m_io_space_config; @@ -142,20 +231,8 @@ public: } } - required_device m_v53tcu; - required_device m_v53dmau; - required_device m_v53icu; - required_device m_v53scu; - DECLARE_WRITE_LINE_MEMBER(dreq0_trampoline_w); - DECLARE_WRITE_LINE_MEMBER(dreq1_trampoline_w); - DECLARE_WRITE_LINE_MEMBER(dreq2_trampoline_w); - DECLARE_WRITE_LINE_MEMBER(dreq3_trampoline_w); - DECLARE_WRITE_LINE_MEMBER(hack_trampoline_w); - DECLARE_WRITE_LINE_MEMBER(dma_hrq_changed); - DECLARE_WRITE8_MEMBER(dma_io_3_w); - DECLARE_READ8_MEMBER(dma_memin_r); DECLARE_READ8_MEMBER(get_pic_ack); DECLARE_WRITE_LINE_MEMBER(upd71059_irq_w); @@ -165,6 +242,11 @@ protected: virtual machine_config_constructor device_mconfig_additions() const; virtual void device_start(); virtual void device_reset(); + + required_device m_v53tcu; + required_device m_v53dmau; + required_device m_v53icu; + required_device m_v53scu; // SCU devcb_write_line m_txd_handler; @@ -182,6 +264,29 @@ protected: devcb_write_line m_out0_handler; devcb_write_line m_out1_handler; devcb_write_line m_out2_handler; + + + // DMAU + devcb_write_line m_out_hreq_cb; + devcb_write_line m_out_eop_cb; + devcb_read8 m_in_memr_cb; + devcb_write8 m_out_memw_cb; + devcb_read8 m_in_ior_0_cb; + devcb_read8 m_in_ior_1_cb; + devcb_read8 m_in_ior_2_cb; + devcb_read8 m_in_ior_3_cb; + devcb_write8 m_out_iow_0_cb; + devcb_write8 m_out_iow_1_cb; + devcb_write8 m_out_iow_2_cb; + devcb_write8 m_out_iow_3_cb; + devcb_write_line m_out_dack_0_cb; + devcb_write_line m_out_dack_1_cb; + devcb_write_line m_out_dack_2_cb; + devcb_write_line m_out_dack_3_cb; + + + + }; diff --git a/src/mame/audio/hng64.c b/src/mame/audio/hng64.c index a16f7b8d369..bdd48bda03f 100644 --- a/src/mame/audio/hng64.c +++ b/src/mame/audio/hng64.c @@ -153,8 +153,8 @@ WRITE16_MEMBER(hng64_state::hng64_sound_port_0008_w) // seems to one or more of the DMARQ on the V53, writes here when it expects DMA channel 3 to transfer ~0x20 bytes just after startup - m_audiocpu->dreq3_trampoline_w(data&1); -// m_audiocpu->hack_trampoline_w(1); + m_audiocpu->dreq3_w(data&1); +// m_audiocpu->hack_w(1); } @@ -162,11 +162,56 @@ static ADDRESS_MAP_START( hng_sound_io, AS_IO, 16, hng64_state ) AM_RANGE(0x0008, 0x0009) AM_WRITE( hng64_sound_port_0008_w ) ADDRESS_MAP_END +WRITE_LINE_MEMBER(hng64_state::dma_hreq_cb) +{ + m_audiocpu->hack_w(1); +} + +READ8_MEMBER(hng64_state::dma_memr_cb) +{ + return m_audiocpu->space(AS_PROGRAM).read_byte(offset);; +} + +WRITE8_MEMBER(hng64_state::dma_iow3_cb) +{ + // currently it reads a block of 0x20 '0x00' values from a very specific block of RAM where there is a 0x20 space in the data and transfers them repeatedly, I assume + // this is some kind of buffer for the audio or DSP and eventually will be populated with other values... + // if this comes to life maybe something interesting is happening! + if (data!=0x00) printf("dma_iow3_cb %02x\n", data); +} + +WRITE_LINE_MEMBER(hng64_state::tcu_tm0_cb) +{ + // this goes high once near startup + printf("tcu_tm0_cb %02x\n", state); +} + +WRITE_LINE_MEMBER(hng64_state::tcu_tm1_cb) +{ + // these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1 +// printf("tcu_tm1_cb %02x\n", state); +} + +WRITE_LINE_MEMBER(hng64_state::tcu_tm2_cb) +{ + // these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1 +// printf("tcu_tm2_cb %02x\n", state); +} + + MACHINE_CONFIG_FRAGMENT( hng64_audio ) MCFG_CPU_ADD("audiocpu", V53A, 16000000) // V53A, 16? mhz! MCFG_CPU_PROGRAM_MAP(hng_sound_map) MCFG_CPU_IO_MAP(hng_sound_io) + MCFG_V53_DMAU_OUT_HREQ_CB(WRITELINE(hng64_state, dma_hreq_cb)) + MCFG_V53_DMAU_IN_MEMR_CB(READ8(hng64_state, dma_memr_cb)) + MCFG_V53_DMAU_OUT_IOW_3_CB(WRITE8(hng64_state,dma_iow3_cb)) + + MCFG_V53_TCU_OUT0_HANDLER(WRITELINE(hng64_state, tcu_tm0_cb)) + MCFG_V53_TCU_OUT1_HANDLER(WRITELINE(hng64_state, tcu_tm1_cb)) + MCFG_V53_TCU_OUT2_HANDLER(WRITELINE(hng64_state, tcu_tm2_cb)) + MACHINE_CONFIG_END diff --git a/src/mame/includes/hng64.h b/src/mame/includes/hng64.h index 36ad331dd86..c4377dda530 100644 --- a/src/mame/includes/hng64.h +++ b/src/mame/includes/hng64.h @@ -354,7 +354,14 @@ public: int m_vertsrom_size; void reset_sound(); void reset_net(); - WRITE16_MEMBER(hng64_sound_port_0008_w); + DECLARE_WRITE16_MEMBER(hng64_sound_port_0008_w); + + DECLARE_WRITE_LINE_MEMBER(dma_hreq_cb); + DECLARE_READ8_MEMBER(dma_memr_cb); + DECLARE_WRITE8_MEMBER(dma_iow3_cb); + WRITE_LINE_MEMBER(tcu_tm0_cb); + WRITE_LINE_MEMBER(tcu_tm1_cb); + WRITE_LINE_MEMBER(tcu_tm2_cb); }; -- cgit v1.2.3