From 5f326aa5d4209fb52fb6065676512200322b3e56 Mon Sep 17 00:00:00 2001 From: Ted Green Date: Sun, 5 May 2019 09:09:31 -0600 Subject: (nw) MIPS3: Use sequence generator for random tlb indices so that DRC and non-DRC code sequences match --- src/devices/cpu/mips/mips3.cpp | 14 ++++++++++---- src/devices/cpu/mips/mips3.h | 3 ++- src/devices/cpu/mips/mips3com.cpp | 18 ++++++++++++++---- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/src/devices/cpu/mips/mips3.cpp b/src/devices/cpu/mips/mips3.cpp index 561d4b56506..bd50fb22df7 100644 --- a/src/devices/cpu/mips/mips3.cpp +++ b/src/devices/cpu/mips/mips3.cpp @@ -534,9 +534,14 @@ void mips3_device::device_start() save_item(NAME(m_tlb[tlbindex].entry_hi), tlbindex); save_item(NAME(m_tlb[tlbindex].entry_lo), tlbindex); } + save_item(NAME(m_tlb_seed)); // Register state with debugger state_add( MIPS3_PC, "PC", m_core->pc).formatstr("%08X"); + state_add( MIPS3_SR, "SR", m_core->cpr[0][COP0_Status]).formatstr("%08X"); + state_add( MIPS3_EPC, "EPC", m_core->cpr[0][COP0_EPC]).formatstr("%08X"); + state_add( MIPS3_CAUSE, "Cause", m_core->cpr[0][COP0_Cause]).formatstr("%08X"); + state_add( MIPS3_BADVADDR, "BadVAddr", m_core->cpr[0][COP0_BadVAddr]).formatstr("%08X"); #if USE_ABI_REG_NAMES state_add( MIPS3_R0, "zero", m_core->r[0]).callimport().formatstr("%016X"); // Can't change R0 @@ -707,9 +712,9 @@ void mips3_device::device_start() state_add( MIPS3_FPS31, "FPS31", m_core->cpr[1][31]).formatstr("%17s"); state_add( MIPS3_FPD31, "FPD31", m_core->cpr[1][31]).formatstr("%17s"); - state_add( MIPS3_SR, "SR", m_core->cpr[0][COP0_Status]).formatstr("%08X"); - state_add( MIPS3_EPC, "EPC", m_core->cpr[0][COP0_EPC]).formatstr("%08X"); - state_add( MIPS3_CAUSE, "Cause", m_core->cpr[0][COP0_Cause]).formatstr("%08X"); + //state_add( MIPS3_SR, "SR", m_core->cpr[0][COP0_Status]).formatstr("%08X"); + //state_add( MIPS3_EPC, "EPC", m_core->cpr[0][COP0_EPC]).formatstr("%08X"); + //state_add( MIPS3_CAUSE, "Cause", m_core->cpr[0][COP0_Cause]).formatstr("%08X"); state_add( MIPS3_COUNT, "Count", m_debugger_temp).callexport().formatstr("%08X"); state_add( MIPS3_COMPARE, "Compare", m_core->cpr[0][COP0_Compare]).formatstr("%08X"); state_add( MIPS3_INDEX, "Index", m_core->cpr[0][COP0_Index]).formatstr("%08X"); @@ -719,7 +724,7 @@ void mips3_device::device_start() state_add( MIPS3_ENTRYLO1, "EntryLo1", m_core->cpr[0][COP0_EntryLo1]).formatstr("%016X"); state_add( MIPS3_PAGEMASK, "PageMask", m_core->cpr[0][COP0_PageMask]).formatstr("%016X"); state_add( MIPS3_WIRED, "Wired", m_core->cpr[0][COP0_Wired]).formatstr("%08X"); - state_add( MIPS3_BADVADDR, "BadVAddr", m_core->cpr[0][COP0_BadVAddr]).formatstr("%08X"); + //state_add( MIPS3_BADVADDR, "BadVAddr", m_core->cpr[0][COP0_BadVAddr]).formatstr("%08X"); state_add( MIPS3_LLADDR, "LLAddr", m_core->cpr[0][COP0_LLAddr]).formatstr("%08X"); state_add( STATE_GENPCBASE, "CURPC", m_core->pc).noshow(); @@ -1117,6 +1122,7 @@ void mips3_device::device_reset() // TX4925 on-board peripherals pass-through if (m_flavor == MIPS3_TYPE_TX4925) vtlb_load(2 * m_tlbentries + 2, (0xff200000 - 0xff1f0000) >> MIPS3_MIN_PAGE_SHIFT, 0xff1f0000, 0xff1f0000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID); + m_tlb_seed = 0; m_core->mode = (MODE_KERNEL << 1) | 0; m_drc_cache_dirty = true; diff --git a/src/devices/cpu/mips/mips3.h b/src/devices/cpu/mips/mips3.h index 10183851804..147e9213620 100644 --- a/src/devices/cpu/mips/mips3.h +++ b/src/devices/cpu/mips/mips3.h @@ -432,6 +432,7 @@ protected: uint32_t c_system_clock; uint32_t m_cpu_clock; emu_timer * m_compare_int_timer; + uint32_t m_tlb_seed; /* derived info based on flavor */ uint32_t m_pfnmask; @@ -511,7 +512,6 @@ protected: } m_hotspot[MIPS3_MAX_HOTSPOTS]; bool m_isdrc; - void generate_exception(int exception, int backup); void generate_tlb_exception(int exception, offs_t address); virtual void check_irqs(); @@ -529,6 +529,7 @@ private: uint32_t compute_config_register(); uint32_t compute_prid_register(); + uint32_t generate_tlb_index(); void tlb_map_entry(int tlbindex); void tlb_write_common(int tlbindex); diff --git a/src/devices/cpu/mips/mips3com.cpp b/src/devices/cpu/mips/mips3com.cpp index 04225d86da7..f671ba2c335 100644 --- a/src/devices/cpu/mips/mips3com.cpp +++ b/src/devices/cpu/mips/mips3com.cpp @@ -136,6 +136,18 @@ void mips3_device::mips3com_tlbwi() } +/*------------------------------------------------- +generate_tlb_index - generate a random tlb index +-------------------------------------------------*/ + +uint32_t mips3_device::generate_tlb_index() +{ + // Actual hardware uses a free running counter to generate the index. + // This impementation uses a linear congruential generator so that DRC and non-DRC code sequences match. + m_tlb_seed = 214013 * m_tlb_seed + 2531011; + return (m_tlb_seed >> 16) & 0x3f; +} + /*------------------------------------------------- mips3com_tlbwr - execute the tlbwr instruction -------------------------------------------------*/ @@ -146,9 +158,9 @@ void mips3_device::mips3com_tlbwr() uint32_t unwired = m_tlbentries - wired; uint32_t tlbindex = m_tlbentries - 1; - /* "random" is based off of the current cycle counting through the non-wired pages */ + /* "random" is based off of linear congruential sequence through the non-wired pages */ if (unwired > 0) - tlbindex = ((total_cycles() - m_core->count_zero_time) % unwired + wired) & 0x3f; + tlbindex = (generate_tlb_index() % unwired) + wired; /* use the common handler to write to this tlbindex */ tlb_write_common(tlbindex); @@ -352,7 +364,6 @@ uint32_t mips3_device::compute_prid_register() //return 0x2000; } - /*------------------------------------------------- tlb_map_entry - map a single TLB entry @@ -443,7 +454,6 @@ void mips3_device::tlb_write_common(int tlbindex) /* remap this TLB entry */ tlb_map_entry(tlbindex); - /* log the two halves once they are in */ tlb_entry_log_half(entry, tlbindex, 0); tlb_entry_log_half(entry, tlbindex, 1); -- cgit v1.2.3