From 5dc861b772ebd763549a621514978cc9c36da6dd Mon Sep 17 00:00:00 2001 From: tim lindner Date: Tue, 4 Apr 2023 11:43:52 -0700 Subject: add undocumented instructions and dissasembler (#11050) --- src/devices/cpu/m6809/6x09dasm.cpp | 1614 +++++++++++++++++++----------------- src/devices/cpu/m6809/6x09dasm.h | 61 +- src/devices/cpu/m6809/m6809.cpp | 6 + src/devices/cpu/m6809/m6809.h | 1 + src/devices/cpu/m6809/m6809.lst | 195 ++++- 5 files changed, 1066 insertions(+), 811 deletions(-) diff --git a/src/devices/cpu/m6809/6x09dasm.cpp b/src/devices/cpu/m6809/6x09dasm.cpp index c40192336ec..f0caae2b318 100644 --- a/src/devices/cpu/m6809/6x09dasm.cpp +++ b/src/devices/cpu/m6809/6x09dasm.cpp @@ -49,50 +49,111 @@ u32 m6x09_base_disassembler::opcode_alignment() const return 1; } +//------------------------------------------------- +// constructor +//------------------------------------------------- + +m6x09_base_disassembler::m6x09_base_disassembler(const opcodeinfo *opcodes, size_t opcode_count, uint32_t level) + : m_level(level), m_page(0) +{ + // create filtered opcode table + for (int i=0; imode()) { - case PG1: - page = 0x1000; - break; - - case PG2: - page = 0x1100; - break; + // on the 6809 an unimplemented page 2 or 3 opcodes fall through to the first page. + if (!(m_level & HD6309_EXCLUSIVE) && (m_page != 0)) + { + // backup the opcode pointer and disassemble the bare opcode. + --p; + m_page = 0; + } + else + // nothing to disassemble. + return nullptr; + } + else + { + // was this a $10 or $11 page? + switch (iter->mode()) + { + case PG2: + case PG3: + if (m_page != 0 && m_level & HD6309_EXCLUSIVE) + { + // multiple pages are illegal on the 6309 + m_page = 0; + return nullptr; + } + else if (m_page == 0) + { + // remember the page that comes first + page_count++; + m_page = iter->opcode() << 8; + } + else + { + // output single page opcode after a two pages + if (page_count++) + { + --p; + return nullptr; + } + } + break; - default: - op = &*iter; - break; + default: + op = &*iter; + m_page = 0; + break; + } } }; - // is this an HD6309 exclusive instruction, and we're not HD6309? if so, reject it - if (op && (op->level() > m_level)) - op = nullptr; - return op; } @@ -113,29 +174,27 @@ offs_t m6x09_base_disassembler::disassemble(std::ostream &stream, offs_t pc, con if (!op) { // illegal opcode - util::stream_format(stream, "%-6s$%02X", "FCB", opcodes.r8(pc)); + util::stream_format(stream, "%-7s$%02X", "FCB", opcodes.r8(pc)); for (offs_t q = pc + 1; q < p; q++) util::stream_format(stream, ",$%02X", opcodes.r8(q)); return (p - pc) | SUPPORTED; } - // how many operands do we have? - int numoperands = (p - pc == 1) - ? op->length() - 1 - : op->length() - 2; offs_t flags = op->flags(); offs_t ppc = p; - p += numoperands; + p += op->operand_length(); // output the base instruction name if (op->mode() == INH) stream << op->name(); else - util::stream_format(stream, "%-6s", op->name()); + util::stream_format(stream, "%-7s", op->name()); switch (op->mode()) { + case PG2: + case PG3: case INH: // No operands break; @@ -198,23 +257,23 @@ offs_t m6x09_base_disassembler::disassemble(std::ostream &stream, offs_t pc, con case REL: offset = (int8_t)params.r8(ppc); - util::stream_format(stream, "$%04X", (pc + op->length() + offset) & 0xffff); + util::stream_format(stream, "$%04X", (p + offset) & 0xffff); break; case LREL: offset = (int16_t)params.r16(ppc); - util::stream_format(stream, "$%04X", (pc + op->length() + offset) & 0xffff); + util::stream_format(stream, "$%04X", (p + offset) & 0xffff); break; case EXT: - if (numoperands == 3) + if (op->operand_length() == 3) { assert_hd6309_exclusive(); pb = params.r8(ppc); ea = params.r16(ppc+1); util::stream_format(stream, "#$%02X,$%04X", pb, ea); } - else if (numoperands == 2) + else if (op->operand_length() == 2) { ea = params.r16(ppc); if( !(ea & 0xff00) ) @@ -226,7 +285,7 @@ offs_t m6x09_base_disassembler::disassemble(std::ostream &stream, offs_t pc, con break; case IND: - if (numoperands == 2) + if (op->operand_length() == 2) { assert_hd6309_exclusive(); util::stream_format(stream, "#$%02X;", params.r8(ppc)); @@ -241,19 +300,19 @@ offs_t m6x09_base_disassembler::disassemble(std::ostream &stream, offs_t pc, con break; case IMM: - if (numoperands == 4) + if (op->operand_length() == 4) { ea = params.r32(ppc); util::stream_format(stream, "#$%08X", ea); } else - if (numoperands == 2) + if (op->operand_length() == 2) { ea = params.r16(ppc); util::stream_format(stream, "#$%04X", ea); } else - if (numoperands == 1) + if (op->operand_length() == 1) { ea = params.r8(ppc); util::stream_format(stream, "#$%02X", ea); @@ -292,525 +351,550 @@ offs_t m6x09_base_disassembler::disassemble(std::ostream &stream, offs_t pc, con const m6x09_base_disassembler::opcodeinfo m6x09_disassembler::m6x09_opcodes[] = { - // Page 0 opcodes (single byte) - { 0x00, 2, "NEG", DIR, M6x09_GENERAL }, - { 0x01, 3, "OIM", DIR_IM, HD6309_EXCLUSIVE }, - { 0x02, 3, "AIM", DIR_IM, HD6309_EXCLUSIVE }, - { 0x03, 2, "COM", DIR, M6x09_GENERAL }, - { 0x04, 2, "LSR", DIR, M6x09_GENERAL }, - { 0x05, 3, "EIM", DIR_IM, HD6309_EXCLUSIVE }, - { 0x06, 2, "ROR", DIR, M6x09_GENERAL }, - { 0x07, 2, "ASR", DIR, M6x09_GENERAL }, - { 0x08, 2, "ASL", DIR, M6x09_GENERAL }, - { 0x09, 2, "ROL", DIR, M6x09_GENERAL }, - { 0x0A, 2, "DEC", DIR, M6x09_GENERAL }, - { 0x0B, 3, "TIM", DIR_IM, HD6309_EXCLUSIVE }, - { 0x0C, 2, "INC", DIR, M6x09_GENERAL }, - { 0x0D, 2, "TST", DIR, M6x09_GENERAL }, - { 0x0E, 2, "JMP", DIR, M6x09_GENERAL }, - { 0x0F, 2, "CLR", DIR, M6x09_GENERAL }, - - { 0x10, 1, "page1", PG1, M6x09_GENERAL }, - { 0x11, 1, "page2", PG2, M6x09_GENERAL }, - { 0x12, 1, "NOP", INH, M6x09_GENERAL }, - { 0x13, 1, "SYNC", INH, M6x09_GENERAL }, - { 0x14, 1, "SEXW", INH, HD6309_EXCLUSIVE }, - { 0x16, 3, "LBRA", LREL, M6x09_GENERAL }, - { 0x17, 3, "LBSR", LREL, M6x09_GENERAL, STEP_OVER }, - { 0x19, 1, "DAA", INH, M6x09_GENERAL }, - { 0x1A, 2, "ORCC", IMM, M6x09_GENERAL }, - { 0x1C, 2, "ANDCC", IMM, M6x09_GENERAL }, - { 0x1D, 1, "SEX", INH, M6x09_GENERAL }, - { 0x1E, 2, "EXG", IMM_RR, M6x09_GENERAL }, - { 0x1F, 2, "TFR", IMM_RR, M6x09_GENERAL }, - - { 0x20, 2, "BRA", REL, M6x09_GENERAL }, - { 0x21, 2, "BRN", REL, M6x09_GENERAL }, - { 0x22, 2, "BHI", REL, M6x09_GENERAL, STEP_COND }, - { 0x23, 2, "BLS", REL, M6x09_GENERAL, STEP_COND }, - { 0x24, 2, "BCC", REL, M6x09_GENERAL, STEP_COND }, - { 0x25, 2, "BCS", REL, M6x09_GENERAL, STEP_COND }, - { 0x26, 2, "BNE", REL, M6x09_GENERAL, STEP_COND }, - { 0x27, 2, "BEQ", REL, M6x09_GENERAL, STEP_COND }, - { 0x28, 2, "BVC", REL, M6x09_GENERAL, STEP_COND }, - { 0x29, 2, "BVS", REL, M6x09_GENERAL, STEP_COND }, - { 0x2A, 2, "BPL", REL, M6x09_GENERAL, STEP_COND }, - { 0x2B, 2, "BMI", REL, M6x09_GENERAL, STEP_COND }, - { 0x2C, 2, "BGE", REL, M6x09_GENERAL, STEP_COND }, - { 0x2D, 2, "BLT", REL, M6x09_GENERAL, STEP_COND }, - { 0x2E, 2, "BGT", REL, M6x09_GENERAL, STEP_COND }, - { 0x2F, 2, "BLE", REL, M6x09_GENERAL, STEP_COND }, - - { 0x30, 2, "LEAX", IND, M6x09_GENERAL }, - { 0x31, 2, "LEAY", IND, M6x09_GENERAL }, - { 0x32, 2, "LEAS", IND, M6x09_GENERAL }, - { 0x33, 2, "LEAU", IND, M6x09_GENERAL }, - { 0x34, 2, "PSHS", PSHS, M6x09_GENERAL }, - { 0x35, 2, "PULS", PULS, M6x09_GENERAL }, - { 0x36, 2, "PSHU", PSHU, M6x09_GENERAL }, - { 0x37, 2, "PULU", PULU, M6x09_GENERAL }, - { 0x39, 1, "RTS", INH , M6x09_GENERAL, STEP_OUT }, - { 0x3A, 1, "ABX", INH, M6x09_GENERAL }, - { 0x3B, 1, "RTI", INH, M6x09_GENERAL, STEP_OUT }, - { 0x3C, 2, "CWAI", IMM, M6x09_GENERAL }, - { 0x3D, 1, "MUL", INH, M6x09_GENERAL }, - { 0x3F, 1, "SWI", INH, M6x09_GENERAL }, - - { 0x40, 1, "NEGA", INH, M6x09_GENERAL }, - { 0x43, 1, "COMA", INH, M6x09_GENERAL }, - { 0x44, 1, "LSRA", INH, M6x09_GENERAL }, - { 0x46, 1, "RORA", INH, M6x09_GENERAL }, - { 0x47, 1, "ASRA", INH, M6x09_GENERAL }, - { 0x48, 1, "ASLA", INH, M6x09_GENERAL }, - { 0x49, 1, "ROLA", INH, M6x09_GENERAL }, - { 0x4A, 1, "DECA", INH, M6x09_GENERAL }, - { 0x4C, 1, "INCA", INH, M6x09_GENERAL }, - { 0x4D, 1, "TSTA", INH, M6x09_GENERAL }, - { 0x4F, 1, "CLRA", INH, M6x09_GENERAL }, - - { 0x50, 1, "NEGB", INH, M6x09_GENERAL }, - { 0x53, 1, "COMB", INH, M6x09_GENERAL }, - { 0x54, 1, "LSRB", INH, M6x09_GENERAL }, - { 0x56, 1, "RORB", INH, M6x09_GENERAL }, - { 0x57, 1, "ASRB", INH, M6x09_GENERAL }, - { 0x58, 1, "ASLB", INH, M6x09_GENERAL }, - { 0x59, 1, "ROLB", INH, M6x09_GENERAL }, - { 0x5A, 1, "DECB", INH, M6x09_GENERAL }, - { 0x5C, 1, "INCB", INH, M6x09_GENERAL }, - { 0x5D, 1, "TSTB", INH, M6x09_GENERAL }, - { 0x5F, 1, "CLRB", INH, M6x09_GENERAL }, - - { 0x60, 2, "NEG", IND, M6x09_GENERAL }, - { 0x61, 3, "OIM", IND, HD6309_EXCLUSIVE }, - { 0x62, 3, "AIM", IND, HD6309_EXCLUSIVE }, - { 0x63, 2, "COM", IND, M6x09_GENERAL }, - { 0x64, 2, "LSR", IND, M6x09_GENERAL }, - { 0x65, 3, "EIM", IND, HD6309_EXCLUSIVE }, - { 0x66, 2, "ROR", IND, M6x09_GENERAL }, - { 0x67, 2, "ASR", IND, M6x09_GENERAL }, - { 0x68, 2, "ASL", IND, M6x09_GENERAL }, - { 0x69, 2, "ROL", IND, M6x09_GENERAL }, - { 0x6A, 2, "DEC", IND, M6x09_GENERAL }, - { 0x6B, 3, "TIM", IND, HD6309_EXCLUSIVE }, - { 0x6C, 2, "INC", IND, M6x09_GENERAL }, - { 0x6D, 2, "TST", IND, M6x09_GENERAL }, - { 0x6E, 2, "JMP", IND, M6x09_GENERAL }, - { 0x6F, 2, "CLR", IND, M6x09_GENERAL }, - - { 0x70, 3, "NEG", EXT, M6x09_GENERAL }, - { 0x71, 4, "OIM", EXT, HD6309_EXCLUSIVE }, - { 0x72, 4, "AIM", EXT, HD6309_EXCLUSIVE }, - { 0x73, 3, "COM", EXT, M6x09_GENERAL }, - { 0x74, 3, "LSR", EXT, M6x09_GENERAL }, - { 0x75, 4, "EIM", EXT, HD6309_EXCLUSIVE }, - { 0x76, 3, "ROR", EXT, M6x09_GENERAL }, - { 0x77, 3, "ASR", EXT, M6x09_GENERAL }, - { 0x78, 3, "ASL", EXT, M6x09_GENERAL }, - { 0x79, 3, "ROL", EXT, M6x09_GENERAL }, - { 0x7A, 3, "DEC", EXT, M6x09_GENERAL }, - { 0x7B, 4, "TIM", EXT, HD6309_EXCLUSIVE }, - { 0x7C, 3, "INC", EXT, M6x09_GENERAL }, - { 0x7D, 3, "TST", EXT, M6x09_GENERAL }, - { 0x7E, 3, "JMP", EXT, M6x09_GENERAL }, - { 0x7F, 3, "CLR", EXT, M6x09_GENERAL }, - - { 0x80, 2, "SUBA", IMM, M6x09_GENERAL }, - { 0x81, 2, "CMPA", IMM, M6x09_GENERAL }, - { 0x82, 2, "SBCA", IMM, M6x09_GENERAL }, - { 0x83, 3, "SUBD", IMM, M6x09_GENERAL }, - { 0x84, 2, "ANDA", IMM, M6x09_GENERAL }, - { 0x85, 2, "BITA", IMM, M6x09_GENERAL }, - { 0x86, 2, "LDA", IMM, M6x09_GENERAL }, - { 0x88, 2, "EORA", IMM, M6x09_GENERAL }, - { 0x89, 2, "ADCA", IMM, M6x09_GENERAL }, - { 0x8A, 2, "ORA", IMM, M6x09_GENERAL }, - { 0x8B, 2, "ADDA", IMM, M6x09_GENERAL }, - { 0x8C, 3, "CMPX", IMM, M6x09_GENERAL }, - { 0x8D, 2, "BSR", REL, M6x09_GENERAL, STEP_OVER }, - { 0x8E, 3, "LDX", IMM, M6x09_GENERAL }, - - { 0x90, 2, "SUBA", DIR, M6x09_GENERAL }, - { 0x91, 2, "CMPA", DIR, M6x09_GENERAL }, - { 0x92, 2, "SBCA", DIR, M6x09_GENERAL }, - { 0x93, 2, "SUBD", DIR, M6x09_GENERAL }, - { 0x94, 2, "ANDA", DIR, M6x09_GENERAL }, - { 0x95, 2, "BITA", DIR, M6x09_GENERAL }, - { 0x96, 2, "LDA", DIR, M6x09_GENERAL }, - { 0x97, 2, "STA", DIR, M6x09_GENERAL }, - { 0x98, 2, "EORA", DIR, M6x09_GENERAL }, - { 0x99, 2, "ADCA", DIR, M6x09_GENERAL }, - { 0x9A, 2, "ORA", DIR, M6x09_GENERAL }, - { 0x9B, 2, "ADDA", DIR, M6x09_GENERAL }, - { 0x9C, 2, "CMPX", DIR, M6x09_GENERAL }, - { 0x9D, 2, "JSR", DIR, M6x09_GENERAL, STEP_OVER }, - { 0x9E, 2, "LDX", DIR, M6x09_GENERAL }, - { 0x9F, 2, "STX", DIR, M6x09_GENERAL }, - - { 0xA0, 2, "SUBA", IND, M6x09_GENERAL }, - { 0xA1, 2, "CMPA", IND, M6x09_GENERAL }, - { 0xA2, 2, "SBCA", IND, M6x09_GENERAL }, - { 0xA3, 2, "SUBD", IND, M6x09_GENERAL }, - { 0xA4, 2, "ANDA", IND, M6x09_GENERAL }, - { 0xA5, 2, "BITA", IND, M6x09_GENERAL }, - { 0xA6, 2, "LDA", IND, M6x09_GENERAL }, - { 0xA7, 2, "STA", IND, M6x09_GENERAL }, - { 0xA8, 2, "EORA", IND, M6x09_GENERAL }, - { 0xA9, 2, "ADCA", IND, M6x09_GENERAL }, - { 0xAA, 2, "ORA", IND, M6x09_GENERAL }, - { 0xAB, 2, "ADDA", IND, M6x09_GENERAL }, - { 0xAC, 2, "CMPX", IND, M6x09_GENERAL }, - { 0xAD, 2, "JSR", IND, M6x09_GENERAL, STEP_OVER }, - { 0xAE, 2, "LDX", IND, M6x09_GENERAL }, - { 0xAF, 2, "STX", IND, M6x09_GENERAL }, - - { 0xB0, 3, "SUBA", EXT, M6x09_GENERAL }, - { 0xB1, 3, "CMPA", EXT, M6x09_GENERAL }, - { 0xB2, 3, "SBCA", EXT, M6x09_GENERAL }, - { 0xB3, 3, "SUBD", EXT, M6x09_GENERAL }, - { 0xB4, 3, "ANDA", EXT, M6x09_GENERAL }, - { 0xB5, 3, "BITA", EXT, M6x09_GENERAL }, - { 0xB6, 3, "LDA", EXT, M6x09_GENERAL }, - { 0xB7, 3, "STA", EXT, M6x09_GENERAL }, - { 0xB8, 3, "EORA", EXT, M6x09_GENERAL }, - { 0xB9, 3, "ADCA", EXT, M6x09_GENERAL }, - { 0xBA, 3, "ORA", EXT, M6x09_GENERAL }, - { 0xBB, 3, "ADDA", EXT, M6x09_GENERAL }, - { 0xBC, 3, "CMPX", EXT, M6x09_GENERAL }, - { 0xBD, 3, "JSR", EXT, M6x09_GENERAL, STEP_OVER }, - { 0xBE, 3, "LDX", EXT, M6x09_GENERAL }, - { 0xBF, 3, "STX", EXT, M6x09_GENERAL }, - - { 0xC0, 2, "SUBB", IMM, M6x09_GENERAL }, - { 0xC1, 2, "CMPB", IMM, M6x09_GENERAL }, - { 0xC2, 2, "SBCB", IMM, M6x09_GENERAL }, - { 0xC3, 3, "ADDD", IMM, M6x09_GENERAL }, - { 0xC4, 2, "ANDB", IMM, M6x09_GENERAL }, - { 0xC5, 2, "BITB", IMM, M6x09_GENERAL }, - { 0xC6, 2, "LDB", IMM, M6x09_GENERAL }, - { 0xC8, 2, "EORB", IMM, M6x09_GENERAL }, - { 0xC9, 2, "ADCB", IMM, M6x09_GENERAL }, - { 0xCA, 2, "ORB", IMM, M6x09_GENERAL }, - { 0xCB, 2, "ADDB", IMM, M6x09_GENERAL }, - { 0xCC, 3, "LDD", IMM, M6x09_GENERAL }, - { 0xCD, 5, "LDQ", IMM, HD6309_EXCLUSIVE }, - { 0xCE, 3, "LDU", IMM, M6x09_GENERAL }, - - { 0xD0, 2, "SUBB", DIR, M6x09_GENERAL }, - { 0xD1, 2, "CMPB", DIR, M6x09_GENERAL }, - { 0xD2, 2, "SBCB", DIR, M6x09_GENERAL }, - { 0xD3, 2, "ADDD", DIR, M6x09_GENERAL }, - { 0xD4, 2, "ANDB", DIR, M6x09_GENERAL }, - { 0xD5, 2, "BITB", DIR, M6x09_GENERAL }, - { 0xD6, 2, "LDB", DIR, M6x09_GENERAL }, - { 0xD7, 2, "STB", DIR, M6x09_GENERAL }, - { 0xD8, 2, "EORB", DIR, M6x09_GENERAL }, - { 0xD9, 2, "ADCB", DIR, M6x09_GENERAL }, - { 0xDA, 2, "ORB", DIR, M6x09_GENERAL }, - { 0xDB, 2, "ADDB", DIR, M6x09_GENERAL }, - { 0xDC, 2, "LDD", DIR, M6x09_GENERAL }, - { 0xDD, 2, "STD", DIR, M6x09_GENERAL }, - { 0xDE, 2, "LDU", DIR, M6x09_GENERAL }, - { 0xDF, 2, "STU", DIR, M6x09_GENERAL }, - - { 0xE0, 2, "SUBB", IND, M6x09_GENERAL }, - { 0xE1, 2, "CMPB", IND, M6x09_GENERAL }, - { 0xE2, 2, "SBCB", IND, M6x09_GENERAL }, - { 0xE3, 2, "ADDD", IND, M6x09_GENERAL }, - { 0xE4, 2, "ANDB", IND, M6x09_GENERAL }, - { 0xE5, 2, "BITB", IND, M6x09_GENERAL }, - { 0xE6, 2, "LDB", IND, M6x09_GENERAL }, - { 0xE7, 2, "STB", IND, M6x09_GENERAL }, - { 0xE8, 2, "EORB", IND, M6x09_GENERAL }, - { 0xE9, 2, "ADCB", IND, M6x09_GENERAL }, - { 0xEA, 2, "ORB", IND, M6x09_GENERAL }, - { 0xEB, 2, "ADDB", IND, M6x09_GENERAL }, - { 0xEC, 2, "LDD", IND, M6x09_GENERAL }, - { 0xED, 2, "STD", IND, M6x09_GENERAL }, - { 0xEE, 2, "LDU", IND, M6x09_GENERAL }, - { 0xEF, 2, "STU", IND, M6x09_GENERAL }, - - { 0xF0, 3, "SUBB", EXT, M6x09_GENERAL }, - { 0xF1, 3, "CMPB", EXT, M6x09_GENERAL }, - { 0xF2, 3, "SBCB", EXT, M6x09_GENERAL }, - { 0xF3, 3, "ADDD", EXT, M6x09_GENERAL }, - { 0xF4, 3, "ANDB", EXT, M6x09_GENERAL }, - { 0xF5, 3, "BITB", EXT, M6x09_GENERAL }, - { 0xF6, 3, "LDB", EXT, M6x09_GENERAL }, - { 0xF7, 3, "STB", EXT, M6x09_GENERAL }, - { 0xF8, 3, "EORB", EXT, M6x09_GENERAL }, - { 0xF9, 3, "ADCB", EXT, M6x09_GENERAL }, - { 0xFA, 3, "ORB", EXT, M6x09_GENERAL }, - { 0xFB, 3, "ADDB", EXT, M6x09_GENERAL }, - { 0xFC, 3, "LDD", EXT, M6x09_GENERAL }, - { 0xFD, 3, "STD", EXT, M6x09_GENERAL }, - { 0xFE, 3, "LDU", EXT, M6x09_GENERAL }, - { 0xFF, 3, "STU", EXT, M6x09_GENERAL }, - - // Page 1 opcodes (0x10 0x..) - { 0x1021, 4, "LBRN", LREL, M6x09_GENERAL }, - { 0x1022, 4, "LBHI", LREL, M6x09_GENERAL }, - { 0x1023, 4, "LBLS", LREL, M6x09_GENERAL }, - { 0x1024, 4, "LBCC", LREL, M6x09_GENERAL }, - { 0x1025, 4, "LBCS", LREL, M6x09_GENERAL }, - { 0x1026, 4, "LBNE", LREL, M6x09_GENERAL }, - { 0x1027, 4, "LBEQ", LREL, M6x09_GENERAL }, - { 0x1028, 4, "LBVC", LREL, M6x09_GENERAL }, - { 0x1029, 4, "LBVS", LREL, M6x09_GENERAL }, - { 0x102A, 4, "LBPL", LREL, M6x09_GENERAL }, - { 0x102B, 4, "LBMI", LREL, M6x09_GENERAL }, - { 0x102C, 4, "LBGE", LREL, M6x09_GENERAL }, - { 0x102D, 4, "LBLT", LREL, M6x09_GENERAL }, - { 0x102E, 4, "LBGT", LREL, M6x09_GENERAL }, - { 0x102F, 4, "LBLE", LREL, M6x09_GENERAL }, - - { 0x1030, 3, "ADDR", IMM_RR, HD6309_EXCLUSIVE }, - { 0x1031, 3, "ADCR", IMM_RR, HD6309_EXCLUSIVE }, - { 0x1032, 3, "SUBR", IMM_RR, HD6309_EXCLUSIVE }, - { 0x1033, 3, "SBCR", IMM_RR, HD6309_EXCLUSIVE }, - { 0x1034, 3, "ANDR", IMM_RR, HD6309_EXCLUSIVE }, - { 0x1035, 3, "ORR", IMM_RR, HD6309_EXCLUSIVE }, - { 0x1036, 3, "EORR", IMM_RR, HD6309_EXCLUSIVE }, - { 0x1037, 3, "CMPR", IMM_RR, HD6309_EXCLUSIVE }, - - { 0x1038, 2, "PSHSW", INH, HD6309_EXCLUSIVE }, - { 0x1039, 2, "PULSW", INH, HD6309_EXCLUSIVE }, - { 0x103A, 2, "PSHUW", INH, HD6309_EXCLUSIVE }, - { 0x103B, 2, "PULUW", INH, HD6309_EXCLUSIVE }, - - { 0x103F, 2, "SWI2", INH, M6x09_GENERAL }, - - { 0x1040, 2, "NEGD", INH, HD6309_EXCLUSIVE }, - { 0x1043, 2, "COMD", INH, HD6309_EXCLUSIVE }, - { 0x1044, 2, "LSRD", INH, HD6309_EXCLUSIVE }, - { 0x1046, 2, "RORD", INH, HD6309_EXCLUSIVE }, - { 0x1047, 2, "ASRD", INH, HD6309_EXCLUSIVE }, - { 0x1048, 2, "ASLD", INH, HD6309_EXCLUSIVE }, - { 0x1049, 2, "ROLD", INH, HD6309_EXCLUSIVE }, - - { 0x104A, 2, "DECD", INH, HD6309_EXCLUSIVE }, - { 0x104C, 2, "INCD", INH, HD6309_EXCLUSIVE }, - { 0x104D, 2, "TSTD", INH, HD6309_EXCLUSIVE }, - { 0x104f, 2, "CLRD", INH, HD6309_EXCLUSIVE }, - - { 0x1053, 2, "COMW", INH, HD6309_EXCLUSIVE }, - { 0x1054, 2, "LSRW", INH, HD6309_EXCLUSIVE }, - { 0x1056, 2, "RORW", INH, HD6309_EXCLUSIVE }, - { 0x1059, 2, "ROLW", INH, HD6309_EXCLUSIVE }, - { 0x105A, 2, "DECW", INH, HD6309_EXCLUSIVE }, - { 0x105C, 2, "INCW", INH, HD6309_EXCLUSIVE }, - { 0x105D, 2, "TSTW", INH, HD6309_EXCLUSIVE }, - { 0x105F, 2, "CLRW", INH, HD6309_EXCLUSIVE }, - { 0x1080, 4, "SUBW", IMM, HD6309_EXCLUSIVE }, - { 0x1081, 4, "CMPW", IMM, HD6309_EXCLUSIVE }, - { 0x1082, 4, "SBCD", IMM, HD6309_EXCLUSIVE }, - - { 0x1083, 4, "CMPD", IMM, M6x09_GENERAL }, - - { 0x1084, 4, "ANDD", IMM, HD6309_EXCLUSIVE }, - { 0x1085, 4, "BITD", IMM, HD6309_EXCLUSIVE }, - { 0x1086, 4, "LDW", IMM, HD6309_EXCLUSIVE }, - { 0x1088, 4, "EORD", IMM, HD6309_EXCLUSIVE }, - { 0x1089, 4, "ADCD", IMM, HD6309_EXCLUSIVE }, - { 0x108A, 4, "ORD", IMM, HD6309_EXCLUSIVE }, - { 0x108B, 4, "ADDW", IMM, HD6309_EXCLUSIVE }, - - { 0x108C, 4, "CMPY", IMM, M6x09_GENERAL }, - { 0x108E, 4, "LDY", IMM, M6x09_GENERAL }, - - { 0x1090, 3, "SUBW", DIR, HD6309_EXCLUSIVE }, - { 0x1091, 3, "CMPW", DIR, HD6309_EXCLUSIVE }, - { 0x1092, 3, "SBCD", DIR, HD6309_EXCLUSIVE }, - - { 0x1093, 3, "CMPD", DIR, M6x09_GENERAL }, - - { 0x1094, 3, "ANDD", DIR, HD6309_EXCLUSIVE }, - { 0x1095, 3, "BITD", DIR, HD6309_EXCLUSIVE }, - { 0x1096, 3, "LDW", DIR, HD6309_EXCLUSIVE }, - { 0x1097, 3, "STW", DIR, HD6309_EXCLUSIVE }, - { 0x1098, 3, "EORD", DIR, HD6309_EXCLUSIVE }, - { 0x1099, 3, "ADCD", DIR, HD6309_EXCLUSIVE }, - { 0x109A, 3, "ORD", DIR, HD6309_EXCLUSIVE }, - { 0x109B, 3, "ADDW", DIR, HD6309_EXCLUSIVE }, - - { 0x109C, 3, "CMPY", DIR, M6x09_GENERAL }, - { 0x109E, 3, "LDY", DIR, M6x09_GENERAL }, - { 0x109F, 3, "STY", DIR, M6x09_GENERAL }, - - { 0x10A0, 3, "SUBW", IND, HD6309_EXCLUSIVE }, - { 0x10A1, 3, "CMPW", IND, HD6309_EXCLUSIVE }, - { 0x10A2, 3, "SBCD", IND, HD6309_EXCLUSIVE }, - - { 0x10A3, 3, "CMPD", IND, M6x09_GENERAL }, - - { 0x10A4, 3, "ANDD", IND, HD6309_EXCLUSIVE }, - { 0x10A5, 3, "BITD", IND, HD6309_EXCLUSIVE }, - - { 0x10A6, 3, "LDW", IND, HD6309_EXCLUSIVE }, - { 0x10A7, 3, "STW", IND, HD6309_EXCLUSIVE }, - { 0x10A8, 3, "EORD", IND, HD6309_EXCLUSIVE }, - { 0x10A9, 3, "ADCD", IND, HD6309_EXCLUSIVE }, - { 0x10AA, 3, "ORD", IND, HD6309_EXCLUSIVE }, - { 0x10AB, 3, "ADDW", IND, HD6309_EXCLUSIVE }, - - { 0x10AC, 3, "CMPY", IND, M6x09_GENERAL }, - { 0x10AE, 3, "LDY", IND, M6x09_GENERAL }, - { 0x10AF, 3, "STY", IND, M6x09_GENERAL }, - - { 0x10B0, 4, "SUBW", EXT, HD6309_EXCLUSIVE }, - { 0x10B1, 4, "CMPW", EXT, HD6309_EXCLUSIVE }, - { 0x10B2, 4, "SBCD", EXT, HD6309_EXCLUSIVE }, - - { 0x10B3, 4, "CMPD", EXT, M6x09_GENERAL }, - - { 0x10B4, 4, "ANDD", EXT, HD6309_EXCLUSIVE }, - { 0x10B5, 4, "BITD", EXT, HD6309_EXCLUSIVE }, - { 0x10B6, 4, "LDW", EXT, HD6309_EXCLUSIVE }, - { 0x10B7, 4, "STW", EXT, HD6309_EXCLUSIVE }, - { 0x10B8, 4, "EORD", EXT, HD6309_EXCLUSIVE }, - { 0x10B9, 4, "ADCD", EXT, HD6309_EXCLUSIVE }, - { 0x10BA, 4, "ORD", EXT, HD6309_EXCLUSIVE }, - { 0x10BB, 4, "ADDW", EXT, HD6309_EXCLUSIVE }, - - { 0x10BC, 4, "CMPY", EXT, M6x09_GENERAL }, - { 0x10BE, 4, "LDY", EXT, M6x09_GENERAL }, - { 0x10BF, 4, "STY", EXT, M6x09_GENERAL }, - { 0x10CE, 4, "LDS", IMM, M6x09_GENERAL }, - - { 0x10DC, 3, "LDQ", DIR, HD6309_EXCLUSIVE }, - { 0x10DD, 3, "STQ", DIR, HD6309_EXCLUSIVE }, - - { 0x10DE, 3, "LDS", DIR, M6x09_GENERAL }, - { 0x10DF, 3, "STS", DIR, M6x09_GENERAL }, - - { 0x10EC, 3, "LDQ", IND, HD6309_EXCLUSIVE }, - { 0x10ED, 3, "STQ", IND, HD6309_EXCLUSIVE }, - - { 0x10EE, 3, "LDS", IND, M6x09_GENERAL }, - { 0x10EF, 3, "STS", IND, M6x09_GENERAL }, - - { 0x10FC, 4, "LDQ", EXT, HD6309_EXCLUSIVE }, - { 0x10FD, 4, "STQ", EXT, HD6309_EXCLUSIVE }, - - { 0x10FE, 4, "LDS", EXT, M6x09_GENERAL }, - { 0x10FF, 4, "STS", EXT, M6x09_GENERAL }, - - // Page 2 opcodes (0x11 0x..) - { 0x1130, 4, "BAND", IMM_BW, HD6309_EXCLUSIVE }, - { 0x1131, 4, "BIAND", IMM_BW, HD6309_EXCLUSIVE }, - { 0x1132, 4, "BOR", IMM_BW, HD6309_EXCLUSIVE }, - { 0x1133, 4, "BIOR", IMM_BW, HD6309_EXCLUSIVE }, - { 0x1134, 4, "BEOR", IMM_BW, HD6309_EXCLUSIVE }, - { 0x1135, 4, "BIEOR", IMM_BW, HD6309_EXCLUSIVE }, - - { 0x1136, 4, "LDBT", IMM_BW, HD6309_EXCLUSIVE }, - { 0x1137, 4, "STBT", IMM_BW, HD6309_EXCLUSIVE }, - - { 0x1138, 3, "TFM", IMM_TFM, HD6309_EXCLUSIVE }, - { 0x1139, 3, "TFM", IMM_TFM, HD6309_EXCLUSIVE }, - { 0x113A, 3, "TFM", IMM_TFM, HD6309_EXCLUSIVE }, - { 0x113B, 3, "TFM", IMM_TFM, HD6309_EXCLUSIVE }, - - { 0x113C, 3, "BITMD", IMM, HD6309_EXCLUSIVE }, - { 0x113D, 3, "LDMD", IMM, HD6309_EXCLUSIVE }, - - { 0x113F, 2, "SWI3", INH, M6x09_GENERAL }, - - { 0x1143, 2, "COME", INH, HD6309_EXCLUSIVE }, - { 0x114A, 2, "DECE", INH, HD6309_EXCLUSIVE }, - { 0x114C, 2, "INCE", INH, HD6309_EXCLUSIVE }, - { 0x114D, 2, "TSTE", INH, HD6309_EXCLUSIVE }, - { 0x114F, 2, "CLRE", INH, HD6309_EXCLUSIVE }, - { 0x1153, 2, "COMF", INH, HD6309_EXCLUSIVE }, - { 0x115A, 2, "DECF", INH, HD6309_EXCLUSIVE }, - { 0x115C, 2, "INCF", INH, HD6309_EXCLUSIVE }, - { 0x115D, 2, "TSTF", INH, HD6309_EXCLUSIVE }, - { 0x115F, 2, "CLRF", INH, HD6309_EXCLUSIVE }, - - { 0x1180, 3, "SUBE", IMM, HD6309_EXCLUSIVE }, - { 0x1181, 3, "CMPE", IMM, HD6309_EXCLUSIVE }, - - { 0x1183, 4, "CMPU", IMM, M6x09_GENERAL }, - - { 0x1186, 3, "LDE", IMM, HD6309_EXCLUSIVE }, - { 0x118B, 3, "ADDE", IMM, HD6309_EXCLUSIVE }, - - { 0x118C, 4, "CMPS", IMM, M6x09_GENERAL }, - - { 0x118D, 3, "DIVD", IMM, HD6309_EXCLUSIVE }, - { 0x118E, 4, "DIVQ", IMM, HD6309_EXCLUSIVE }, - { 0x118F, 4, "MULD", IMM, HD6309_EXCLUSIVE }, - { 0x1190, 3, "SUBE", DIR, HD6309_EXCLUSIVE }, - { 0x1191, 3, "CMPE", DIR, HD6309_EXCLUSIVE }, - - { 0x1193, 3, "CMPU", DIR, M6x09_GENERAL }, - - { 0x1196, 3, "LDE", DIR, HD6309_EXCLUSIVE }, - { 0x1197, 3, "STE", DIR, HD6309_EXCLUSIVE }, - { 0x119B, 3, "ADDE", DIR, HD6309_EXCLUSIVE }, - - { 0x119C, 3, "CMPS", DIR, M6x09_GENERAL }, - - { 0x119D, 3, "DIVD", DIR, HD6309_EXCLUSIVE }, - { 0x119E, 3, "DIVQ", DIR, HD6309_EXCLUSIVE }, - { 0x119F, 3, "MULD", DIR, HD6309_EXCLUSIVE }, - - { 0x11A0, 3, "SUBE", IND, HD6309_EXCLUSIVE }, - { 0x11A1, 3, "CMPE", IND, HD6309_EXCLUSIVE }, - - { 0x11A3, 3, "CMPU", IND, M6x09_GENERAL }, - - { 0x11A6, 3, "LDE", IND, HD6309_EXCLUSIVE }, - { 0x11A7, 3, "STE", IND, HD6309_EXCLUSIVE }, - { 0x11AB, 3, "ADDE", IND, HD6309_EXCLUSIVE }, - - { 0x11AC, 3, "CMPS", IND, M6x09_GENERAL }, - - { 0x11AD, 3, "DIVD", IND, HD6309_EXCLUSIVE }, - { 0x11AE, 3, "DIVQ", IND, HD6309_EXCLUSIVE }, - { 0x11AF, 3, "MULD", IND, HD6309_EXCLUSIVE }, - { 0x11B0, 4, "SUBE", EXT, HD6309_EXCLUSIVE }, - { 0x11B1, 4, "CMPE", EXT, HD6309_EXCLUSIVE }, - - { 0x11B3, 4, "CMPU", EXT, M6x09_GENERAL }, - - { 0x11B6, 4, "LDE", EXT, HD6309_EXCLUSIVE }, - { 0x11B7, 4, "STE", EXT, HD6309_EXCLUSIVE }, - - { 0x11BB, 4, "ADDE", EXT, HD6309_EXCLUSIVE }, - { 0x11BC, 4, "CMPS", EXT, M6x09_GENERAL }, - - { 0x11BD, 4, "DIVD", EXT, HD6309_EXCLUSIVE }, - { 0x11BE, 4, "DIVQ", EXT, HD6309_EXCLUSIVE }, - { 0x11BF, 4, "MULD", EXT, HD6309_EXCLUSIVE }, - - { 0x11C0, 3, "SUBF", IMM, HD6309_EXCLUSIVE }, - { 0x11C1, 3, "CMPF", IMM, HD6309_EXCLUSIVE }, - { 0x11C6, 3, "LDF", IMM, HD6309_EXCLUSIVE }, - { 0x11CB, 3, "ADDF", IMM, HD6309_EXCLUSIVE }, - - { 0x11D0, 3, "SUBF", DIR, HD6309_EXCLUSIVE }, - { 0x11D1, 3, "CMPF", DIR, HD6309_EXCLUSIVE }, - { 0x11D6, 3, "LDF", DIR, HD6309_EXCLUSIVE }, - { 0x11D7, 3, "STF", DIR, HD6309_EXCLUSIVE }, - { 0x11DB, 3, "ADDF", DIR, HD6309_EXCLUSIVE }, - - { 0x11E0, 3, "SUBF", IND, HD6309_EXCLUSIVE }, - { 0x11E1, 3, "CMPF", IND, HD6309_EXCLUSIVE }, - { 0x11E6, 3, "LDF", IND, HD6309_EXCLUSIVE }, - { 0x11E7, 3, "STF", IND, HD6309_EXCLUSIVE }, - { 0x11EB, 3, "ADDF", IND, HD6309_EXCLUSIVE }, - - { 0x11F0, 4, "SUBF", EXT, HD6309_EXCLUSIVE }, - { 0x11F1, 4, "CMPF", EXT, HD6309_EXCLUSIVE }, - { 0x11F6, 4, "LDF", EXT, HD6309_EXCLUSIVE }, - { 0x11F7, 4, "STF", EXT, HD6309_EXCLUSIVE }, - { 0x11FB, 4, "ADDF", EXT, HD6309_EXCLUSIVE } + // Page 1 opcodes (single byte) + { 0x00, 1, "NEG", DIR, M6x09_GENERAL }, + { 0x01, 2, "OIM", DIR_IM, HD6309_EXCLUSIVE }, + { 0x01, 1, "NEG", DIR, M6809_UNDOCUMENTED }, + { 0x02, 2, "AIM", DIR_IM, HD6309_EXCLUSIVE }, + { 0x02, 1, "XNC", DIR, M6809_UNDOCUMENTED }, + { 0x03, 1, "COM", DIR, M6x09_GENERAL }, + { 0x04, 1, "LSR", DIR, M6x09_GENERAL }, + { 0x05, 2, "EIM", DIR_IM, HD6309_EXCLUSIVE }, + { 0x05, 1, "LSR", DIR, M6809_UNDOCUMENTED }, + { 0x06, 1, "ROR", DIR, M6x09_GENERAL }, + { 0x07, 1, "ASR", DIR, M6x09_GENERAL }, + { 0x08, 1, "ASL", DIR, M6x09_GENERAL }, + { 0x09, 1, "ROL", DIR, M6x09_GENERAL }, + { 0x0A, 1, "DEC", DIR, M6x09_GENERAL }, + { 0x0B, 2, "TIM", DIR_IM, HD6309_EXCLUSIVE }, + { 0x0B, 1, "XDEC", DIR, M6809_UNDOCUMENTED }, + { 0x0C, 1, "INC", DIR, M6x09_GENERAL }, + { 0x0D, 1, "TST", DIR, M6x09_GENERAL }, + { 0x0E, 1, "JMP", DIR, M6x09_GENERAL }, + { 0x0F, 1, "CLR", DIR, M6x09_GENERAL }, + + { 0x10, 0, "PAGE2", PG2, M6x09_GENERAL }, + { 0x11, 0, "PAGE3", PG3, M6x09_GENERAL }, + { 0x12, 0, "NOP", INH, M6x09_GENERAL }, + { 0x13, 0, "SYNC", INH, M6x09_GENERAL }, + { 0x14, 0, "SEXW", INH, HD6309_EXCLUSIVE }, + { 0x14, 0, "XHCF", INH, M6809_UNDOCUMENTED }, + { 0x15, 0, "XHCF", INH, M6809_UNDOCUMENTED }, + { 0x16, 2, "LBRA", LREL, M6x09_GENERAL }, + { 0x17, 2, "LBSR", LREL, M6x09_GENERAL, STEP_OVER }, + { 0x18, 0, "X18", INH, M6809_UNDOCUMENTED }, + { 0x19, 0, "DAA", INH, M6x09_GENERAL }, + { 0x1A, 1, "ORCC", IMM, M6x09_GENERAL }, + { 0x1B, 0, "NOP", INH, M6809_UNDOCUMENTED }, + { 0x1C, 1, "ANDCC", IMM, M6x09_GENERAL }, + { 0x1D, 0, "SEX", INH, M6x09_GENERAL }, + { 0x1E, 1, "EXG", IMM_RR, M6x09_GENERAL }, + { 0x1F, 1, "TFR", IMM_RR, M6x09_GENERAL }, + + { 0x20, 1, "BRA", REL, M6x09_GENERAL }, + { 0x21, 1, "BRN", REL, M6x09_GENERAL }, + { 0x22, 1, "BHI", REL, M6x09_GENERAL, STEP_COND }, + { 0x23, 1, "BLS", REL, M6x09_GENERAL, STEP_COND }, + { 0x24, 1, "BCC", REL, M6x09_GENERAL, STEP_COND }, + { 0x25, 1, "BCS", REL, M6x09_GENERAL, STEP_COND }, + { 0x26, 1, "BNE", REL, M6x09_GENERAL, STEP_COND }, + { 0x27, 1, "BEQ", REL, M6x09_GENERAL, STEP_COND }, + { 0x28, 1, "BVC", REL, M6x09_GENERAL, STEP_COND }, + { 0x29, 1, "BVS", REL, M6x09_GENERAL, STEP_COND }, + { 0x2A, 1, "BPL", REL, M6x09_GENERAL, STEP_COND }, + { 0x2B, 1, "BMI", REL, M6x09_GENERAL, STEP_COND }, + { 0x2C, 1, "BGE", REL, M6x09_GENERAL, STEP_COND }, + { 0x2D, 1, "BLT", REL, M6x09_GENERAL, STEP_COND }, + { 0x2E, 1, "BGT", REL, M6x09_GENERAL, STEP_COND }, + { 0x2F, 1, "BLE", REL, M6x09_GENERAL, STEP_COND }, + + { 0x30, 1, "LEAX", IND, M6x09_GENERAL }, + { 0x31, 1, "LEAY", IND, M6x09_GENERAL }, + { 0x32, 1, "LEAS", IND, M6x09_GENERAL }, + { 0x33, 1, "LEAU", IND, M6x09_GENERAL }, + { 0x34, 1, "PSHS", PSHS, M6x09_GENERAL }, + { 0x35, 1, "PULS", PULS, M6x09_GENERAL }, + { 0x36, 1, "PSHU", PSHU, M6x09_GENERAL }, + { 0x37, 1, "PULU", PULU, M6x09_GENERAL }, + { 0x38, 1, "XANDCC", IMM, M6809_UNDOCUMENTED }, + { 0x39, 0, "RTS", INH, M6x09_GENERAL, STEP_OUT }, + { 0x3A, 0, "ABX", INH, M6x09_GENERAL }, + { 0x3B, 0, "RTI", INH, M6x09_GENERAL, STEP_OUT }, + { 0x3C, 1, "CWAI", IMM, M6x09_GENERAL }, + { 0x3D, 0, "MUL", INH, M6x09_GENERAL }, + { 0x3E, 0, "XRES", INH, M6809_UNDOCUMENTED }, + { 0x3F, 0, "SWI", INH, M6x09_GENERAL }, + + { 0x40, 0, "NEGA", INH, M6x09_GENERAL }, + { 0x41, 0, "NEGA", INH, M6809_UNDOCUMENTED }, + { 0x42, 0, "XNCA", INH, M6809_UNDOCUMENTED }, + { 0x43, 0, "COMA", INH, M6x09_GENERAL }, + { 0x44, 0, "LSRA", INH, M6x09_GENERAL }, + { 0x45, 0, "LSRA", INH, M6809_UNDOCUMENTED }, + { 0x46, 0, "RORA", INH, M6x09_GENERAL }, + { 0x47, 0, "ASRA", INH, M6x09_GENERAL }, + { 0x48, 0, "ASLA", INH, M6x09_GENERAL }, + { 0x49, 0, "ROLA", INH, M6x09_GENERAL }, + { 0x4A, 0, "DECA", INH, M6x09_GENERAL }, + { 0x4B, 0, "XDECA", INH, M6809_UNDOCUMENTED }, + { 0x4C, 0, "INCA", INH, M6x09_GENERAL }, + { 0x4D, 0, "TSTA", INH, M6x09_GENERAL }, + { 0x4E, 0, "XCLRA", INH, M6809_UNDOCUMENTED }, + { 0x4F, 0, "CLRA", INH, M6x09_GENERAL }, + + { 0x50, 0, "NEGB", INH, M6x09_GENERAL }, + { 0x51, 0, "NEGB", INH, M6809_UNDOCUMENTED }, + { 0x52, 0, "XNCB", INH, M6809_UNDOCUMENTED }, + { 0x53, 0, "COMB", INH, M6x09_GENERAL }, + { 0x54, 0, "LSRB", INH, M6x09_GENERAL }, + { 0x55, 0, "LSRB", INH, M6809_UNDOCUMENTED }, + { 0x56, 0, "RORB", INH, M6x09_GENERAL }, + { 0x57, 0, "ASRB", INH, M6x09_GENERAL }, + { 0x58, 0, "ASLB", INH, M6x09_GENERAL }, + { 0x59, 0, "ROLB", INH, M6x09_GENERAL }, + { 0x5A, 0, "DECB", INH, M6x09_GENERAL }, + { 0x5B, 0, "XDECB", INH, M6809_UNDOCUMENTED }, + { 0x5C, 0, "INCB", INH, M6x09_GENERAL }, + { 0x5D, 0, "TSTB", INH, M6x09_GENERAL }, + { 0x5E, 0, "XCLRB", INH, M6809_UNDOCUMENTED }, + { 0x5F, 0, "CLRB", INH, M6x09_GENERAL }, + + { 0x60, 1, "NEG", IND, M6x09_GENERAL }, + { 0x61, 2, "OIM", IND, HD6309_EXCLUSIVE }, + { 0x61, 1, "NEG", IND, M6809_UNDOCUMENTED }, + { 0x62, 2, "AIM", IND, HD6309_EXCLUSIVE }, + { 0x62, 1, "XNC", IND, M6809_UNDOCUMENTED }, + { 0x63, 1, "COM", IND, M6x09_GENERAL }, + { 0x64, 1, "LSR", IND, M6x09_GENERAL }, + { 0x65, 2, "EIM", IND, HD6309_EXCLUSIVE }, + { 0x65, 1, "LSR", IND, M6809_UNDOCUMENTED }, + { 0x66, 1, "ROR", IND, M6x09_GENERAL }, + { 0x67, 1, "ASR", IND, M6x09_GENERAL }, + { 0x68, 1, "ASL", IND, M6x09_GENERAL }, + { 0x69, 1, "ROL", IND, M6x09_GENERAL }, + { 0x6A, 1, "DEC", IND, M6x09_GENERAL }, + { 0x6B, 2, "TIM", IND, HD6309_EXCLUSIVE }, + { 0x6B, 1, "XDEC", IND, M6809_UNDOCUMENTED }, + { 0x6C, 1, "INC", IND, M6x09_GENERAL }, + { 0x6D, 1, "TST", IND, M6x09_GENERAL }, + { 0x6E, 1, "JMP", IND, M6x09_GENERAL }, + { 0x6F, 1, "CLR", IND, M6x09_GENERAL }, + + { 0x70, 2, "NEG", EXT, M6x09_GENERAL }, + { 0x71, 3, "OIM", EXT, HD6309_EXCLUSIVE }, + { 0x71, 2, "NEG", EXT, M6809_UNDOCUMENTED }, + { 0x72, 3, "AIM", EXT, HD6309_EXCLUSIVE }, + { 0x72, 2, "XNC", EXT, M6809_UNDOCUMENTED }, + { 0x73, 2, "COM", EXT, M6x09_GENERAL }, + { 0x74, 2, "LSR", EXT, M6x09_GENERAL }, + { 0x75, 3, "EIM", EXT, HD6309_EXCLUSIVE }, + { 0x75, 2, "LSR", EXT, M6809_UNDOCUMENTED }, + { 0x76, 2, "ROR", EXT, M6x09_GENERAL }, + { 0x77, 2, "ASR", EXT, M6x09_GENERAL }, + { 0x78, 2, "ASL", EXT, M6x09_GENERAL }, + { 0x79, 2, "ROL", EXT, M6x09_GENERAL }, + { 0x7A, 2, "DEC", EXT, M6x09_GENERAL }, + { 0x7B, 3, "TIM", EXT, HD6309_EXCLUSIVE }, + { 0x7B, 2, "XDEC", EXT, M6809_UNDOCUMENTED }, + { 0x7C, 2, "INC", EXT, M6x09_GENERAL }, + { 0x7D, 2, "TST", EXT, M6x09_GENERAL }, + { 0x7E, 2, "JMP", EXT, M6x09_GENERAL }, + { 0x7F, 2, "CLR", EXT, M6x09_GENERAL }, + + { 0x80, 1, "SUBA", IMM, M6x09_GENERAL }, + { 0x81, 1, "CMPA", IMM, M6x09_GENERAL }, + { 0x82, 1, "SBCA", IMM, M6x09_GENERAL }, + { 0x83, 2, "SUBD", IMM, M6x09_GENERAL }, + { 0x84, 1, "ANDA", IMM, M6x09_GENERAL }, + { 0x85, 1, "BITA", IMM, M6x09_GENERAL }, + { 0x86, 1, "LDA", IMM, M6x09_GENERAL }, + { 0x87, 1, "XSTA", IMM, M6809_UNDOCUMENTED }, + { 0x88, 1, "EORA", IMM, M6x09_GENERAL }, + { 0x89, 1, "ADCA", IMM, M6x09_GENERAL }, + { 0x8A, 1, "ORA", IMM, M6x09_GENERAL }, + { 0x8B, 1, "ADDA", IMM, M6x09_GENERAL }, + { 0x8C, 2, "CMPX", IMM, M6x09_GENERAL }, + { 0x8D, 1, "BSR", REL, M6x09_GENERAL, STEP_OVER }, + { 0x8E, 2, "LDX", IMM, M6x09_GENERAL }, + { 0x8F, 2, "XSTX", IMM, M6809_UNDOCUMENTED }, + + { 0x90, 1, "SUBA", DIR, M6x09_GENERAL }, + { 0x91, 1, "CMPA", DIR, M6x09_GENERAL }, + { 0x92, 1, "SBCA", DIR, M6x09_GENERAL }, + { 0x93, 1, "SUBD", DIR, M6x09_GENERAL }, + { 0x94, 1, "ANDA", DIR, M6x09_GENERAL }, + { 0x95, 1, "BITA", DIR, M6x09_GENERAL }, + { 0x96, 1, "LDA", DIR, M6x09_GENERAL }, + { 0x97, 1, "STA", DIR, M6x09_GENERAL }, + { 0x98, 1, "EORA", DIR, M6x09_GENERAL }, + { 0x99, 1, "ADCA", DIR, M6x09_GENERAL }, + { 0x9A, 1, "ORA", DIR, M6x09_GENERAL }, + { 0x9B, 1, "ADDA", DIR, M6x09_GENERAL }, + { 0x9C, 1, "CMPX", DIR, M6x09_GENERAL }, + { 0x9D, 1, "JSR", DIR, M6x09_GENERAL, STEP_OVER }, + { 0x9E, 1, "LDX", DIR, M6x09_GENERAL }, + { 0x9F, 1, "STX", DIR, M6x09_GENERAL }, + + { 0xA0, 1, "SUBA", IND, M6x09_GENERAL }, + { 0xA1, 1, "CMPA", IND, M6x09_GENERAL }, + { 0xA2, 1, "SBCA", IND, M6x09_GENERAL }, + { 0xA3, 1, "SUBD", IND, M6x09_GENERAL }, + { 0xA4, 1, "ANDA", IND, M6x09_GENERAL }, + { 0xA5, 1, "BITA", IND, M6x09_GENERAL }, + { 0xA6, 1, "LDA", IND, M6x09_GENERAL }, + { 0xA7, 1, "STA", IND, M6x09_GENERAL }, + { 0xA8, 1, "EORA", IND, M6x09_GENERAL }, + { 0xA9, 1, "ADCA", IND, M6x09_GENERAL }, + { 0xAA, 1, "ORA", IND, M6x09_GENERAL }, + { 0xAB, 1, "ADDA", IND, M6x09_GENERAL }, + { 0xAC, 1, "CMPX", IND, M6x09_GENERAL }, + { 0xAD, 1, "JSR", IND, M6x09_GENERAL, STEP_OVER }, + { 0xAE, 1, "LDX", IND, M6x09_GENERAL }, + { 0xAF, 1, "STX", IND, M6x09_GENERAL }, + + { 0xB0, 2, "SUBA", EXT, M6x09_GENERAL }, + { 0xB1, 2, "CMPA", EXT, M6x09_GENERAL }, + { 0xB2, 2, "SBCA", EXT, M6x09_GENERAL }, + { 0xB3, 2, "SUBD", EXT, M6x09_GENERAL }, + { 0xB4, 2, "ANDA", EXT, M6x09_GENERAL }, + { 0xB5, 2, "BITA", EXT, M6x09_GENERAL }, + { 0xB6, 2, "LDA", EXT, M6x09_GENERAL }, + { 0xB7, 2, "STA", EXT, M6x09_GENERAL }, + { 0xB8, 2, "EORA", EXT, M6x09_GENERAL }, + { 0xB9, 2, "ADCA", EXT, M6x09_GENERAL }, + { 0xBA, 2, "ORA", EXT, M6x09_GENERAL }, + { 0xBB, 2, "ADDA", EXT, M6x09_GENERAL }, + { 0xBC, 2, "CMPX", EXT, M6x09_GENERAL }, + { 0xBD, 2, "JSR", EXT, M6x09_GENERAL, STEP_OVER }, + { 0xBE, 2, "LDX", EXT, M6x09_GENERAL }, + { 0xBF, 2, "STX", EXT, M6x09_GENERAL }, + + { 0xC0, 1, "SUBB", IMM, M6x09_GENERAL }, + { 0xC1, 1, "CMPB", IMM, M6x09_GENERAL }, + { 0xC2, 1, "SBCB", IMM, M6x09_GENERAL }, + { 0xC3, 2, "ADDD", IMM, M6x09_GENERAL }, + { 0xC4, 1, "ANDB", IMM, M6x09_GENERAL }, + { 0xC5, 1, "BITB", IMM, M6x09_GENERAL }, + { 0xC6, 1, "LDB", IMM, M6x09_GENERAL }, + { 0xC7, 1, "XSTB", IMM, M6809_UNDOCUMENTED }, + { 0xC8, 1, "EORB", IMM, M6x09_GENERAL }, + { 0xC9, 1, "ADCB", IMM, M6x09_GENERAL }, + { 0xCA, 1, "ORB", IMM, M6x09_GENERAL }, + { 0xCB, 1, "ADDB", IMM, M6x09_GENERAL }, + { 0xCC, 2, "LDD", IMM, M6x09_GENERAL }, + { 0xCD, 4, "LDQ", IMM, HD6309_EXCLUSIVE }, + { 0xCD, 0, "XHCF", INH, M6809_UNDOCUMENTED }, + { 0xCE, 2, "LDU", IMM, M6x09_GENERAL }, + { 0xCF, 2, "XSTU", IMM, M6809_UNDOCUMENTED }, + + { 0xD0, 1, "SUBB", DIR, M6x09_GENERAL }, + { 0xD1, 1, "CMPB", DIR, M6x09_GENERAL }, + { 0xD2, 1, "SBCB", DIR, M6x09_GENERAL }, + { 0xD3, 1, "ADDD", DIR, M6x09_GENERAL }, + { 0xD4, 1, "ANDB", DIR, M6x09_GENERAL }, + { 0xD5, 1, "BITB", DIR, M6x09_GENERAL }, + { 0xD6, 1, "LDB", DIR, M6x09_GENERAL }, + { 0xD7, 1, "STB", DIR, M6x09_GENERAL }, + { 0xD8, 1, "EORB", DIR, M6x09_GENERAL }, + { 0xD9, 1, "ADCB", DIR, M6x09_GENERAL }, + { 0xDA, 1, "ORB", DIR, M6x09_GENERAL }, + { 0xDB, 1, "ADDB", DIR, M6x09_GENERAL }, + { 0xDC, 1, "LDD", DIR, M6x09_GENERAL }, + { 0xDD, 1, "STD", DIR, M6x09_GENERAL }, + { 0xDE, 1, "LDU", DIR, M6x09_GENERAL }, + { 0xDF, 1, "STU", DIR, M6x09_GENERAL }, + + { 0xE0, 1, "SUBB", IND, M6x09_GENERAL }, + { 0xE1, 1, "CMPB", IND, M6x09_GENERAL }, + { 0xE2, 1, "SBCB", IND, M6x09_GENERAL }, + { 0xE3, 1, "ADDD", IND, M6x09_GENERAL }, + { 0xE4, 1, "ANDB", IND, M6x09_GENERAL }, + { 0xE5, 1, "BITB", IND, M6x09_GENERAL }, + { 0xE6, 1, "LDB", IND, M6x09_GENERAL }, + { 0xE7, 1, "STB", IND, M6x09_GENERAL }, + { 0xE8, 1, "EORB", IND, M6x09_GENERAL }, + { 0xE9, 1, "ADCB", IND, M6x09_GENERAL }, + { 0xEA, 1, "ORB", IND, M6x09_GENERAL }, + { 0xEB, 1, "ADDB", IND, M6x09_GENERAL }, + { 0xEC, 1, "LDD", IND, M6x09_GENERAL }, + { 0xED, 1, "STD", IND, M6x09_GENERAL }, + { 0xEE, 1, "LDU", IND, M6x09_GENERAL }, + { 0xEF, 1, "STU", IND, M6x09_GENERAL }, + + { 0xF0, 2, "SUBB", EXT, M6x09_GENERAL }, + { 0xF1, 2, "CMPB", EXT, M6x09_GENERAL }, + { 0xF2, 2, "SBCB", EXT, M6x09_GENERAL }, + { 0xF3, 2, "ADDD", EXT, M6x09_GENERAL }, + { 0xF4, 2, "ANDB", EXT, M6x09_GENERAL }, + { 0xF5, 2, "BITB", EXT, M6x09_GENERAL }, + { 0xF6, 2, "LDB", EXT, M6x09_GENERAL }, + { 0xF7, 2, "STB", EXT, M6x09_GENERAL }, + { 0xF8, 2, "EORB", EXT, M6x09_GENERAL }, + { 0xF9, 2, "ADCB", EXT, M6x09_GENERAL }, + { 0xFA, 2, "ORB", EXT, M6x09_GENERAL }, + { 0xFB, 2, "ADDB", EXT, M6x09_GENERAL }, + { 0xFC, 2, "LDD", EXT, M6x09_GENERAL }, + { 0xFD, 2, "STD", EXT, M6x09_GENERAL }, + { 0xFE, 2, "LDU", EXT, M6x09_GENERAL }, + { 0xFF, 2, "STU", EXT, M6x09_GENERAL }, + + // Page 2 opcodes (0x10 0x..) + { 0x1010, 0, "PAGE2", PG2, M6x09_GENERAL }, + { 0x1011, 0, "PAGE3", PG3, M6x09_GENERAL }, + + { 0x1020, 2, "XLBRA", LREL, M6809_UNDOCUMENTED }, + { 0x1021, 2, "LBRN", LREL, M6x09_GENERAL }, + { 0x1022, 2, "LBHI", LREL, M6x09_GENERAL }, + { 0x1023, 2, "LBLS", LREL, M6x09_GENERAL }, + { 0x1024, 2, "LBCC", LREL, M6x09_GENERAL }, + { 0x1025, 2, "LBCS", LREL, M6x09_GENERAL }, + { 0x1026, 2, "LBNE", LREL, M6x09_GENERAL }, + { 0x1027, 2, "LBEQ", LREL, M6x09_GENERAL }, + { 0x1028, 2, "LBVC", LREL, M6x09_GENERAL }, + { 0x1029, 2, "LBVS", LREL, M6x09_GENERAL }, + { 0x102A, 2, "LBPL", LREL, M6x09_GENERAL }, + { 0x102B, 2, "LBMI", LREL, M6x09_GENERAL }, + { 0x102C, 2, "LBGE", LREL, M6x09_GENERAL }, + { 0x102D, 2, "LBLT", LREL, M6x09_GENERAL }, + { 0x102E, 2, "LBGT", LREL, M6x09_GENERAL }, + { 0x102F, 2, "LBLE", LREL, M6x09_GENERAL }, + + { 0x1030, 1, "ADDR", IMM_RR, HD6309_EXCLUSIVE }, + { 0x1031, 1, "ADCR", IMM_RR, HD6309_EXCLUSIVE }, + { 0x1032, 1, "SUBR", IMM_RR, HD6309_EXCLUSIVE }, + { 0x1033, 1, "SBCR", IMM_RR, HD6309_EXCLUSIVE }, + { 0x1034, 1, "ANDR", IMM_RR, HD6309_EXCLUSIVE }, + { 0x1035, 1, "ORR", IMM_RR, HD6309_EXCLUSIVE }, + { 0x1036, 1, "EORR", IMM_RR, HD6309_EXCLUSIVE }, + { 0x1037, 1, "CMPR", IMM_RR, HD6309_EXCLUSIVE }, + { 0x1038, 0, "PSHSW", INH, HD6309_EXCLUSIVE }, + { 0x1039, 0, "PULSW", INH, HD6309_EXCLUSIVE }, + { 0x103A, 0, "PSHUW", INH, HD6309_EXCLUSIVE }, + { 0x103B, 0, "PULUW", INH, HD6309_EXCLUSIVE }, + { 0x103E, 0, "XSWI2", INH, M6809_UNDOCUMENTED }, + { 0x103F, 0, "SWI2", INH, M6x09_GENERAL }, + + { 0x1040, 0, "NEGD", INH, HD6309_EXCLUSIVE }, + { 0x1043, 0, "COMD", INH, HD6309_EXCLUSIVE }, + { 0x1044, 0, "LSRD", INH, HD6309_EXCLUSIVE }, + { 0x1046, 0, "RORD", INH, HD6309_EXCLUSIVE }, + { 0x1047, 0, "ASRD", INH, HD6309_EXCLUSIVE }, + { 0x1048, 0, "ASLD", INH, HD6309_EXCLUSIVE }, + { 0x1049, 0, "ROLD", INH, HD6309_EXCLUSIVE }, + + { 0x104A, 0, "DECD", INH, HD6309_EXCLUSIVE }, + { 0x104C, 0, "INCD", INH, HD6309_EXCLUSIVE }, + { 0x104D, 0, "TSTD", INH, HD6309_EXCLUSIVE }, + { 0x104F, 0, "CLRD", INH, HD6309_EXCLUSIVE }, + + { 0x1053, 0, "COMW", INH, HD6309_EXCLUSIVE }, + { 0x1054, 0, "LSRW", INH, HD6309_EXCLUSIVE }, + { 0x1056, 0, "RORW", INH, HD6309_EXCLUSIVE }, + { 0x1059, 0, "ROLW", INH, HD6309_EXCLUSIVE }, + { 0x105A, 0, "DECW", INH, HD6309_EXCLUSIVE }, + { 0x105C, 0, "INCW", INH, HD6309_EXCLUSIVE }, + { 0x105D, 0, "TSTW", INH, HD6309_EXCLUSIVE }, + { 0x105F, 0, "CLRW", INH, HD6309_EXCLUSIVE }, + + { 0x1080, 2, "SUBW", IMM, HD6309_EXCLUSIVE }, + { 0x1081, 2, "CMPW", IMM, HD6309_EXCLUSIVE }, + { 0x1082, 2, "SBCD", IMM, HD6309_EXCLUSIVE }, + { 0x1083, 2, "CMPD", IMM, M6x09_GENERAL }, + { 0x1084, 2, "ANDD", IMM, HD6309_EXCLUSIVE }, + { 0x1085, 2, "BITD", IMM, HD6309_EXCLUSIVE }, + { 0x1086, 2, "LDW", IMM, HD6309_EXCLUSIVE }, + { 0x1087, 1, "XSTA", IMM, M6809_UNDOCUMENTED }, + { 0x1088, 2, "EORD", IMM, HD6309_EXCLUSIVE }, + { 0x1089, 2, "ADCD", IMM, HD6309_EXCLUSIVE }, + { 0x108A, 2, "ORD", IMM, HD6309_EXCLUSIVE }, + { 0x108B, 2, "ADDW", IMM, HD6309_EXCLUSIVE }, + { 0x108C, 2, "CMPY", IMM, M6x09_GENERAL }, + { 0x108E, 2, "LDY", IMM, M6x09_GENERAL }, + { 0x108F, 2, "XSTY", IMM, M6809_UNDOCUMENTED }, + + { 0x1090, 1, "SUBW", DIR, HD6309_EXCLUSIVE }, + { 0x1091, 1, "CMPW", DIR, HD6309_EXCLUSIVE }, + { 0x1092, 1, "SBCD", DIR, HD6309_EXCLUSIVE }, + { 0x1093, 1, "CMPD", DIR, M6x09_GENERAL }, + { 0x1094, 1, "ANDD", DIR, HD6309_EXCLUSIVE }, + { 0x1095, 1, "BITD", DIR, HD6309_EXCLUSIVE }, + { 0x1096, 1, "LDW", DIR, HD6309_EXCLUSIVE }, + { 0x1097, 1, "STW", DIR, HD6309_EXCLUSIVE }, + { 0x1098, 1, "EORD", DIR, HD6309_EXCLUSIVE }, + { 0x1099, 1, "ADCD", DIR, HD6309_EXCLUSIVE }, + { 0x109A, 1, "ORD", DIR, HD6309_EXCLUSIVE }, + { 0x109B, 1, "ADDW", DIR, HD6309_EXCLUSIVE }, + { 0x109C, 1, "CMPY", DIR, M6x09_GENERAL }, + { 0x109E, 1, "LDY", DIR, M6x09_GENERAL }, + { 0x109F, 1, "STY", DIR, M6x09_GENERAL }, + + { 0x10A0, 1, "SUBW", IND, HD6309_EXCLUSIVE }, + { 0x10A1, 1, "CMPW", IND, HD6309_EXCLUSIVE }, + { 0x10A2, 1, "SBCD", IND, HD6309_EXCLUSIVE }, + { 0x10A3, 1, "CMPD", IND, M6x09_GENERAL }, + { 0x10A4, 1, "ANDD", IND, HD6309_EXCLUSIVE }, + { 0x10A5, 1, "BITD", IND, HD6309_EXCLUSIVE }, + { 0x10A6, 1, "LDW", IND, HD6309_EXCLUSIVE }, + { 0x10A7, 1, "STW", IND, HD6309_EXCLUSIVE }, + { 0x10A8, 1, "EORD", IND, HD6309_EXCLUSIVE }, + { 0x10A9, 1, "ADCD", IND, HD6309_EXCLUSIVE }, + { 0x10AA, 1, "ORD", IND, HD6309_EXCLUSIVE }, + { 0x10AB, 1, "ADDW", IND, HD6309_EXCLUSIVE }, + { 0x10AC, 1, "CMPY", IND, M6x09_GENERAL }, + { 0x10AE, 1, "LDY", IND, M6x09_GENERAL }, + { 0x10AF, 1, "STY", IND, M6x09_GENERAL }, + + { 0x10B0, 2, "SUBW", EXT, HD6309_EXCLUSIVE }, + { 0x10B1, 2, "CMPW", EXT, HD6309_EXCLUSIVE }, + { 0x10B2, 2, "SBCD", EXT, HD6309_EXCLUSIVE }, + { 0x10B3, 2, "CMPD", EXT, M6x09_GENERAL }, + { 0x10B4, 2, "ANDD", EXT, HD6309_EXCLUSIVE }, + { 0x10B5, 2, "BITD", EXT, HD6309_EXCLUSIVE }, + { 0x10B6, 2, "LDW", EXT, HD6309_EXCLUSIVE }, + { 0x10B7, 2, "STW", EXT, HD6309_EXCLUSIVE }, + { 0x10B8, 2, "EORD", EXT, HD6309_EXCLUSIVE }, + { 0x10B9, 2, "ADCD", EXT, HD6309_EXCLUSIVE }, + { 0x10BA, 2, "ORD", EXT, HD6309_EXCLUSIVE }, + { 0x10BB, 2, "ADDW", EXT, HD6309_EXCLUSIVE }, + { 0x10BC, 2, "CMPY", EXT, M6x09_GENERAL }, + { 0x10BE, 2, "LDY", EXT, M6x09_GENERAL }, + { 0x10BF, 2, "STY", EXT, M6x09_GENERAL }, + + { 0x10C3, 2, "XADDD", IMM, M6809_UNDOCUMENTED }, + { 0x10C7, 1, "XSTB", IMM, M6809_UNDOCUMENTED }, + { 0x10CE, 2, "LDS", IMM, M6x09_GENERAL }, + { 0x10CF, 2, "XSTS", IMM, M6809_UNDOCUMENTED }, + + { 0x10D3, 1, "XADDD", DIR, M6809_UNDOCUMENTED }, + { 0x10DC, 1, "LDQ", DIR, HD6309_EXCLUSIVE }, + { 0x10DD, 1, "STQ", DIR, HD6309_EXCLUSIVE }, + { 0x10DE, 1, "LDS", DIR, M6x09_GENERAL }, + { 0x10DF, 1, "STS", DIR, M6x09_GENERAL }, + + { 0x10E3, 1, "XADDD", IND, M6809_UNDOCUMENTED }, + { 0x10EC, 1, "LDQ", IND, HD6309_EXCLUSIVE }, + { 0x10ED, 1, "STQ", IND, HD6309_EXCLUSIVE }, + { 0x10EE, 1, "LDS", IND, M6x09_GENERAL }, + { 0x10EF, 1, "STS", IND, M6x09_GENERAL }, + + { 0x10F3, 2, "XADDD", EXT, M6809_UNDOCUMENTED }, + { 0x10FC, 2, "LDQ", EXT, HD6309_EXCLUSIVE }, + { 0x10FD, 2, "STQ", EXT, HD6309_EXCLUSIVE }, + { 0x10FE, 2, "LDS", EXT, M6x09_GENERAL }, + { 0x10FF, 2, "STS", EXT, M6x09_GENERAL }, + + // Page 3 opcodes (0x11 0x..) + { 0x1110, 0, "PAGE2", PG2, M6x09_GENERAL }, + { 0x1111, 0, "PAGE3", PG3, M6x09_GENERAL }, + + { 0x1130, 2, "BAND", IMM_BW, HD6309_EXCLUSIVE }, + { 0x1131, 2, "BIAND", IMM_BW, HD6309_EXCLUSIVE }, + { 0x1132, 2, "BOR", IMM_BW, HD6309_EXCLUSIVE }, + { 0x1133, 2, "BIOR", IMM_BW, HD6309_EXCLUSIVE }, + { 0x1134, 2, "BEOR", IMM_BW, HD6309_EXCLUSIVE }, + { 0x1135, 2, "BIEOR", IMM_BW, HD6309_EXCLUSIVE }, + { 0x1136, 2, "LDBT", IMM_BW, HD6309_EXCLUSIVE }, + { 0x1137, 2, "STBT", IMM_BW, HD6309_EXCLUSIVE }, + { 0x1138, 1, "TFM", IMM_TFM, HD6309_EXCLUSIVE }, + { 0x1139, 1, "TFM", IMM_TFM, HD6309_EXCLUSIVE }, + { 0x113A, 1, "TFM", IMM_TFM, HD6309_EXCLUSIVE }, + { 0x113B, 1, "TFM", IMM_TFM, HD6309_EXCLUSIVE }, + { 0x113C, 1, "BITMD", IMM, HD6309_EXCLUSIVE }, + { 0x113D, 1, "LDMD", IMM, HD6309_EXCLUSIVE }, + { 0x113E, 0, "XFIRQ", INH, M6809_UNDOCUMENTED }, + { 0x113F, 0, "SWI3", INH, M6x09_GENERAL }, + + { 0x1143, 0, "COME", INH, HD6309_EXCLUSIVE }, + { 0x114A, 0, "DECE", INH, HD6309_EXCLUSIVE }, + { 0x114C, 0, "INCE", INH, HD6309_EXCLUSIVE }, + { 0x114D, 0, "TSTE", INH, HD6309_EXCLUSIVE }, + { 0x114F, 0, "CLRE", INH, HD6309_EXCLUSIVE }, + + { 0x1153, 0, "COMF", INH, HD6309_EXCLUSIVE }, + { 0x115A, 0, "DECF", INH, HD6309_EXCLUSIVE }, + { 0x115C, 0, "INCF", INH, HD6309_EXCLUSIVE }, + { 0x115D, 0, "TSTF", INH, HD6309_EXCLUSIVE }, + { 0x115F, 0, "CLRF", INH, HD6309_EXCLUSIVE }, + + { 0x1180, 1, "SUBE", IMM, HD6309_EXCLUSIVE }, + { 0x1181, 1, "CMPE", IMM, HD6309_EXCLUSIVE }, + { 0x1183, 2, "CMPU", IMM, M6x09_GENERAL }, + { 0x1186, 1, "LDE", IMM, HD6309_EXCLUSIVE }, + { 0x1187, 1, "XSTA", IMM, M6809_UNDOCUMENTED }, + { 0x118B, 1, "ADDE", IMM, HD6309_EXCLUSIVE }, + { 0x118C, 2, "CMPS", IMM, M6x09_GENERAL }, + { 0x118D, 1, "DIVD", IMM, HD6309_EXCLUSIVE }, + { 0x118E, 2, "DIVQ", IMM, HD6309_EXCLUSIVE }, + { 0x118F, 2, "MULD", IMM, HD6309_EXCLUSIVE }, + { 0x118F, 2, "XSTX", IMM, M6809_UNDOCUMENTED }, + + { 0x1190, 1, "SUBE", DIR, HD6309_EXCLUSIVE }, + { 0x1191, 1, "CMPE", DIR, HD6309_EXCLUSIVE }, + { 0x1193, 1, "CMPU", DIR, M6x09_GENERAL }, + { 0x1196, 1, "LDE", DIR, HD6309_EXCLUSIVE }, + { 0x1197, 1, "STE", DIR, HD6309_EXCLUSIVE }, + { 0x119B, 1, "ADDE", DIR, HD6309_EXCLUSIVE }, + { 0x119C, 1, "CMPS", DIR, M6x09_GENERAL }, + { 0x119D, 1, "DIVD", DIR, HD6309_EXCLUSIVE }, + { 0x119E, 1, "DIVQ", DIR, HD6309_EXCLUSIVE }, + { 0x119F, 1, "MULD", DIR, HD6309_EXCLUSIVE }, + + { 0x11A0, 1, "SUBE", IND, HD6309_EXCLUSIVE }, + { 0x11A1, 1, "CMPE", IND, HD6309_EXCLUSIVE }, + { 0x11A3, 1, "CMPU", IND, M6x09_GENERAL }, + { 0x11A6, 1, "LDE", IND, HD6309_EXCLUSIVE }, + { 0x11A7, 1, "STE", IND, HD6309_EXCLUSIVE }, + { 0x11AB, 1, "ADDE", IND, HD6309_EXCLUSIVE }, + { 0x11AC, 1, "CMPS", IND, M6x09_GENERAL }, + { 0x11AD, 1, "DIVD", IND, HD6309_EXCLUSIVE }, + { 0x11AE, 1, "DIVQ", IND, HD6309_EXCLUSIVE }, + { 0x11AF, 1, "MULD", IND, HD6309_EXCLUSIVE }, + + { 0x11B0, 2, "SUBE", EXT, HD6309_EXCLUSIVE }, + { 0x11B1, 2, "CMPE", EXT, HD6309_EXCLUSIVE }, + { 0x11B3, 2, "CMPU", EXT, M6x09_GENERAL }, + { 0x11B6, 2, "LDE", EXT, HD6309_EXCLUSIVE }, + { 0x11B7, 2, "STE", EXT, HD6309_EXCLUSIVE }, + { 0x11BB, 2, "ADDE", EXT, HD6309_EXCLUSIVE }, + { 0x11BC, 2, "CMPS", EXT, M6x09_GENERAL }, + { 0x11BD, 2, "DIVD", EXT, HD6309_EXCLUSIVE }, + { 0x11BE, 2, "DIVQ", EXT, HD6309_EXCLUSIVE }, + { 0x11BF, 2, "MULD", EXT, HD6309_EXCLUSIVE }, + + { 0x11C0, 1, "SUBF", IMM, HD6309_EXCLUSIVE }, + { 0x11C1, 1, "CMPF", IMM, HD6309_EXCLUSIVE }, + { 0x11C3, 2, "XADDU", IMM, M6809_UNDOCUMENTED }, + { 0x11C6, 1, "LDF", IMM, HD6309_EXCLUSIVE }, + { 0x11C7, 1, "XSTB", IMM, M6809_UNDOCUMENTED }, + { 0x11CB, 1, "ADDF", IMM, HD6309_EXCLUSIVE }, + { 0x11CF, 2, "XSTU", IMM, M6809_UNDOCUMENTED }, + + { 0x11D0, 1, "SUBF", DIR, HD6309_EXCLUSIVE }, + { 0x11D1, 1, "CMPF", DIR, HD6309_EXCLUSIVE }, + { 0x11D3, 1, "XADDU", DIR, M6809_UNDOCUMENTED }, + { 0x11D6, 1, "LDF", DIR, HD6309_EXCLUSIVE }, + { 0x11D7, 1, "STF", DIR, HD6309_EXCLUSIVE }, + { 0x11DB, 1, "ADDF", DIR, HD6309_EXCLUSIVE }, + + { 0x11E0, 1, "SUBF", IND, HD6309_EXCLUSIVE }, + { 0x11E1, 1, "CMPF", IND, HD6309_EXCLUSIVE }, + { 0x11E3, 1, "XADDU", IND, M6809_UNDOCUMENTED }, + { 0x11E6, 1, "LDF", IND, HD6309_EXCLUSIVE }, + { 0x11E7, 1, "STF", IND, HD6309_EXCLUSIVE }, + { 0x11EB, 1, "ADDF", IND, HD6309_EXCLUSIVE }, + + { 0x11F0, 2, "SUBF", EXT, HD6309_EXCLUSIVE }, + { 0x11F1, 2, "CMPF", EXT, HD6309_EXCLUSIVE }, + { 0x11F3, 2, "XADDU", EXT, M6809_UNDOCUMENTED }, + { 0x11F6, 2, "LDF", EXT, HD6309_EXCLUSIVE }, + { 0x11F7, 2, "STF", EXT, HD6309_EXCLUSIVE }, + { 0x11FB, 2, "ADDF", EXT, HD6309_EXCLUSIVE } }; // ======================> m6x09_disassembler -m6x09_disassembler::m6x09_disassembler(m6x09_instruction_level level, const char teregs[16][4]) +m6x09_disassembler::m6x09_disassembler(uint32_t level, const char teregs[16][4]) : m6x09_base_disassembler(m6x09_opcodes, std::size(m6x09_opcodes), level) , m_teregs(*reinterpret_cast, 16> *>(teregs)) { @@ -999,7 +1083,7 @@ const char m6809_disassembler::m6809_teregs[16][4] = }; -m6809_disassembler::m6809_disassembler() : m6x09_disassembler(M6x09_GENERAL, m6809_teregs) +m6809_disassembler::m6809_disassembler() : m6x09_disassembler(M6x09_GENERAL|M6809_UNDOCUMENTED, m6809_teregs) { } @@ -1014,7 +1098,7 @@ const char hd6309_disassembler::hd6309_teregs[16][4] = "A", "B", "CC", "DP", "0", "0", "E", "F" }; -hd6309_disassembler::hd6309_disassembler() : m6x09_disassembler(HD6309_EXCLUSIVE, hd6309_teregs) +hd6309_disassembler::hd6309_disassembler() : m6x09_disassembler(M6x09_GENERAL|HD6309_EXCLUSIVE, hd6309_teregs) { } @@ -1025,216 +1109,216 @@ hd6309_disassembler::hd6309_disassembler() : m6x09_disassembler(HD6309_EXCLUSIVE const m6x09_base_disassembler::opcodeinfo konami_disassembler::konami_opcodes[] = { - { 0x08, 2, "LEAX", IND, M6x09_GENERAL }, - { 0x09, 2, "LEAY", IND, M6x09_GENERAL }, - { 0x0A, 2, "LEAU", IND, M6x09_GENERAL }, - { 0x0B, 2, "LEAS", IND, M6x09_GENERAL }, - { 0x0C, 2, "PUSHS", PSHS, M6x09_GENERAL }, - { 0x0D, 2, "PUSHU", PSHU, M6x09_GENERAL }, - { 0x0E, 2, "PULLS", PULS, M6x09_GENERAL }, - { 0x0F, 2, "PULLU", PULU, M6x09_GENERAL }, - - { 0x10, 2, "LDA", IMM, M6x09_GENERAL }, - { 0x11, 2, "LDB", IMM, M6x09_GENERAL }, - { 0x12, 2, "LDA", IND, M6x09_GENERAL }, - { 0x13, 2, "LDB", IND, M6x09_GENERAL }, - { 0x14, 2, "ADDA", IMM, M6x09_GENERAL }, - { 0x15, 2, "ADDB", IMM, M6x09_GENERAL }, - { 0x16, 2, "ADDA", IND, M6x09_GENERAL }, - { 0x17, 2, "ADDB", IND, M6x09_GENERAL }, - { 0x18, 2, "ADCA", IMM, M6x09_GENERAL }, - { 0x19, 2, "ADCB", IMM, M6x09_GENERAL }, - { 0x1A, 2, "ADCA", IND, M6x09_GENERAL }, - { 0x1B, 2, "ADCB", IND, M6x09_GENERAL }, - { 0x1C, 2, "SUBA", IMM, M6x09_GENERAL }, - { 0x1D, 2, "SUBB", IMM, M6x09_GENERAL }, - { 0x1E, 2, "SUBA", IND, M6x09_GENERAL }, - { 0x1F, 2, "SUBB", IND, M6x09_GENERAL }, - - { 0x20, 2, "SBCA", IMM, M6x09_GENERAL }, - { 0x21, 2, "SBCB", IMM, M6x09_GENERAL }, - { 0x22, 2, "SBCA", IND, M6x09_GENERAL }, - { 0x23, 2, "SBCB", IND, M6x09_GENERAL }, - { 0x24, 2, "ANDA", IMM, M6x09_GENERAL }, - { 0x25, 2, "ANDB", IMM, M6x09_GENERAL }, - { 0x26, 2, "ANDA", IND, M6x09_GENERAL }, - { 0x27, 2, "ANDB", IND, M6x09_GENERAL }, - { 0x28, 2, "BITA", IMM, M6x09_GENERAL }, - { 0x29, 2, "BITB", IMM, M6x09_GENERAL }, - { 0x2A, 2, "BITA", IND, M6x09_GENERAL }, - { 0x2B, 2, "BITB", IND, M6x09_GENERAL }, - { 0x2C, 2, "EORA", IMM, M6x09_GENERAL }, - { 0x2D, 2, "EORB", IMM, M6x09_GENERAL }, - { 0x2E, 2, "EORA", IND, M6x09_GENERAL }, - { 0x2F, 2, "EORB", IND, M6x09_GENERAL }, - - { 0x30, 2, "ORA", IMM, M6x09_GENERAL }, - { 0x31, 2, "ORB", IMM, M6x09_GENERAL }, - { 0x32, 2, "ORA", IND, M6x09_GENERAL }, - { 0x33, 2, "ORB", IND, M6x09_GENERAL }, - { 0x34, 2, "CMPA", IMM, M6x09_GENERAL }, - { 0x35, 2, "CMPB", IMM, M6x09_GENERAL }, - { 0x36, 2, "CMPA", IND, M6x09_GENERAL }, - { 0x37, 2, "CMPB", IND, M6x09_GENERAL }, - { 0x38, 2, "SETLINES", IMM, M6x09_GENERAL }, - { 0x39, 2, "SETLINES", IND, M6x09_GENERAL }, - { 0x3A, 2, "STA", IND, M6x09_GENERAL }, - { 0x3B, 2, "STB", IND, M6x09_GENERAL }, - { 0x3C, 2, "ANDCC", IMM, M6x09_GENERAL }, - { 0x3D, 2, "ORCC", IMM, M6x09_GENERAL }, - { 0x3E, 2, "EXG", IMM_RR, M6x09_GENERAL }, - { 0x3F, 2, "TFR", IMM_RR, M6x09_GENERAL }, - - { 0x40, 3, "LDD", IMM, M6x09_GENERAL }, - { 0x41, 2, "LDD", IND, M6x09_GENERAL }, - { 0x42, 3, "LDX", IMM, M6x09_GENERAL }, - { 0x43, 2, "LDX", IND, M6x09_GENERAL }, - { 0x44, 3, "LDY", IMM, M6x09_GENERAL }, - { 0x45, 2, "LDY", IND, M6x09_GENERAL }, - { 0x46, 3, "LDU", IMM, M6x09_GENERAL }, - { 0x47, 2, "LDU", IND, M6x09_GENERAL }, - { 0x48, 3, "LDS", IMM, M6x09_GENERAL }, - { 0x49, 2, "LDS", IND, M6x09_GENERAL }, - { 0x4A, 3, "CMPD", IMM, M6x09_GENERAL }, - { 0x4B, 2, "CMPD", IND, M6x09_GENERAL }, - { 0x4C, 3, "CMPX", IMM, M6x09_GENERAL }, - { 0x4D, 2, "CMPX", IND, M6x09_GENERAL }, - { 0x4E, 3, "CMPY", IMM, M6x09_GENERAL }, - { 0x4F, 2, "CMPY", IND, M6x09_GENERAL }, - - { 0x50, 3, "CMPU", IMM, M6x09_GENERAL }, - { 0x51, 2, "CMPU", IND, M6x09_GENERAL }, - { 0x52, 3, "CMPS", IMM, M6x09_GENERAL }, - { 0x53, 2, "CMPS", IND, M6x09_GENERAL }, - { 0x54, 3, "ADDD", IMM, M6x09_GENERAL }, - { 0x55, 2, "ADDD", IND, M6x09_GENERAL }, - { 0x56, 3, "SUBD", IMM, M6x09_GENERAL }, - { 0x57, 2, "SUBD", IND, M6x09_GENERAL }, - { 0x58, 2, "STD", IND, M6x09_GENERAL }, - { 0x59, 2, "STX", IND, M6x09_GENERAL }, - { 0x5A, 2, "STY", IND, M6x09_GENERAL }, - { 0x5B, 2, "STU", IND, M6x09_GENERAL }, - { 0x5C, 2, "STS", IND, M6x09_GENERAL }, - - { 0x60, 2, "BRA", REL, M6x09_GENERAL }, - { 0x61, 2, "BHI", REL, M6x09_GENERAL, STEP_COND }, - { 0x62, 2, "BCC", REL, M6x09_GENERAL, STEP_COND }, - { 0x63, 2, "BNE", REL, M6x09_GENERAL, STEP_COND }, - { 0x64, 2, "BVC", REL, M6x09_GENERAL, STEP_COND }, - { 0x65, 2, "BPL", REL, M6x09_GENERAL, STEP_COND }, - { 0x66, 2, "BGE", REL, M6x09_GENERAL, STEP_COND }, - { 0x67, 2, "BGT", REL, M6x09_GENERAL, STEP_COND }, - { 0x68, 3, "LBRA", LREL, M6x09_GENERAL }, - { 0x69, 3, "LBHI", LREL, M6x09_GENERAL, STEP_COND }, - { 0x6A, 3, "LBCC", LREL, M6x09_GENERAL, STEP_COND }, - { 0x6B, 3, "LBNE", LREL, M6x09_GENERAL, STEP_COND }, - { 0x6C, 3, "LBVC", LREL, M6x09_GENERAL, STEP_COND }, - { 0x6D, 3, "LBPL", LREL, M6x09_GENERAL, STEP_COND }, - { 0x6E, 3, "LBGE", LREL, M6x09_GENERAL, STEP_COND }, - { 0x6F, 3, "LBGT", LREL, M6x09_GENERAL, STEP_COND }, - - { 0x70, 2, "BRN", REL, M6x09_GENERAL }, - { 0x71, 2, "BLS", REL, M6x09_GENERAL, STEP_COND }, - { 0x72, 2, "BCS", REL, M6x09_GENERAL, STEP_COND }, - { 0x73, 2, "BEQ", REL, M6x09_GENERAL, STEP_COND }, - { 0x74, 2, "BVS", REL, M6x09_GENERAL, STEP_COND }, - { 0x75, 2, "BMI", REL, M6x09_GENERAL, STEP_COND }, - { 0x76, 2, "BLT", REL, M6x09_GENERAL, STEP_COND }, - { 0x77, 2, "BLE", REL, M6x09_GENERAL, STEP_COND }, - { 0x78, 3, "LBRN", LREL, M6x09_GENERAL }, - { 0x79, 3, "LBLS", LREL, M6x09_GENERAL, STEP_COND }, - { 0x7A, 3, "LBCS", LREL, M6x09_GENERAL, STEP_COND }, - { 0x7B, 3, "LBEQ", LREL, M6x09_GENERAL, STEP_COND }, - { 0x7C, 3, "LBVS", LREL, M6x09_GENERAL, STEP_COND }, - { 0x7D, 3, "LBMI", LREL, M6x09_GENERAL, STEP_COND }, - { 0x7E, 3, "LBLT", LREL, M6x09_GENERAL, STEP_COND }, - { 0x7F, 3, "LBLE", LREL, M6x09_GENERAL, STEP_COND }, - - { 0x80, 1, "CLRA", INH, M6x09_GENERAL }, - { 0x81, 1, "CLRB", INH, M6x09_GENERAL }, - { 0x82, 2, "CLR", IND, M6x09_GENERAL }, - { 0x83, 1, "COMA", INH, M6x09_GENERAL }, - { 0x84, 1, "COMB", INH, M6x09_GENERAL }, - { 0x85, 2, "COM", IND, M6x09_GENERAL }, - { 0x86, 1, "NEGA", INH, M6x09_GENERAL }, - { 0x87, 1, "NEGB", INH, M6x09_GENERAL }, - { 0x88, 2, "NEG", IND, M6x09_GENERAL }, - { 0x89, 1, "INCA", INH, M6x09_GENERAL }, - { 0x8A, 1, "INCB", INH, M6x09_GENERAL }, - { 0x8B, 2, "INC", IND, M6x09_GENERAL }, - { 0x8C, 1, "DECA", INH, M6x09_GENERAL }, - { 0x8D, 1, "DECB", INH, M6x09_GENERAL }, - { 0x8E, 2, "DEC", IND, M6x09_GENERAL }, - { 0x8F, 1, "RTS", INH , M6x09_GENERAL, STEP_OUT }, - - { 0x90, 1, "TSTA", INH, M6x09_GENERAL }, - { 0x91, 1, "TSTB", INH, M6x09_GENERAL }, - { 0x92, 2, "TST", IND, M6x09_GENERAL }, - { 0x93, 1, "LSRA", INH, M6x09_GENERAL }, - { 0x94, 1, "LSRB", INH, M6x09_GENERAL }, - { 0x95, 2, "LSR", IND, M6x09_GENERAL }, - { 0x96, 1, "RORA", INH, M6x09_GENERAL }, - { 0x97, 1, "RORB", INH, M6x09_GENERAL }, - { 0x98, 2, "ROR", IND, M6x09_GENERAL }, - { 0x99, 1, "ASRA", INH, M6x09_GENERAL }, - { 0x9A, 1, "ASRB", INH, M6x09_GENERAL }, - { 0x9B, 2, "ASR", IND, M6x09_GENERAL }, - { 0x9C, 1, "ASLA", INH, M6x09_GENERAL }, - { 0x9D, 1, "ASLB", INH, M6x09_GENERAL }, - { 0x9E, 2, "ASL", IND, M6x09_GENERAL }, - { 0x9F, 1, "RTI", INH , M6x09_GENERAL, STEP_OUT }, - - { 0xA0, 1, "ROLA", INH, M6x09_GENERAL }, - { 0xA1, 1, "ROLB", INH, M6x09_GENERAL }, - { 0xA2, 2, "ROL", IND, M6x09_GENERAL }, - { 0xA3, 2, "LSRW", IND, M6x09_GENERAL }, - { 0xA4, 2, "RORW", IND, M6x09_GENERAL }, - { 0xA5, 2, "ASRW", IND, M6x09_GENERAL }, - { 0xA6, 2, "ASLW", IND, M6x09_GENERAL }, - { 0xA7, 2, "ROLW", IND, M6x09_GENERAL }, - { 0xA8, 2, "JMP", IND, M6x09_GENERAL }, - { 0xA9, 2, "JSR", IND, M6x09_GENERAL, STEP_OVER }, - { 0xAA, 2, "BSR", REL, M6x09_GENERAL, STEP_OVER }, - { 0xAB, 3, "LBSR", LREL, M6x09_GENERAL, STEP_OVER }, - { 0xAC, 2, "DECB,JNZ", REL, M6x09_GENERAL }, - { 0xAD, 2, "DECX,JNZ", REL, M6x09_GENERAL }, - { 0xAE, 1, "NOP", INH, M6x09_GENERAL }, - - { 0xB0, 1, "ABX", INH, M6x09_GENERAL }, - { 0xB1, 1, "DAA", INH, M6x09_GENERAL }, - { 0xB2, 1, "SEX", INH, M6x09_GENERAL }, - { 0xB3, 1, "MUL", INH, M6x09_GENERAL }, - { 0xB4, 1, "LMUL", INH, M6x09_GENERAL }, - { 0xB5, 1, "DIV X,B", INH, M6x09_GENERAL }, - { 0xB6, 1, "BMOVE Y,X,U", INH , M6x09_GENERAL }, - { 0xB7, 1, "MOVE Y,X,U", INH , M6x09_GENERAL }, - { 0xB8, 2, "LSRD", IMM, M6x09_GENERAL }, - { 0xB9, 2, "LSRD", IND, M6x09_GENERAL }, - { 0xBA, 2, "RORD", IMM, M6x09_GENERAL }, - { 0xBB, 2, "RORD", IND, M6x09_GENERAL }, - { 0xBC, 2, "ASRD", IMM, M6x09_GENERAL }, - { 0xBD, 2, "ASRD", IND, M6x09_GENERAL }, - { 0xBE, 2, "ASLD", IMM, M6x09_GENERAL }, - { 0xBF, 2, "ASLD", IND, M6x09_GENERAL }, - - { 0xC0, 2, "ROLD", IMM, M6x09_GENERAL }, - { 0xC1, 2, "ROLD", IND, M6x09_GENERAL }, - { 0xC2, 1, "CLRD", INH, M6x09_GENERAL }, - { 0xC3, 2, "CLRW", IND, M6x09_GENERAL }, - { 0xC4, 1, "NEGD", INH, M6x09_GENERAL }, - { 0xC5, 2, "NEGW", IND, M6x09_GENERAL }, - { 0xC6, 1, "INCD", INH, M6x09_GENERAL }, - { 0xC7, 2, "INCW", IND, M6x09_GENERAL }, - { 0xC8, 1, "DECD", INH, M6x09_GENERAL }, - { 0xC9, 2, "DECW", IND, M6x09_GENERAL }, - { 0xCA, 1, "TSTD", INH, M6x09_GENERAL }, - { 0xCB, 2, "TSTW", IND, M6x09_GENERAL }, - { 0xCC, 1, "ABSA", INH, M6x09_GENERAL }, - { 0xCD, 1, "ABSB", INH, M6x09_GENERAL }, - { 0xCE, 1, "ABSD", INH, M6x09_GENERAL }, - { 0xCF, 1, "BSET A,X,U", INH, M6x09_GENERAL }, - - { 0xD0, 1, "BSET D,X,U", INH, M6x09_GENERAL } + { 0x08, 1, "LEAX", IND, M6x09_GENERAL }, + { 0x09, 1, "LEAY", IND, M6x09_GENERAL }, + { 0x0A, 1, "LEAU", IND, M6x09_GENERAL }, + { 0x0B, 1, "LEAS", IND, M6x09_GENERAL }, + { 0x0C, 1, "PUSHS", PSHS, M6x09_GENERAL }, + { 0x0D, 1, "PUSHU", PSHU, M6x09_GENERAL }, + { 0x0E, 1, "PULLS", PULS, M6x09_GENERAL }, + { 0x0F, 1, "PULLU", PULU, M6x09_GENERAL }, + + { 0x10, 1, "LDA", IMM, M6x09_GENERAL }, + { 0x11, 1, "LDB", IMM, M6x09_GENERAL }, + { 0x12, 1, "LDA", IND, M6x09_GENERAL }, + { 0x13, 1, "LDB", IND, M6x09_GENERAL }, + { 0x14, 1, "ADDA", IMM, M6x09_GENERAL }, + { 0x15, 1, "ADDB", IMM, M6x09_GENERAL }, + { 0x16, 1, "ADDA", IND, M6x09_GENERAL }, + { 0x17, 1, "ADDB", IND, M6x09_GENERAL }, + { 0x18, 1, "ADCA", IMM, M6x09_GENERAL }, + { 0x19, 1, "ADCB", IMM, M6x09_GENERAL }, + { 0x1A, 1, "ADCA", IND, M6x09_GENERAL }, + { 0x1B, 1, "ADCB", IND, M6x09_GENERAL }, + { 0x1C, 1, "SUBA", IMM, M6x09_GENERAL }, + { 0x1D, 1, "SUBB", IMM, M6x09_GENERAL }, + { 0x1E, 1, "SUBA", IND, M6x09_GENERAL }, + { 0x1F, 1, "SUBB", IND, M6x09_GENERAL }, + + { 0x20, 1, "SBCA", IMM, M6x09_GENERAL }, + { 0x21, 1, "SBCB", IMM, M6x09_GENERAL }, + { 0x22, 1, "SBCA", IND, M6x09_GENERAL }, + { 0x23, 1, "SBCB", IND, M6x09_GENERAL }, + { 0x24, 1, "ANDA", IMM, M6x09_GENERAL }, + { 0x25, 1, "ANDB", IMM, M6x09_GENERAL }, + { 0x26, 1, "ANDA", IND, M6x09_GENERAL }, + { 0x27, 1, "ANDB", IND, M6x09_GENERAL }, + { 0x28, 1, "BITA", IMM, M6x09_GENERAL }, + { 0x29, 1, "BITB", IMM, M6x09_GENERAL }, + { 0x2A, 1, "BITA", IND, M6x09_GENERAL }, + { 0x2B, 1, "BITB", IND, M6x09_GENERAL }, + { 0x2C, 1, "EORA", IMM, M6x09_GENERAL }, + { 0x2D, 1, "EORB", IMM, M6x09_GENERAL }, + { 0x2E, 1, "EORA", IND, M6x09_GENERAL }, + { 0x2F, 1, "EORB", IND, M6x09_GENERAL }, + + { 0x30, 1, "ORA", IMM, M6x09_GENERAL }, + { 0x31, 1, "ORB", IMM, M6x09_GENERAL }, + { 0x32, 1, "ORA", IND, M6x09_GENERAL }, + { 0x33, 1, "ORB", IND, M6x09_GENERAL }, + { 0x34, 1, "CMPA", IMM, M6x09_GENERAL }, + { 0x35, 1, "CMPB", IMM, M6x09_GENERAL }, + { 0x36, 1, "CMPA", IND, M6x09_GENERAL }, + { 0x37, 1, "CMPB", IND, M6x09_GENERAL }, + { 0x38, 1, "SETLINES", IMM, M6x09_GENERAL }, + { 0x39, 1, "SETLINES", IND, M6x09_GENERAL }, + { 0x3A, 1, "STA", IND, M6x09_GENERAL }, + { 0x3B, 1, "STB", IND, M6x09_GENERAL }, + { 0x3C, 1, "ANDCC", IMM, M6x09_GENERAL }, + { 0x3D, 1, "ORCC", IMM, M6x09_GENERAL }, + { 0x3E, 1, "EXG", IMM_RR, M6x09_GENERAL }, + { 0x3F, 1, "TFR", IMM_RR, M6x09_GENERAL }, + + { 0x40, 2, "LDD", IMM, M6x09_GENERAL }, + { 0x41, 1, "LDD", IND, M6x09_GENERAL }, + { 0x42, 2, "LDX", IMM, M6x09_GENERAL }, + { 0x43, 1, "LDX", IND, M6x09_GENERAL }, + { 0x44, 2, "LDY", IMM, M6x09_GENERAL }, + { 0x45, 1, "LDY", IND, M6x09_GENERAL }, + { 0x46, 2, "LDU", IMM, M6x09_GENERAL }, + { 0x47, 1, "LDU", IND, M6x09_GENERAL }, + { 0x48, 2, "LDS", IMM, M6x09_GENERAL }, + { 0x49, 1, "LDS", IND, M6x09_GENERAL }, + { 0x4A, 2, "CMPD", IMM, M6x09_GENERAL }, + { 0x4B, 1, "CMPD", IND, M6x09_GENERAL }, + { 0x4C, 2, "CMPX", IMM, M6x09_GENERAL }, + { 0x4D, 1, "CMPX", IND, M6x09_GENERAL }, + { 0x4E, 2, "CMPY", IMM, M6x09_GENERAL }, + { 0x4F, 1, "CMPY", IND, M6x09_GENERAL }, + + { 0x50, 2, "CMPU", IMM, M6x09_GENERAL }, + { 0x51, 1, "CMPU", IND, M6x09_GENERAL }, + { 0x52, 2, "CMPS", IMM, M6x09_GENERAL }, + { 0x53, 1, "CMPS", IND, M6x09_GENERAL }, + { 0x54, 2, "ADDD", IMM, M6x09_GENERAL }, + { 0x55, 1, "ADDD", IND, M6x09_GENERAL }, + { 0x56, 2, "SUBD", IMM, M6x09_GENERAL }, + { 0x57, 1, "SUBD", IND, M6x09_GENERAL }, + { 0x58, 1, "STD", IND, M6x09_GENERAL }, + { 0x59, 1, "STX", IND, M6x09_GENERAL }, + { 0x5A, 1, "STY", IND, M6x09_GENERAL }, + { 0x5B, 1, "STU", IND, M6x09_GENERAL }, + { 0x5C, 1, "STS", IND, M6x09_GENERAL }, + + { 0x60, 1, "BRA", REL, M6x09_GENERAL }, + { 0x61, 1, "BHI", REL, M6x09_GENERAL, STEP_COND }, + { 0x62, 1, "BCC", REL, M6x09_GENERAL, STEP_COND }, + { 0x63, 1, "BNE", REL, M6x09_GENERAL, STEP_COND }, + { 0x64, 1, "BVC", REL, M6x09_GENERAL, STEP_COND }, + { 0x65, 1, "BPL", REL, M6x09_GENERAL, STEP_COND }, + { 0x66, 1, "BGE", REL, M6x09_GENERAL, STEP_COND }, + { 0x67, 1, "BGT", REL, M6x09_GENERAL, STEP_COND }, + { 0x68, 2, "LBRA", LREL, M6x09_GENERAL }, + { 0x69, 2, "LBHI", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6A, 2, "LBCC", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6B, 2, "LBNE", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6C, 2, "LBVC", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6D, 2, "LBPL", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6E, 2, "LBGE", LREL, M6x09_GENERAL, STEP_COND }, + { 0x6F, 2, "LBGT", LREL, M6x09_GENERAL, STEP_COND }, + + { 0x70, 1, "BRN", REL, M6x09_GENERAL }, + { 0x71, 1, "BLS", REL, M6x09_GENERAL, STEP_COND }, + { 0x72, 1, "BCS", REL, M6x09_GENERAL, STEP_COND }, + { 0x73, 1, "BEQ", REL, M6x09_GENERAL, STEP_COND }, + { 0x74, 1, "BVS", REL, M6x09_GENERAL, STEP_COND }, + { 0x75, 1, "BMI", REL, M6x09_GENERAL, STEP_COND }, + { 0x76, 1, "BLT", REL, M6x09_GENERAL, STEP_COND }, + { 0x77, 1, "BLE", REL, M6x09_GENERAL, STEP_COND }, + { 0x78, 2, "LBRN", LREL, M6x09_GENERAL }, + { 0x79, 2, "LBLS", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7A, 2, "LBCS", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7B, 2, "LBEQ", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7C, 2, "LBVS", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7D, 2, "LBMI", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7E, 2, "LBLT", LREL, M6x09_GENERAL, STEP_COND }, + { 0x7F, 2, "LBLE", LREL, M6x09_GENERAL, STEP_COND }, + + { 0x80, 0, "CLRA", INH, M6x09_GENERAL }, + { 0x81, 0, "CLRB", INH, M6x09_GENERAL }, + { 0x82, 1, "CLR", IND, M6x09_GENERAL }, + { 0x83, 0, "COMA", INH, M6x09_GENERAL }, + { 0x84, 0, "COMB", INH, M6x09_GENERAL }, + { 0x85, 1, "COM", IND, M6x09_GENERAL }, + { 0x86, 0, "NEGA", INH, M6x09_GENERAL }, + { 0x87, 0, "NEGB", INH, M6x09_GENERAL }, + { 0x88, 1, "NEG", IND, M6x09_GENERAL }, + { 0x89, 0, "INCA", INH, M6x09_GENERAL }, + { 0x8A, 0, "INCB", INH, M6x09_GENERAL }, + { 0x8B, 1, "INC", IND, M6x09_GENERAL }, + { 0x8C, 0, "DECA", INH, M6x09_GENERAL }, + { 0x8D, 0, "DECB", INH, M6x09_GENERAL }, + { 0x8E, 1, "DEC", IND, M6x09_GENERAL }, + { 0x8F, 0, "RTS", INH , M6x09_GENERAL, STEP_OUT }, + + { 0x90, 0, "TSTA", INH, M6x09_GENERAL }, + { 0x91, 0, "TSTB", INH, M6x09_GENERAL }, + { 0x92, 1, "TST", IND, M6x09_GENERAL }, + { 0x93, 0, "LSRA", INH, M6x09_GENERAL }, + { 0x94, 0, "LSRB", INH, M6x09_GENERAL }, + { 0x95, 1, "LSR", IND, M6x09_GENERAL }, + { 0x96, 0, "RORA", INH, M6x09_GENERAL }, + { 0x97, 0, "RORB", INH, M6x09_GENERAL }, + { 0x98, 1, "ROR", IND, M6x09_GENERAL }, + { 0x99, 0, "ASRA", INH, M6x09_GENERAL }, + { 0x9A, 0, "ASRB", INH, M6x09_GENERAL }, + { 0x9B, 1, "ASR", IND, M6x09_GENERAL }, + { 0x9C, 0, "ASLA", INH, M6x09_GENERAL }, + { 0x9D, 0, "ASLB", INH, M6x09_GENERAL }, + { 0x9E, 1, "ASL", IND, M6x09_GENERAL }, + { 0x9F, 0, "RTI", INH , M6x09_GENERAL, STEP_OUT }, + + { 0xA0, 0, "ROLA", INH, M6x09_GENERAL }, + { 0xA1, 0, "ROLB", INH, M6x09_GENERAL }, + { 0xA2, 1, "ROL", IND, M6x09_GENERAL }, + { 0xA3, 1, "LSRW", IND, M6x09_GENERAL }, + { 0xA4, 1, "RORW", IND, M6x09_GENERAL }, + { 0xA5, 1, "ASRW", IND, M6x09_GENERAL }, + { 0xA6, 1, "ASLW", IND, M6x09_GENERAL }, + { 0xA7, 1, "ROLW", IND, M6x09_GENERAL }, + { 0xA8, 1, "JMP", IND, M6x09_GENERAL }, + { 0xA9, 1, "JSR", IND, M6x09_GENERAL, STEP_OVER }, + { 0xAA, 1, "BSR", REL, M6x09_GENERAL, STEP_OVER }, + { 0xAB, 2, "LBSR", LREL, M6x09_GENERAL, STEP_OVER }, + { 0xAC, 1, "DECB,JNZ", REL, M6x09_GENERAL }, + { 0xAD, 1, "DECX,JNZ", REL, M6x09_GENERAL }, + { 0xAE, 0, "NOP", INH, M6x09_GENERAL }, + + { 0xB0, 0, "ABX", INH, M6x09_GENERAL }, + { 0xB1, 0, "DAA", INH, M6x09_GENERAL }, + { 0xB2, 0, "SEX", INH, M6x09_GENERAL }, + { 0xB3, 0, "MUL", INH, M6x09_GENERAL }, + { 0xB4, 0, "LMUL", INH, M6x09_GENERAL }, + { 0xB5, 0, "DIV X,B", INH, M6x09_GENERAL }, + { 0xB6, 0, "BMOVE Y,X,U", INH, M6x09_GENERAL }, + { 0xB7, 0, "MOVE Y,X,U", INH, M6x09_GENERAL }, + { 0xB8, 1, "LSRD", IMM, M6x09_GENERAL }, + { 0xB9, 1, "LSRD", IND, M6x09_GENERAL }, + { 0xBA, 1, "RORD", IMM, M6x09_GENERAL }, + { 0xBB, 1, "RORD", IND, M6x09_GENERAL }, + { 0xBC, 1, "ASRD", IMM, M6x09_GENERAL }, + { 0xBD, 1, "ASRD", IND, M6x09_GENERAL }, + { 0xBE, 1, "ASLD", IMM, M6x09_GENERAL }, + { 0xBF, 1, "ASLD", IND, M6x09_GENERAL }, + + { 0xC0, 1, "ROLD", IMM, M6x09_GENERAL }, + { 0xC1, 1, "ROLD", IND, M6x09_GENERAL }, + { 0xC2, 0, "CLRD", INH, M6x09_GENERAL }, + { 0xC3, 1, "CLRW", IND, M6x09_GENERAL }, + { 0xC4, 0, "NEGD", INH, M6x09_GENERAL }, + { 0xC5, 1, "NEGW", IND, M6x09_GENERAL }, + { 0xC6, 0, "INCD", INH, M6x09_GENERAL }, + { 0xC7, 1, "INCW", IND, M6x09_GENERAL }, + { 0xC8, 0, "DECD", INH, M6x09_GENERAL }, + { 0xC9, 1, "DECW", IND, M6x09_GENERAL }, + { 0xCA, 0, "TSTD", INH, M6x09_GENERAL }, + { 0xCB, 1, "TSTW", IND, M6x09_GENERAL }, + { 0xCC, 0, "ABSA", INH, M6x09_GENERAL }, + { 0xCD, 0, "ABSB", INH, M6x09_GENERAL }, + { 0xCE, 0, "ABSD", INH, M6x09_GENERAL }, + { 0xCF, 0, "BSET A,X,U", INH, M6x09_GENERAL }, + + { 0xD0, 0, "BSET D,X,U", INH, M6x09_GENERAL } }; diff --git a/src/devices/cpu/m6809/6x09dasm.h b/src/devices/cpu/m6809/6x09dasm.h index 036ba5c676e..fc6c27e7279 100644 --- a/src/devices/cpu/m6809/6x09dasm.h +++ b/src/devices/cpu/m6809/6x09dasm.h @@ -29,6 +29,8 @@ #ifndef MAME_CPU_M6809_6X09DASM_H #define MAME_CPU_M6809_6X09DASM_H +#include + #pragma once class m6x09_base_disassembler : public util::disasm_interface @@ -37,22 +39,21 @@ protected: class opcodeinfo; public: - // General, or 6309 only? - enum m6x09_instruction_level + // General, undocumented, or 6309 only? + enum m6x09_instruction_level : uint8_t { - M6x09_GENERAL, - HD6309_EXCLUSIVE + M6x09_GENERAL = 1, + M6809_UNDOCUMENTED = 2, + HD6309_EXCLUSIVE = 4 }; - m6x09_base_disassembler(const opcodeinfo *opcodes, size_t opcode_count, m6x09_instruction_level level) - : m_opcodes(opcodes, opcode_count), m_level(level) - { - } + m6x09_base_disassembler(const opcodeinfo *opcodes, size_t opcode_count, uint32_t level); + virtual u32 opcode_alignment() const override; virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override; protected: - enum m6x09_addressing_mode + enum m6x09_addressing_mode : uint8_t { INH, // Inherent PSHS, PSHU, // Push @@ -67,33 +68,41 @@ protected: IMM_RR, // Register-to-register IMM_BW, // Bitwise operations (6309 only) IMM_TFM, // Transfer from memory (6309 only) - PG1, // Switch to page 1 opcodes - PG2 // Switch to page 2 opcodes + PG2, // Switch to page 2 opcodes + PG3 // Switch to page 3 opcodes }; // Opcode structure class opcodeinfo { public: - constexpr opcodeinfo(uint16_t opcode, uint8_t length, const char *name, m6x09_addressing_mode mode, m6x09_instruction_level level, unsigned flags = 0) - : m_opcode(opcode), m_length(length), m_mode(mode), m_level(level), m_flags(flags), m_name(name) + constexpr opcodeinfo(uint16_t opcode, uint8_t operand_length, const char *name, m6x09_addressing_mode mode, uint32_t level, unsigned flags = 0) + : m_opcode(opcode), m_operand_length(operand_length), m_mode(mode), m_level(level), m_flags(flags), m_name(name) { } uint16_t opcode() const { return m_opcode; } - uint8_t length() const { return m_length; } + uint8_t operand_length() const { return m_operand_length; } m6x09_addressing_mode mode() const { return m_mode; } - m6x09_instruction_level level() const { return m_level; } + uint32_t level() const { return m_level; } unsigned flags() const { return m_flags; } const char *name() const { return m_name; } + struct compare + { + using is_transparent = void; + bool operator()(opcodeinfo const& lhs, opcodeinfo const& rhs) const; + bool operator()(uint16_t opcode, opcodeinfo const& rhs) const; + bool operator()(opcodeinfo const& lhs, uint16_t opcode) const; + }; + private: - uint16_t m_opcode; // 8-bit opcode value - uint8_t m_length; // Opcode length in bytes - m6x09_addressing_mode m_mode : 6; // Addressing mode - m6x09_instruction_level m_level : 2; // General, or 6309 only? - unsigned m_flags; // Disassembly flags - const char * m_name; // Opcode name + uint16_t m_opcode; // 8-bit opcode value + uint8_t m_operand_length; // Opcode length in bytes + m6x09_addressing_mode m_mode; // Addressing mode + uint8_t m_level; // General, or 6309 only? + unsigned m_flags; // Disassembly flags + const char * m_name; // Opcode name }; static const char *const m6x09_regs[5]; @@ -105,14 +114,16 @@ protected: virtual void register_register(std::ostream &stream, uint8_t pb) = 0; private: - util::contiguous_sequence_wrapper m_opcodes; - m6x09_instruction_level m_level; + std::set m_opcodes; + + uint32_t m_level; + uint16_t m_page; const opcodeinfo *fetch_opcode(const data_buffer &opcodes, offs_t &p); void assert_hd6309_exclusive() { - if (m_level < HD6309_EXCLUSIVE) + if (!(m_level & HD6309_EXCLUSIVE)) throw false; } }; @@ -120,7 +131,7 @@ private: class m6x09_disassembler : public m6x09_base_disassembler { public: - m6x09_disassembler(m6x09_instruction_level level, const char teregs[16][4]); + m6x09_disassembler(uint32_t level, const char teregs[16][4]); protected: virtual void indexed(std::ostream &stream, uint8_t pb, const data_buffer ¶ms, offs_t &p) override; diff --git a/src/devices/cpu/m6809/m6809.cpp b/src/devices/cpu/m6809/m6809.cpp index 227b07b4208..8495d8c27f1 100644 --- a/src/devices/cpu/m6809/m6809.cpp +++ b/src/devices/cpu/m6809/m6809.cpp @@ -22,6 +22,10 @@ History: +January 2023 tlindner: + Add 6809 undocumented opcodes as described here: + https://github.com/hoglet67/6809Decoder/wiki/Undocumented-6809-Behaviours + July 2016 ErikGav: Unify with 6309 pairs and quads (A+B=D, E+F=W, D+W=Q) @@ -214,6 +218,7 @@ void m6809_base_device::device_start() save_item(NAME(m_addressing_mode)); save_item(NAME(m_reg)); save_item(NAME(m_cond)); + save_item(NAME(m_free_run)); // set our instruction counter set_icountptr(m_icount); @@ -233,6 +238,7 @@ void m6809_base_device::device_reset() m_firq_line = false; m_irq_line = false; m_lds_encountered = false; + m_free_run = false; m_dp = 0x00; // reset direct page register diff --git a/src/devices/cpu/m6809/m6809.h b/src/devices/cpu/m6809/m6809.h index 9013f5c8263..96cfbebe1fd 100644 --- a/src/devices/cpu/m6809/m6809.h +++ b/src/devices/cpu/m6809/m6809.h @@ -279,6 +279,7 @@ private: // other state uint32_t m_state; bool m_cond; + bool m_free_run; // incidentals int m_clock_divider; diff --git a/src/devices/cpu/m6809/m6809.lst b/src/devices/cpu/m6809/m6809.lst index 18527afac31..4e6bc204144 100644 --- a/src/devices/cpu/m6809/m6809.lst +++ b/src/devices/cpu/m6809/m6809.lst @@ -13,22 +13,27 @@ MAIN: m_ppc = m_pc; debugger_instruction_hook(m_pc.w); +DISPATCH01: // opcode fetch m_lic_func(ASSERT_LINE); @m_opcode = read_opcode(); m_lic_func(CLEAR_LINE); + if (m_free_run) goto FREERUN; + // dispatch opcode switch(m_opcode) { case 0x00: case 0x01: %DIRECT; %NEG8; return; - case 0x03: case 0x02: %DIRECT; %COM8; return; + case 0x02: %DIRECT; %XNC8; return; + case 0x03: %DIRECT; %COM8; return; case 0x04: case 0x05: %DIRECT; %LSR8; return; case 0x06: %DIRECT; %ROR8; return; case 0x07: %DIRECT; %ASR8; return; case 0x08: %DIRECT; %ASL8; return; case 0x09: %DIRECT; %ROL8; return; - case 0x0A: case 0x0B: %DIRECT; %DEC8; return; + case 0x0A: %DIRECT; %DEC8; return; + case 0x0B: %DIRECT; %XDEC8; return; case 0x0C: %DIRECT; %INC8; return; case 0x0D: %DIRECT; %TST8; return; case 0x0E: %DIRECT; %JMP; return; @@ -38,10 +43,13 @@ MAIN: case 0x11: %DISPATCH11; return; case 0x12: %NOP; return; case 0x13: %SYNC; return; + case 0x14: case 0x15: %FREERUN; return; case 0x16: set_cond(true); %LBRANCH; return; case 0x17: %LBSR; return; + case 0x18: %X18; return; case 0x19: %DAA; return; case 0x1A: set_imm(); %ORCC; return; + case 0x1B: %NOP; return; case 0x1C: set_imm(); %ANDCC; return; case 0x1D: %SEX; return; case 0x1E: %EXG; return; @@ -72,60 +80,70 @@ MAIN: case 0x35: %PULS; return; case 0x36: %PSHU; return; case 0x37: %PULU; return; + case 0x38: set_imm(); %XANDCC; return; case 0x39: %RTS; return; case 0x3A: %ABX; return; case 0x3B: %RTI; return; case 0x3C: %CWAI; return; case 0x3D: %MUL; return; + case 0x3E: %XRES; return; case 0x3F: %SWI; return; case 0x40: case 0x41: set_a(); %NEG8; return; - case 0x43: case 0x42: set_a(); %COM8; return; + case 0x42: set_a(); %XNC8; return; + case 0x43: set_a(); %COM8; return; case 0x44: case 0x45: set_a(); %LSR8; return; case 0x46: set_a(); %ROR8; return; case 0x47: set_a(); %ASR8; return; case 0x48: set_a(); %ASL8; return; case 0x49: set_a(); %ROL8; return; - case 0x4A: case 0x4B: set_a(); %DEC8; return; + case 0x4A: set_a(); %DEC8; return; + case 0x4B: set_a(); %XDEC8; return; case 0x4C: set_a(); %INC8; return; case 0x4D: set_a(); %TST8; return; - case 0x4E: set_a(); %JMP; return; + case 0x4E: set_a(); %XCLR8; return; case 0x4F: set_a(); %CLR8; return; case 0x50: case 0x51: set_b(); %NEG8; return; - case 0x53: case 0x52: set_b(); %COM8; return; + case 0x52: set_b(); %XNC8; return; + case 0x53: set_b(); %COM8; return; case 0x54: case 0x55: set_b(); %LSR8; return; case 0x56: set_b(); %ROR8; return; case 0x57: set_b(); %ASR8; return; case 0x58: set_b(); %ASL8; return; case 0x59: set_b(); %ROL8; return; - case 0x5A: case 0x5B: set_b(); %DEC8; return; + case 0x5A: set_b(); %DEC8; return; + case 0x5B: set_b(); %XDEC8; return; case 0x5C: set_b(); %INC8; return; case 0x5D: set_b(); %TST8; return; - case 0x5E: set_b(); %JMP; return; + case 0x5E: set_b(); %XCLR8; return; case 0x5F: set_b(); %CLR8; return; case 0x60: case 0x61: %INDEXED; %NEG8; return; - case 0x63: case 0x62: %INDEXED; %COM8; return; + case 0x62: %INDEXED; %XNC8; return; + case 0x63: %INDEXED; %COM8; return; case 0x64: case 0x65: %INDEXED; %LSR8; return; case 0x66: %INDEXED; %ROR8; return; case 0x67: %INDEXED; %ASR8; return; case 0x68: %INDEXED; %ASL8; return; case 0x69: %INDEXED; %ROL8; return; - case 0x6A: case 0x6B: %INDEXED; %DEC8; return; + case 0x6A: %INDEXED; %DEC8; return; + case 0x6B: %INDEXED; %XDEC8; return; case 0x6C: %INDEXED; %INC8; return; case 0x6D: %INDEXED; %TST8; return; case 0x6E: %INDEXED; %JMP; return; case 0x6F: %INDEXED; %CLR8; return; case 0x70: case 0x71: %EXTENDED; %NEG8; return; - case 0x73: case 0x72: %EXTENDED; %COM8; return; + case 0x72: %EXTENDED; %XNC8; return; + case 0x73: %EXTENDED; %COM8; return; case 0x74: case 0x75: %EXTENDED; %LSR8; return; case 0x76: %EXTENDED; %ROR8; return; case 0x77: %EXTENDED; %ASR8; return; case 0x78: %EXTENDED; %ASL8; return; case 0x79: %EXTENDED; %ROL8; return; - case 0x7A: case 0x7B: %EXTENDED; %DEC8; return; + case 0x7A: %EXTENDED; %DEC8; return; + case 0x7B: %EXTENDED; %XDEC8; return; case 0x7C: %EXTENDED; %INC8; return; case 0x7D: %EXTENDED; %TST8; return; case 0x7E: %EXTENDED; %JMP; return; @@ -138,7 +156,7 @@ MAIN: case 0x84: set_regop8(m_q.r.a); set_imm(); %AND8; return; case 0x85: set_regop8(m_q.r.a); set_imm(); %BIT8; return; case 0x86: set_regop8(m_q.r.a); set_imm(); %LD8; return; - case 0x87: set_regop8(m_q.r.a); set_imm(); %ST8; return; + case 0x87: set_regop8(m_q.r.a); set_imm(); %XST8; return; case 0x88: set_regop8(m_q.r.a); set_imm(); %EOR8; return; case 0x89: set_regop8(m_q.r.a); set_imm(); %ADC8; return; case 0x8A: set_regop8(m_q.r.a); set_imm(); %OR8; return; @@ -146,7 +164,7 @@ MAIN: case 0x8C: set_regop16(m_x); set_imm(); %CMP16; return; case 0x8D: %BSR; return; case 0x8E: set_regop16(m_x); set_imm(); %LD16; return; - case 0x8F: set_regop16(m_x); set_imm(); %ST16; return; + case 0x8F: set_regop16(m_x); set_imm(); %XST16; return; case 0x90: set_regop8(m_q.r.a); %DIRECT; %SUB8; return; case 0x91: set_regop8(m_q.r.a); %DIRECT; %CMP8; return; @@ -206,15 +224,15 @@ MAIN: case 0xC4: set_regop8(m_q.r.b); set_imm(); %AND8; return; case 0xC5: set_regop8(m_q.r.b); set_imm(); %BIT8; return; case 0xC6: set_regop8(m_q.r.b); set_imm(); %LD8; return; - case 0xC7: set_regop8(m_q.r.b); set_imm(); %ST8; return; + case 0xC7: set_regop8(m_q.r.b); set_imm(); %XST8; return; case 0xC8: set_regop8(m_q.r.b); set_imm(); %EOR8; return; case 0xC9: set_regop8(m_q.r.b); set_imm(); %ADC8; return; case 0xCA: set_regop8(m_q.r.b); set_imm(); %OR8; return; case 0xCB: set_regop8(m_q.r.b); set_imm(); %ADD8; return; case 0xCC: set_regop16(m_q.p.d); set_imm(); %LD16; return; - case 0xCD: set_regop16(m_q.p.d); set_imm(); %ST16; return; + case 0xCD: %FREERUN; return; case 0xCE: set_regop16(m_u); set_imm(); %LD16; return; - case 0xCF: set_regop16(m_u); set_imm(); %ST16; return; + case 0xCF: set_regop16(m_u); set_imm(); %XST16; return; case 0xD0: set_regop8(m_q.r.b); %DIRECT; %SUB8; return; case 0xD1: set_regop8(m_q.r.b); %DIRECT; %CMP8; return; @@ -274,6 +292,9 @@ DISPATCH10: @m_opcode = read_opcode(); switch(m_opcode) { + case 0x10: %DISPATCH10; return; + case 0x11: %DISPATCH10; return; + case 0x20: set_cond(true); %LBRANCH; return; case 0x21: set_cond(false); %LBRANCH; return; case 0x22: set_cond(cond_hi()); %LBRANCH; return; @@ -291,35 +312,48 @@ DISPATCH10: case 0x2E: set_cond(cond_gt()); %LBRANCH; return; case 0x2F: set_cond(!cond_gt()); %LBRANCH; return; + case 0x3E: %XSWI2; return; case 0x3F: %SWI2; return; case 0x83: set_regop16(m_q.p.d); set_imm(); %CMP16; return; + case 0x87: set_regop8(m_q.r.a); set_imm(); %XST8; return; case 0x8C: set_regop16(m_y); set_imm(); %CMP16; return; case 0x8E: set_regop16(m_y); set_imm(); %LD16; return; - case 0x8F: set_regop16(m_y); set_imm(); %ST16; return; + case 0x8F: set_regop16(m_y); set_imm(); %XST16; return; + case 0x93: set_regop16(m_q.p.d); %DIRECT; %CMP16; return; case 0x9C: set_regop16(m_y); %DIRECT; %CMP16; return; case 0x9E: set_regop16(m_y); %DIRECT; %LD16; return; case 0x9F: set_regop16(m_y); %DIRECT; %ST16; return; + case 0xA3: set_regop16(m_q.p.d); %INDEXED; %CMP16; return; case 0xAC: set_regop16(m_y); %INDEXED; %CMP16; return; case 0xAE: set_regop16(m_y); %INDEXED; %LD16; return; case 0xAF: set_regop16(m_y); %INDEXED; %ST16; return; + case 0xB3: set_regop16(m_q.p.d); %EXTENDED; %CMP16; return; case 0xBC: set_regop16(m_y); %EXTENDED; %CMP16; return; case 0xBE: set_regop16(m_y); %EXTENDED; %LD16; return; case 0xBF: set_regop16(m_y); %EXTENDED; %ST16; return; + case 0xC3: set_regop16(m_q.p.d); set_imm(); %XADD16; return; + case 0xC7: set_regop8(m_q.r.b); set_imm(); %XST8; return; case 0xCE: set_regop16(m_s); set_imm(); %LD16; return; - case 0xCF: set_regop16(m_s); set_imm(); %ST16; return; + case 0xCF: set_regop16(m_s); set_imm(); %XST16; return; + + case 0xD3: set_regop16(m_q.p.d); %DIRECT; %XADD16; return; case 0xDE: set_regop16(m_s); %DIRECT; %LD16; return; case 0xDF: set_regop16(m_s); %DIRECT; %ST16; return; + + case 0xE3: set_regop16(m_q.p.d); %INDEXED; %XADD16; return; case 0xEE: set_regop16(m_s); %INDEXED; %LD16; return; case 0xEF: set_regop16(m_s); %INDEXED; %ST16; return; + + case 0xF3: set_regop16(m_q.p.d); %EXTENDED; %XADD16; return; case 0xFE: set_regop16(m_s); %EXTENDED; %LD16; return; case 0xFF: set_regop16(m_s); %EXTENDED; %ST16; return; - default: %ILLEGAL; return; + default: %DISPATCH01; return; } return; @@ -327,16 +361,28 @@ DISPATCH11: @m_opcode = read_opcode(); switch(m_opcode) { + case 0x10: %DISPATCH11; return; + case 0x11: %DISPATCH11; return; + + case 0x3E: %XFIRQ; return; case 0x3F: %SWI3; return; case 0x83: set_regop16(m_u); set_imm(); %CMP16; return; case 0x8C: set_regop16(m_s); set_imm(); %CMP16; return; + case 0x87: set_regop8(m_q.r.a); set_imm(); %XST8; return; + case 0x8F: set_regop16(m_x); set_imm(); %XST16; return; case 0x93: set_regop16(m_u); %DIRECT; %CMP16; return; case 0x9C: set_regop16(m_s); %DIRECT; %CMP16; return; + case 0xC3: set_regop16(m_u); set_imm(); %XADD16; return; + case 0xC7: set_regop8(m_q.r.b); set_imm(); %XST8; return; + case 0xCF: set_regop16(m_u); set_imm(); %XST16; return; case 0xA3: set_regop16(m_u); %INDEXED; %CMP16; return; case 0xAC: set_regop16(m_s); %INDEXED; %CMP16; return; case 0xB3: set_regop16(m_u); %EXTENDED; %CMP16; return; case 0xBC: set_regop16(m_s); %EXTENDED; %CMP16; return; - default: %ILLEGAL; return; + case 0xD3: set_regop16(m_u); %DIRECT; %XADD16; return; + case 0xE3: set_regop16(m_u); %INDEXED; %XADD16; return; + case 0xF3: set_regop16(m_u); %EXTENDED; %XADD16; return; + default: %DISPATCH01; return; } return; @@ -600,6 +646,113 @@ TFR: @dummy_vma(hd6309_native_mode() ? 2 : 4); return; +FREERUN: + // A CPU test mode that increments the address bus until reset. + m_free_run = true; + return; + +X18: + @m_temp.b.l = read_opcode_arg(m_pc.w); + m_temp.b.l = (m_cc & m_temp.b.l) << 1; + m_cc = m_temp.b.l | ((m_cc & 0x04) >> 1); + return; + +XANDCC: + @eat(1); + goto ANDCC; + +XRES: + set_ea(VECTOR_RESET_FFFE); + standard_irq_callback(M6809_SWI, m_pc.w); + set_regop16(m_s); + m_temp.w = entire_state_registers(); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + %PUSH_REGISTERS; + goto INTERRUPT_VECTOR; + +XNC8: + if (m_cc & CC_C) + goto COM8; + else + goto NEG8; + +XDEC8: + @m_temp.b.l = read_operand(); + if (m_temp.b.l) + m_cc |= CC_C; + else + m_cc &= ~CC_C; + + m_temp.b.l = set_flags(CC_NZ, m_temp.b.l, 1, m_temp.b.l - 1); + if(!hd6309_native_mode() || !is_register_addressing_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(m_temp.b.l); + return; + +XCLR8: + @read_operand(); + m_cc &= ~CC_NZV; + m_cc |= CC_Z; + if(!hd6309_native_mode() || !is_register_addressing_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + @write_operand(0); + return; + +XST8: + // TODO: Flag setting is much more complex, see: + // https://github.com/hoglet67/6809Decoder/wiki/Undocumented-6809-Behaviours#store-immediate + + @read_operand(); + set_flags(CC_NZV, regop8()); + return; + +XST16: + // TODO: Flag setting is much more complex, see: + // https://github.com/hoglet67/6809Decoder/wiki/Undocumented-6809-Behaviours#store-immediate + + m_temp.b.h = read_operand(0); + write_memory(m_pc.w++, regop16().b.l); + set_flags(CC_NZV, regop16().w); + return; + +XSWI2: + set_ea(VECTOR_SWI2); + standard_irq_callback(M6809_SWI, m_pc.w); + set_regop16(m_s); + m_temp.w = entire_state_registers(); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + %PUSH_REGISTERS; + goto INTERRUPT_VECTOR; + +XADD16: + @m_temp.b.h = read_operand(0); + @m_temp.b.l = read_operand(1); + set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w + m_temp.w); + if(!hd6309_native_mode()) + { + @dummy_read_opcode_arg(0); + ; + } + return; + +XFIRQ: + set_ea(VECTOR_FIRQ); + standard_irq_callback(M6809_SWI, m_pc.w); + set_regop16(m_s); + m_temp.w = entire_state_registers(); + @dummy_read_opcode_arg(0); + @dummy_vma(1); + %PUSH_REGISTERS; + goto INTERRUPT_VECTOR; + ILLEGAL: log_illegal(); return; -- cgit v1.2.3