From 5bb63697f066a04c3072f6e4bed52a5bb446d7c8 Mon Sep 17 00:00:00 2001 From: AJR Date: Fri, 1 Feb 2019 10:21:55 -0500 Subject: mb8421: Eliminate address_space argument from read/write handlers (nw) --- src/devices/machine/mb8421.cpp | 16 ++++++++-------- src/devices/machine/mb8421.h | 16 ++++++++-------- src/mame/drivers/hng64.cpp | 8 ++++---- src/mame/drivers/m72.cpp | 8 ++++---- src/mame/drivers/model1.cpp | 2 +- src/mame/drivers/segaxbd.cpp | 4 ++-- 6 files changed, 27 insertions(+), 27 deletions(-) diff --git a/src/devices/machine/mb8421.cpp b/src/devices/machine/mb8421.cpp index a5b08f5ea90..e6344843f92 100644 --- a/src/devices/machine/mb8421.cpp +++ b/src/devices/machine/mb8421.cpp @@ -129,14 +129,14 @@ void mb8421_master_device::update_intr(offs_t offset) // (write to 7FF asserts INTR) //------------------------------------------------- -WRITE8_MEMBER(mb8421_device::left_w) +void mb8421_device::left_w(offs_t offset, u8 data) { offset &= 0x7ff; m_ram[offset] = data; update_intr(offset); } -WRITE16_MEMBER(mb8421_mb8431_16_device::left_w) +void mb8421_mb8431_16_device::left_w(offs_t offset, u16 data, u16 mem_mask) { offset &= 0x7ff; COMBINE_DATA(&m_ram[offset]); @@ -148,14 +148,14 @@ WRITE16_MEMBER(mb8421_mb8431_16_device::left_w) // (read from 7FE acknowledges INTL) //------------------------------------------------- -READ8_MEMBER(mb8421_device::left_r) +u8 mb8421_device::left_r(offs_t offset) { offset &= 0x7ff; update_intr(offset); return m_ram[offset]; } -READ16_MEMBER(mb8421_mb8431_16_device::left_r) +u16 mb8421_mb8431_16_device::left_r(offs_t offset, u16 mem_mask) { offset &= 0x7ff; update_intr(offset); @@ -167,14 +167,14 @@ READ16_MEMBER(mb8421_mb8431_16_device::left_r) // (write to 7FE asserts INTL) //------------------------------------------------- -WRITE8_MEMBER(mb8421_device::right_w) +void mb8421_device::right_w(offs_t offset, u8 data) { offset &= 0x7ff; m_ram[offset] = data; update_intr(offset); } -WRITE16_MEMBER(mb8421_mb8431_16_device::right_w) +void mb8421_mb8431_16_device::right_w(offs_t offset, u16 data, u16 mem_mask) { offset &= 0x7ff; COMBINE_DATA(&m_ram[offset]); @@ -186,14 +186,14 @@ WRITE16_MEMBER(mb8421_mb8431_16_device::right_w) // (read from 7FF acknowledges INTR) //------------------------------------------------- -READ8_MEMBER(mb8421_device::right_r) +u8 mb8421_device::right_r(offs_t offset) { offset &= 0x7ff; update_intr(offset); return m_ram[offset]; } -READ16_MEMBER(mb8421_mb8431_16_device::right_r) +u16 mb8421_mb8431_16_device::right_r(offs_t offset, u16 mem_mask) { offset &= 0x7ff; update_intr(offset); diff --git a/src/devices/machine/mb8421.h b/src/devices/machine/mb8421.h index 4ef0a010c9b..00e8f8d207f 100644 --- a/src/devices/machine/mb8421.h +++ b/src/devices/machine/mb8421.h @@ -108,10 +108,10 @@ public: u8 peek(offs_t offset) const { return m_ram[offset & 0x7ff]; } - DECLARE_WRITE8_MEMBER(left_w); - DECLARE_READ8_MEMBER(left_r); - DECLARE_WRITE8_MEMBER(right_w); - DECLARE_READ8_MEMBER(right_r); + void left_w(offs_t offset, u8 data); + u8 left_r(offs_t offset); + void right_w(offs_t offset, u8 data); + u8 right_r(offs_t offset); protected: mb8421_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock); @@ -140,10 +140,10 @@ public: u16 peek(offs_t offset) const { return m_ram[offset & 0x7ff]; } - DECLARE_WRITE16_MEMBER(left_w); - DECLARE_READ16_MEMBER(left_r); - DECLARE_WRITE16_MEMBER(right_w); - DECLARE_READ16_MEMBER(right_r); + void left_w(offs_t offset, u16 data, u16 mem_mask = 0xffff); + u16 left_r(offs_t offset, u16 mem_mask = 0xffff); + void right_w(offs_t offset, u16 data, u16 mem_mask = 0xffff); + u16 right_r(offs_t offset, u16 mem_mask = 0xffff); protected: // device-level overrides diff --git a/src/mame/drivers/hng64.cpp b/src/mame/drivers/hng64.cpp index 89688fe9561..343bf35fa53 100644 --- a/src/mame/drivers/hng64.cpp +++ b/src/mame/drivers/hng64.cpp @@ -699,7 +699,7 @@ READ8_MEMBER(hng64_state::hng64_dualport_r) } } - return m_dt71321_dpram->right_r(space, offset); + return m_dt71321_dpram->right_r(offset); } /* @@ -731,7 +731,7 @@ Beast Busters 2 outputs (all at offset == 0x1c): WRITE8_MEMBER(hng64_state::hng64_dualport_w) { - m_dt71321_dpram->right_w(space,offset, data); + m_dt71321_dpram->right_w(offset, data); LOG("%s: dualport WRITE %04x %02x\n", machine().describe_context(), offset, data); } @@ -2016,7 +2016,7 @@ WRITE8_MEMBER(hng64_state::ioport7_w) READ8_MEMBER(hng64_state::ioport0_r) { uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff; - uint8_t ret = m_dt71321_dpram->left_r(space, addr); + uint8_t ret = m_dt71321_dpram->left_r(addr); LOG("%s: ioport0_r %02x (from address %04x)\n", machine().describe_context(), ret, addr); return ret; @@ -2025,7 +2025,7 @@ READ8_MEMBER(hng64_state::ioport0_r) WRITE8_MEMBER(hng64_state::ioport0_w) { uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff; - m_dt71321_dpram->left_w(space, addr, data); + m_dt71321_dpram->left_w(addr, data); LOG("%s: ioport0_w %02x (to address %04x)\n", machine().describe_context(), data, addr); } diff --git a/src/mame/drivers/m72.cpp b/src/mame/drivers/m72.cpp index 0ce6cad4fc5..ecc9a1744f6 100644 --- a/src/mame/drivers/m72.cpp +++ b/src/mame/drivers/m72.cpp @@ -310,7 +310,7 @@ TIMER_CALLBACK_MEMBER(m72_state::delayed_ram16_w) uint16_t mem_mask = (BIT(param, 28) ? 0xff00 : 0x0000) | (BIT(param, 27) ? 0x00ff : 0x0000); logerror("MB8421/MB8431 left_w(0x%03x, 0x%04x, 0x%04x)\n", offset, val, mem_mask); - m_dpram->left_w(machine().dummy_space(), offset, val, mem_mask); + m_dpram->left_w(offset, val, mem_mask); } TIMER_CALLBACK_MEMBER(m72_state::delayed_ram8_w) @@ -319,9 +319,9 @@ TIMER_CALLBACK_MEMBER(m72_state::delayed_ram8_w) uint16_t offset = (param >> 9) & 0x07ff; if (BIT(param, 8)) - m_dpram->right_w(machine().dummy_space(), offset, val << 8, 0xff00); + m_dpram->right_w(offset, val << 8, 0xff00); else - m_dpram->right_w(machine().dummy_space(), offset, val, 0x00ff); + m_dpram->right_w(offset, val, 0x00ff); } @@ -337,7 +337,7 @@ WRITE8_MEMBER(m72_state::mcu_data_w) READ8_MEMBER(m72_state::mcu_data_r) { - return (m_dpram->right_r(space, offset >> 1) >> (BIT(offset, 0) ? 8 : 0)) & 0xff; + return (m_dpram->right_r(offset >> 1) >> (BIT(offset, 0) ? 8 : 0)) & 0xff; } READ8_MEMBER(m72_state::mcu_sample_r) diff --git a/src/mame/drivers/model1.cpp b/src/mame/drivers/model1.cpp index 9546bf48ec8..b776b6159a7 100644 --- a/src/mame/drivers/model1.cpp +++ b/src/mame/drivers/model1.cpp @@ -600,7 +600,7 @@ READ8_MEMBER( model1_state::dpram_r ) { // insert waitstate m_maincpu->adjust_icount(-1); - return m_dpram->right_r(space, offset); + return m_dpram->right_r(offset); } WRITE8_MEMBER( model1_state::vf_outputs_w ) diff --git a/src/mame/drivers/segaxbd.cpp b/src/mame/drivers/segaxbd.cpp index af539851914..e4a110cb409 100644 --- a/src/mame/drivers/segaxbd.cpp +++ b/src/mame/drivers/segaxbd.cpp @@ -732,7 +732,7 @@ WRITE8_MEMBER(segaxbd_state::smgp_motor_w) READ8_MEMBER(segaxbd_rascot_state::commram_r) { - return m_commram->right_r(space, m_commram_bank << 3 | offset); + return m_commram->right_r(m_commram_bank << 3 | offset); } @@ -743,7 +743,7 @@ READ8_MEMBER(segaxbd_rascot_state::commram_r) WRITE8_MEMBER(segaxbd_rascot_state::commram_w) { - m_commram->right_w(space, m_commram_bank << 3 | offset, data); + m_commram->right_w(m_commram_bank << 3 | offset, data); } -- cgit v1.2.3