From 5b600eac2c0a9dc9ca54b3485b04cf940cc5bb3a Mon Sep 17 00:00:00 2001 From: Ted Green Date: Mon, 10 Jul 2017 19:11:48 -0600 Subject: WIP: Get audio to start working in mwskins and add I40 board to vegas driver. (nw) --- src/mame/audio/dcs.cpp | 216 ++++++++++++---- src/mame/audio/dcs.h | 8 +- src/mame/drivers/atlantis.cpp | 47 ++-- src/mame/drivers/vegas.cpp | 554 ++++++++++++++++++++++++++---------------- 4 files changed, 553 insertions(+), 272 deletions(-) diff --git a/src/mame/audio/dcs.cpp b/src/mame/audio/dcs.cpp index 02959b70cdb..c2109facd3b 100644 --- a/src/mame/audio/dcs.cpp +++ b/src/mame/audio/dcs.cpp @@ -367,7 +367,7 @@ static ADDRESS_MAP_START( dcs2_2104_data_map, AS_DATA, 16, dcs_audio_device ) AM_RANGE(0x0403, 0x0403) AM_READ(latch_status_r) AM_RANGE(0x0404, 0x0407) AM_READ(fifo_input_r) AM_RANGE(0x0480, 0x0483) AM_READWRITE(sdrc_r, sdrc_w) - AM_RANGE(0x3800, 0x38ff) AM_RAM AM_SHARE("iram") + AM_RANGE(0x3800, 0x39ff) AM_RAM AM_SHARE("iram") AM_RANGE(0x3fe0, 0x3fff) AM_READWRITE(adsp_control_r, adsp_control_w) ADDRESS_MAP_END @@ -576,10 +576,6 @@ TIMER_CALLBACK_MEMBER( dcs_audio_device::dcs_reset ) m_timer_scale = 1; m_internal_timer->reset(); - /* start the SPORT0 timer */ - if (m_sport_timer != nullptr) - m_sport_timer->adjust(attotime::from_hz(1000), 0, attotime::from_hz(1000)); - /* reset the HLE transfer states */ m_transfer.dcs_state = m_transfer.state = 0; } @@ -646,9 +642,15 @@ void dcs_audio_device::dcs_register_state() machine().save().register_postload(save_prepost_delegate(FUNC(dcs_audio_device::sdrc_remap_memory), this)); if (m_rev == 4) - machine().save().register_postload(save_prepost_delegate(FUNC(dcs_audio_device::dmovlay_remap_memory), this)); + machine().save().register_postload(save_prepost_delegate(FUNC(dcs_audio_device::denver_postload), this)); } +void dcs_audio_device::denver_postload() +{ + m_data_bank->set_entry(DENV_DM_PG % m_sounddata_banks); + dmovlay_remap_memory(); + denver_alloc_dmadac(); +} //------------------------------------------------- // dcs_audio_device - constructor @@ -666,7 +668,7 @@ dcs_audio_device::dcs_audio_device(const machine_config &mconfig, device_type ty m_size(0), m_incs(0), m_reg_timer(nullptr), - m_sport_timer(nullptr), + m_sport0_timer(nullptr), m_internal_timer(nullptr), m_ireg(0), m_ireg_base(0), @@ -698,6 +700,7 @@ dcs_audio_device::dcs_audio_device(const machine_config &mconfig, device_type ty m_timers_fired(0), m_sram(nullptr), m_polling_base(nullptr), + m_polling32_base(nullptr), m_internal_program_ram(nullptr), m_external_program_ram(nullptr), m_internal_data_ram(nullptr), @@ -850,15 +853,22 @@ void dcs2_audio_device::device_start() /* create the timers */ m_internal_timer = subdevice("dcs_int_timer"); m_reg_timer = subdevice("dcs_reg_timer"); - m_sport_timer = subdevice("dcs_sport_timer"); + m_sport0_timer = subdevice("dcs_sport0_timer"); /* we don't do auto-ack by default */ m_auto_ack = false; /* install the speedup handler */ if (m_polling_offset) { - m_cpu->space(AS_DATA).install_readwrite_handler(m_polling_offset, m_polling_offset, read16_delegate(FUNC(dcs_audio_device::dcs_polling_r),this), write16_delegate(FUNC(dcs_audio_device::dcs_polling_w),this)); - m_polling_base = m_iram + (m_polling_offset - 0x3800); + if (m_rev < 3) { + m_cpu->space(AS_DATA).install_readwrite_handler(m_polling_offset, m_polling_offset, read16_delegate(FUNC(dcs_audio_device::dcs_polling_r), this), write16_delegate(FUNC(dcs_audio_device::dcs_polling_w), this)); + m_polling_base = m_iram + (m_polling_offset - 0x3800); + } + else { + // ADSP 2181 (DSIO and DENVER) use program memory + m_cpu->space(AS_PROGRAM).install_readwrite_handler(m_polling_offset, m_polling_offset, read32_delegate(FUNC(dcs_audio_device::dcs_polling32_r), this), write32_delegate(FUNC(dcs_audio_device::dcs_polling32_w), this)); + m_polling32_base = m_internal_program_ram + (m_polling_offset - 0x2000); + } } /* allocate a watchdog timer for HLE transfers */ m_transfer.hle_enabled = (ENABLE_HLE_TRANSFERS && m_dram_in_mb != 0); @@ -1178,6 +1188,7 @@ READ16_MEMBER( dcs_audio_device::dsio_r ) dsio.channelbits ^= 0x0010; result = (result & ~0x0010) | dsio.channelbits; } + if (LOG_DCS_IO && offset != 2) logerror("%04X: dsio_r 0x%x = %04x\n", space.device().safe_pc(), offset, result); return result; } @@ -1206,6 +1217,7 @@ WRITE16_MEMBER( dcs_audio_device::dsio_w ) m_data_bank->set_entry(DSIO_DM_PG % m_sounddata_banks); break; } + if (LOG_DCS_IO) logerror("%04X: dsio_w 0x%x = %04x\n", space.device().safe_pc(), offset, data); } @@ -1221,8 +1233,25 @@ void dcs_audio_device::denver_reset() memset(&m_dsio, 0, sizeof(m_dsio)); m_dmovlay_val = 0; dmovlay_remap_memory(); + dmadac_enable(&m_dmadac[0], m_channels, 0); + m_reg_timer->reset(); } +void dcs_audio_device::denver_alloc_dmadac() +{ + int enable = DENV_MUTE; + for (int chan = 0; chan < m_channels; chan++) + { + char buffer[10]; + sprintf(buffer, "dac%d", chan + 1); + m_dmadac[chan] = subdevice(buffer); + } + dmadac_enable(&m_dmadac[0], m_channels, enable); + if (m_channels < 6) + dmadac_enable(&m_dmadac[m_channels], 6 - m_channels, false); + //if (enable) + // recompute_sample_rate(); +} READ16_MEMBER( dcs_audio_device::denver_r ) { @@ -1231,9 +1260,10 @@ READ16_MEMBER( dcs_audio_device::denver_r ) if (offset == 3) { /* returns 1 for DRAM, 2 for EPROM-based */ - result = 0x0001; + // SDRC Revision + result = 0x0003; } - if (LOG_DCS_IO) logerror("denver: denver_r 0x%x = %04x\n", offset, result); + if (LOG_DCS_IO) logerror("%04X: denver_r 0x%x = %04x\n", space.device().safe_pc(), offset, result); return result; } @@ -1241,32 +1271,31 @@ READ16_MEMBER( dcs_audio_device::denver_r ) WRITE16_MEMBER( dcs_audio_device::denver_w ) { dsio_state &dsio = m_dsio; - int enable, channels, chan; + int channels; + + uint16_t data_change = dsio.reg[offset] ^ data; switch (offset) { /* offset 1 controls I/O */ case 1: dsio.reg[1] = data; - + // Ignore LED + data_change &= ~(1 << 13); /* determine /MUTE and number of channels */ - enable = DENV_MUTE; channels = 2 + 2 * DENV_CHANNELS; - /* if the number of channels has changed, adjust */ + /* if the number of channels has changed adjust */ if (channels != m_channels) { m_channels = channels; - for (chan = 0; chan < m_channels; chan++) - { - char buffer[10]; - sprintf(buffer, "dac%d", chan + 1); - m_dmadac[chan] = subdevice(buffer); - } - dmadac_enable(&m_dmadac[0], m_channels, enable); - if (m_channels <= 6) + denver_alloc_dmadac(); + } + // Set MUTE + if (data_change & (1 << 14)) { + dmadac_enable(&m_dmadac[0], m_channels, DENV_MUTE); + if (m_channels < 6) dmadac_enable(&m_dmadac[m_channels], 6 - m_channels, false); - recompute_sample_rate(); } break; @@ -1281,7 +1310,7 @@ WRITE16_MEMBER( dcs_audio_device::denver_w ) m_fifo_reset_w(1); break; } - if (LOG_DCS_IO) logerror("denver: denver_w 0x%x = %04x\n", offset, data); + if (LOG_DCS_IO) logerror("%04X: denver_w 0x%x = %04x\n", space.device().safe_pc(), offset, data); } @@ -1307,30 +1336,38 @@ WRITE32_MEMBER( dcs_audio_device::dsio_idma_data_w ) { dsio_state &dsio = m_dsio; uint32_t pc = space.device().safe_pc(); + // IDMA is to internal memory only + m_ram_map->set_bank(0); if (ACCESSING_BITS_0_15) { - if (LOG_DCS_TRANSFERS) + if (LOG_DCS_TRANSFERS && !(downcast(m_cpu)->idma_addr_r() & 0x0ffc)) logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, downcast(m_cpu)->idma_addr_r(), data & 0xffff); downcast(m_cpu)->idma_data_w(data & 0xffff); } if (ACCESSING_BITS_16_31) { - if (LOG_DCS_TRANSFERS) + if (LOG_DCS_TRANSFERS && !(downcast(m_cpu)->idma_addr_r() & 0x0ffc)) logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, downcast(m_cpu)->idma_addr_r(), data >> 16); downcast(m_cpu)->idma_data_w(data >> 16); } if (dsio.start_on_next_write && --dsio.start_on_next_write == 0) { - logerror("Starting DSIO CPU\n"); + logerror("%08X: Starting DSIO CPU\n", machine().device("maincpu")->safe_pc()); m_cpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE); } + // Restore internal/external mapping + m_ram_map->set_bank(m_dmovlay_val); } READ32_MEMBER( dcs_audio_device::dsio_idma_data_r ) { uint32_t result; + // IDMA is to internal memory only + m_ram_map->set_bank(0); result = downcast(m_cpu)->idma_data_r(); + // Restore internal/external mapping + m_ram_map->set_bank(m_dmovlay_val); if (LOG_DCS_TRANSFERS) logerror("%08X:IDMA_data_r(%04X) = %04X\n", space.device().safe_pc(), downcast(m_cpu)->idma_addr_r(), result); return result; @@ -1345,8 +1382,12 @@ void dcs_audio_device::dmovlay_remap_memory() } else { m_ram_map->set_bank(1); } - if (LOG_DCS_IO) - logerror("%s dmovlay_remap_memory: Switching data ram location dmovlay=%i\n", machine().describe_context(), m_dmovlay_val); + if (LOG_DCS_IO) { + if (m_dmovlay_val==0) + logerror("%s dmovlay_remap_memory: Switching to internal data ram location dmovlay=%i\n", machine().describe_context(), m_dmovlay_val); + else + logerror("%s dmovlay_remap_memory: Switching to external data ram location dmovlay=%i\n", machine().describe_context(), m_dmovlay_val); + } } WRITE32_MEMBER(dcs_audio_device::dmovlay_callback) @@ -1472,7 +1513,7 @@ void dcs_audio_device::data_w(uint16_t data) return; /* if we are DCS1, set a timer to latch the data */ - if (m_sport_timer == nullptr) + if (m_sport0_timer == nullptr) machine().scheduler().synchronize(timer_expired_delegate(FUNC(dcs_audio_device::dcs_delayed_data_w_callback),this), data); else dcs_delayed_data_w(data); @@ -1552,6 +1593,8 @@ TIMER_CALLBACK_MEMBER( dcs_audio_device::delayed_ack_w_callback ) void dcs_audio_device::ack_w() { + if (LOG_DCS_IO) + logerror("%s:ack_w\n", machine().describe_context()); machine().scheduler().synchronize(timer_expired_delegate(FUNC(dcs_audio_device::delayed_ack_w_callback),this)); } @@ -1577,8 +1620,8 @@ uint16_t dcs_audio_device::data_r() TIMER_CALLBACK_MEMBER( dcs_audio_device::output_control_delayed_w ) { - if (LOG_DCS_IO) - logerror("output_control = %04X\n", param); + //if (LOG_DCS_IO) + // logerror("output_control = %04X\n", param); m_output_control = param; m_output_control_cycles = 0; } @@ -1587,13 +1630,16 @@ TIMER_CALLBACK_MEMBER( dcs_audio_device::output_control_delayed_w ) WRITE16_MEMBER( dcs_audio_device::output_control_w ) { if (LOG_DCS_IO) - logerror("%04X:output_control = %04X\n", space.device().safe_pc(), data); + logerror("%04X:output_control_w = %04X\n", space.device().safe_pc(), data); + //printf("%04X:output_control_w = %04X\n", space.device().safe_pc(), data); machine().scheduler().synchronize(timer_expired_delegate(FUNC(dcs_audio_device::output_control_delayed_w),this), data); } READ16_MEMBER( dcs_audio_device::output_control_r ) { + if (LOG_DCS_IO) + logerror("%04X:output_control_r = %04X\n", space.device().safe_pc(), m_output_control); m_output_control_cycles = m_cpu->total_cycles(); return m_output_control; } @@ -1601,7 +1647,15 @@ READ16_MEMBER( dcs_audio_device::output_control_r ) int dcs_audio_device::data2_r() { - return m_output_control; + if (LOG_DCS_IO) + logerror("%08X dcs:data2_r = %04X\n", machine().device("maincpu")->safe_pc(), m_output_control); + if (m_rev >= 3) { + // Not sure about this but allows sf2049 and roadburn to pass audio initialization tests at boot + return m_output_control << 8; + } + else { + return m_output_control; + } } @@ -1684,6 +1738,14 @@ void dcs_audio_device::reset_timer() m_program->read_dword(0x1c*4) == 0x0A001F) /* RTI */ { m_timer_ignore = true; + } else if ( + // ADSP 2181 (DSIO and DENVER) + m_program->read_dword(0x28*4) == 0x18032F && /* JUMP $0032 */ + m_program->read_dword(0x32*4) == 0x0c0030 && /* ENA SEC_REG */ + m_program->read_dword(0x33*4) == 0x014828 && /* SI = IO($482) */ + m_program->read_dword(0x34*4) == 0x01C828) /* IO($482) = SI */ + { + m_timer_ignore = true; } } @@ -1741,9 +1803,11 @@ READ16_MEMBER( dcs_audio_device::adsp_control_r ) switch (offset) { case PROG_FLAG_DATA_REG: - /* Denver waits for this & 0x000e == 0x0000 */ - /* Denver waits for this & 0x000e == 0x0006 */ - result = m_progflags ^= 0x0006; + // Probably some sort of frame start for DAC with external clock + // Denver Atlantis mwskinswants 0x2 to toggle + // Denver Durnago sf2049te wants 0x6 to toogle + result = (m_control_regs[PROG_FLAG_CONTROL_REG] & m_control_regs[PROG_FLAG_DATA_REG]) | (m_progflags & ~m_control_regs[PROG_FLAG_CONTROL_REG]); + m_progflags ^= 0x6; break; case IDMA_CONTROL_REG: @@ -1760,12 +1824,15 @@ READ16_MEMBER( dcs_audio_device::adsp_control_r ) result = m_control_regs[offset]; break; } + if (LOG_DCS_IO) + logerror("%04X: adsp_control_r(%06x) = %04X\n", space.device().safe_pc(), offset + 0x3fe0, result); return result; } WRITE16_MEMBER(dcs_audio_device:: adsp_control_w ) { + uint16_t data_change = data ^ m_control_regs[offset]; m_control_regs[offset] = data; switch (offset) @@ -1786,6 +1853,21 @@ WRITE16_MEMBER(dcs_audio_device:: adsp_control_w ) dmadac_enable(&m_dmadac[0], m_channels, 0); m_reg_timer->reset(); } + + // Check SPORT0 enabled + if (m_sport0_timer != nullptr) { + if (data & 0x1000) { + // Start the SPORT0 timer + // SPORT0 is used as a 1kHz timer + m_sport0_timer->adjust(attotime::from_hz(1000), 0, attotime::from_hz(1000)); + if (LOG_DCS_IO) + logerror("adsp_control_w: Setting SPORT0 freqency to 1kHz\n"); + } + else { + // Stop the SPORT0 timer + m_sport0_timer->reset(); + } + } break; case S1_AUTOBUF_REG: @@ -1833,6 +1915,8 @@ WRITE16_MEMBER(dcs_audio_device:: adsp_control_w ) downcast(m_cpu)->idma_addr_w(data); break; } + if (LOG_DCS_IO) + logerror("%04X: adsp_control_w(%06x) = %04X\n", space.device().safe_pc(), offset + 0x3fe0, data); } @@ -1844,6 +1928,8 @@ TIMER_DEVICE_CALLBACK_MEMBER( dcs_audio_device::dcs_irq ) { /* get the index register */ int reg = m_cpu->state_int(ADSP2100_I0 + m_ireg); + if (LOG_DCS_IO) + logerror("dcs_irq: m_size: %x m_incs: %x m_channels: %d m_ireg_base: %x reg: %06x\n", m_size, m_incs, m_channels, m_ireg_base, reg); /* copy the current data into the buffer */ { @@ -1863,20 +1949,24 @@ TIMER_DEVICE_CALLBACK_MEMBER( dcs_audio_device::dcs_irq ) } /* check for wrapping */ + m_ireg_base = m_cpu->get_ibase(m_ireg); if (reg >= m_ireg_base + m_size) { /* reset the base pointer */ reg = m_ireg_base; /* generate the (internal, thats why the pulse) irq */ + if (LOG_DCS_IO) + logerror("dcs_irq: Genrating interrupt\n"); m_cpu->machine().driver_data()->generic_pulse_irq_line(*m_cpu, ADSP2105_IRQ1, 1); } /* store it */ m_cpu->set_state_int(ADSP2100_I0 + m_ireg, reg); + if (LOG_DCS_IO) + logerror("dcs_irq end: m_size: %x m_incs: %x m_channels: %d m_ireg_base: %x reg: %06x\n", m_size, m_incs, m_channels, m_ireg_base, reg); } - TIMER_DEVICE_CALLBACK_MEMBER( dcs_audio_device::sport0_irq ) { /* this latches internally, so we just pulse */ @@ -1896,12 +1986,22 @@ void dcs_audio_device::recompute_sample_rate() /* calculate how long until we generate an interrupt */ /* frequency the time per each bit sent */ - attotime sample_period = attotime::from_hz(m_cpu->unscaled_clock()) * (2 * (m_control_regs[S1_SCLKDIV_REG] + 1)); + attotime sample_period; + if (m_control_regs[S1_CONTROL_REG] & 0x4000) { + // Use internal clock for SPORT1 Tx timing + sample_period = attotime::from_hz(m_cpu->unscaled_clock()) * (2 * (m_control_regs[S1_SCLKDIV_REG] + 1)); + /* now put it down to samples, so we know what the channel frequency has to be */ + sample_period *= (16 * m_channels); + } + else { + // Use external clock for SPORT1 Tx timing 31.25 KHz sample clock + sample_period = attotime::from_hz(31250); + } - /* now put it down to samples, so we know what the channel frequency has to be */ - sample_period = sample_period * (16 * m_channels); dmadac_set_frequency(&m_dmadac[0], m_channels, ATTOSECONDS_TO_HZ(sample_period.attoseconds())); dmadac_enable(&m_dmadac[0], m_channels, 1); + if (LOG_DCS_IO) + logerror("recompute_sample_rate: Channels: %d Freq: %e Size: 0x%x m_incs: 0x%x\n", m_channels, ATTOSECONDS_TO_HZ(sample_period.attoseconds()), m_size, m_incs); /* fire off a timer which will hit every half-buffer */ if (m_incs) @@ -1914,8 +2014,10 @@ void dcs_audio_device::recompute_sample_rate() WRITE32_MEMBER(dcs_audio_device::sound_tx_callback) { /* check if it's for SPORT1 */ - if (offset != 1) + if (offset != 1) { + logerror("sound_tx_callback: No code for offset %x\n", offset); return; + } /* check if SPORT1 is enabled */ if (m_control_regs[SYSCONTROL_REG] & 0x0800) /* bit 11 */ @@ -1939,7 +2041,9 @@ WRITE32_MEMBER(dcs_audio_device::sound_tx_callback) m_size = m_cpu->state_int(ADSP2100_L0 + lreg); /* get the base value, since we need to keep it around for wrapping */ - source -= m_incs; + //source -= m_incs; + // Just clear lower 4 bits of source since some DCS versions haven't incremented yet + source &= ~0xf; /* make it go back one so we dont lose the first sample */ m_cpu->set_state_int(ADSP2100_I0 + m_ireg, source); @@ -1947,6 +2051,8 @@ WRITE32_MEMBER(dcs_audio_device::sound_tx_callback) /* save it as it is now */ m_ireg_base = source; + if (LOG_DCS_IO) + logerror("sound_tx_callback: m_ireg_base: %x m_size: %x m_incs: %x \n", m_ireg_base, m_size, m_incs); /* recompute the sample rate and timer */ recompute_sample_rate(); return; @@ -1982,6 +2088,18 @@ WRITE16_MEMBER( dcs_audio_device::dcs_polling_w ) COMBINE_DATA(m_polling_base); } +READ32_MEMBER(dcs_audio_device::dcs_polling32_r) +{ + space.device().execute().eat_cycles(1000); + return *m_polling32_base; +} + +WRITE32_MEMBER(dcs_audio_device::dcs_polling32_w) +{ + m_polling_count = 0; + COMBINE_DATA(m_polling32_base); +} + /*************************************************************************** @@ -2297,7 +2415,7 @@ int dcs_audio_device::preprocess_write(uint16_t data) int result; /* if we're not DCS2, skip */ - if (m_sport_timer == nullptr) + if (m_sport0_timer == nullptr) return 0; /* state 0 - initialization phase */ @@ -2430,7 +2548,7 @@ MACHINE_CONFIG_MEMBER( dcs2_audio_device::add_mconfig_dcs2 ) MCFG_CPU_DATA_MAP(dcs2_2115_data_map) MCFG_TIMER_DEVICE_ADD("dcs_reg_timer", DEVICE_SELF, dcs_audio_device, dcs_irq) - MCFG_TIMER_DEVICE_ADD("dcs_sport_timer", DEVICE_SELF, dcs_audio_device, sport0_irq) + MCFG_TIMER_DEVICE_ADD("dcs_sport0_timer", DEVICE_SELF, dcs_audio_device, sport0_irq) MCFG_TIMER_DEVICE_ADD("dcs_int_timer", DEVICE_SELF, dcs_audio_device, internal_timer_callback) MCFG_TIMER_DEVICE_ADD("dcs_hle_timer", DEVICE_SELF, dcs_audio_device, transfer_watchdog_callback) @@ -2512,7 +2630,7 @@ MACHINE_CONFIG_MEMBER( dcs2_audio_dsio_device::device_add_mconfig ) MCFG_TIMER_DEVICE_ADD("dcs_reg_timer", DEVICE_SELF, dcs_audio_device, dcs_irq) MCFG_TIMER_DEVICE_ADD("dcs_int_timer", DEVICE_SELF, dcs_audio_device, internal_timer_callback) - MCFG_TIMER_DEVICE_ADD("dcs_sport_timer", DEVICE_SELF, dcs_audio_device, sport0_irq) // roadburn needs this to pass harware test + MCFG_TIMER_DEVICE_ADD("dcs_sport0_timer", DEVICE_SELF, dcs_audio_device, sport0_irq) // roadburn needs this to pass harware test MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") @@ -2553,7 +2671,7 @@ MACHINE_CONFIG_MEMBER( dcs2_audio_denver_device::device_add_mconfig ) MCFG_TIMER_DEVICE_ADD("dcs_reg_timer", DEVICE_SELF, dcs_audio_device, dcs_irq) MCFG_TIMER_DEVICE_ADD("dcs_int_timer", DEVICE_SELF, dcs_audio_device, internal_timer_callback) - MCFG_TIMER_DEVICE_ADD("dcs_sport_timer", DEVICE_SELF, dcs_audio_device, sport0_irq) // Atlantis driver waits for sport0 rx interrupts + MCFG_TIMER_DEVICE_ADD("dcs_sport0_timer", DEVICE_SELF, dcs_audio_device, sport0_irq) // Atlantis driver waits for sport0 rx interrupts MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") diff --git a/src/mame/audio/dcs.h b/src/mame/audio/dcs.h index 7c068779dba..afbf97a554f 100644 --- a/src/mame/audio/dcs.h +++ b/src/mame/audio/dcs.h @@ -49,6 +49,7 @@ public: DECLARE_READ32_MEMBER( dsio_idma_data_r ); void dmovlay_remap_memory(); WRITE32_MEMBER(dmovlay_callback); + void denver_postload(void); // non public void dcs_boot(); @@ -66,6 +67,7 @@ public: void dsio_reset(); DECLARE_READ16_MEMBER( dsio_r ); DECLARE_WRITE16_MEMBER( dsio_w ); + void denver_alloc_dmadac(void); void denver_reset(); DECLARE_READ16_MEMBER( denver_r ); DECLARE_WRITE16_MEMBER( denver_w ); @@ -96,6 +98,8 @@ public: WRITE32_MEMBER(sound_tx_callback); DECLARE_READ16_MEMBER( dcs_polling_r ); DECLARE_WRITE16_MEMBER( dcs_polling_w ); + DECLARE_READ32_MEMBER(dcs_polling32_r); + DECLARE_WRITE32_MEMBER(dcs_polling32_w); TIMER_DEVICE_CALLBACK_MEMBER( transfer_watchdog_callback ); TIMER_CALLBACK_MEMBER( s1_ack_callback2 ); TIMER_CALLBACK_MEMBER( s1_ack_callback1 ); @@ -149,14 +153,13 @@ protected: uint8_t m_rev; offs_t m_polling_offset; uint32_t m_polling_count; - /* sound output */ uint8_t m_channels; uint16_t m_size; uint16_t m_incs; dmadac_sound_device *m_dmadac[6]; timer_device *m_reg_timer; - timer_device *m_sport_timer; + timer_device *m_sport0_timer; timer_device *m_internal_timer; int32_t m_ireg; uint16_t m_ireg_base; @@ -205,6 +208,7 @@ protected: uint16_t *m_sram; uint16_t *m_polling_base; + uint32_t *m_polling32_base; uint32_t *m_internal_program_ram; uint32_t *m_external_program_ram; uint32_t *m_internal_data_ram; diff --git a/src/mame/drivers/atlantis.cpp b/src/mame/drivers/atlantis.cpp index 91c0a1371e8..d748836c8b8 100644 --- a/src/mame/drivers/atlantis.cpp +++ b/src/mame/drivers/atlantis.cpp @@ -17,13 +17,14 @@ * CMD 646U2 Ultra DMA IDE controller * M4T28-8R128H1 TimeKeeper RTC/CMOS * PLX PCI9050 Bus Target Interface Chip (interfaces ISA-style designs to PCI) - * Midway Zeus-series custom video - * Actiontec PM560LKI PCI Data/Fax Modem (PCI\VEN_11C1&DEV_0480&SUBSYS_04801668) - * TL16c552 dual UART - * ADSP-2181 based DCS2 audio (unclear which variant) - * Cirrus Logic CS4338 16 bit stereo audio serial DAC, PCB has space for 3 chips (6-channels), only 1 is populated - * Maxim MAX192 8 channel 10 bit serial ADC - * PIC16C57 (protection? serial #?) + * Midway ZeusII-series custom video + * Actiontec PM560LKI PCI Data/Fax Modem (PCI\VEN_11C1&DEV_0480&SUBSYS_04801668) + * TL16c552 dual UART + * ADSP-2181 based DCS2 audio (unclear which variant) + * ICS AV9110 Serially Programmable Frequency Generator. Programmed through ADSP FL0,FL1,FL2 pins. + * Cirrus Logic CS4338 16 bit stereo audio serial DAC, PCB has space for 3 chips (6-channels), only 1 is populated + * Maxim MAX192 8 channel 10 bit serial ADC + * PIC16C57 (protection? serial #?) * Quantum Fireball CX 6.4GB IDE HDD (C/H/S 13328/15/63) TODO: @@ -110,6 +111,7 @@ public: DECLARE_DRIVER_INIT(mwskins); virtual void machine_start() override; virtual void machine_reset() override; + virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; required_device m_maincpu; required_device m_screen; optional_device m_palette; @@ -122,6 +124,7 @@ public: required_device m_ide; required_device m_rtc; optional_ioport_array<8> m_io_analog; + emu_timer *m_adc_ready_timer; READ8_MEMBER(cmos_r); WRITE8_MEMBER(cmos_w); @@ -271,7 +274,6 @@ WRITE32_MEMBER(atlantis_state::board_ctrl_w) case IRQ_EN: // Zero bit will clear cause board_ctrl[CAUSE] &= data; - board_ctrl[STATUS] &= data; update_asic_irq(); if (LOG_IRQ) logerror("%s:board_ctrl_w write to IRQ_EN offset %04X = %08X & %08X bus offset = %08X\n", machine().describe_context(), newOffset, data, mem_mask, offset); @@ -292,7 +294,8 @@ WRITE32_MEMBER(atlantis_state::board_ctrl_w) case 0x90: digit = '9'; break; case 0x88: digit = 'A'; break; case 0x83: digit = 'B'; break; - case 0xa7: digit = 'C'; break; + case 0xc6: digit = 'C'; break; + case 0xa7: digit = 'c'; break; case 0xa1: digit = 'D'; break; case 0x86: digit = 'E'; break; case 0x87: digit = 'F'; break; @@ -594,14 +597,15 @@ WRITE16_MEMBER(atlantis_state::a2d_ctrl_w) int index = (data & A2D_CTRL_CHAN_MASK) >> A2D_CTRL_CHAN_SHIFT; m_a2d_data = (m_io_analog[index].read_safe(0)); if (board_ctrl[IRQ_EN] & (1 << A2D_IRQ_SHIFT)) { - board_ctrl[STATUS] |= (1 << A2D_IRQ_SHIFT); - update_asic_irq(); + // Set adc ready timer to fire + m_adc_ready_timer->adjust(attotime::from_usec(5)); } - logerror("a2d_ctrl_w: offset = %08x index = %d data = %04x\n", offset, index, data); + //logerror("a2d_ctrl_w: offset = %08x index = %d data = %04x\n", offset, index, data); } READ16_MEMBER(atlantis_state::a2d_data_r) { + // Clear interrupt if enabled if (board_ctrl[IRQ_EN] & (1 << A2D_IRQ_SHIFT)) { board_ctrl[STATUS] &= ~(1 << A2D_IRQ_SHIFT); update_asic_irq(); @@ -622,6 +626,9 @@ void atlantis_state::machine_start() /* set the fastest DRC options */ m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS); + // Allocate adc timer + m_adc_ready_timer = timer_alloc(0); + // Save states save_item(NAME(m_cmos_write_enabled)); save_item(NAME(m_serial_count)); @@ -633,8 +640,6 @@ void atlantis_state::machine_start() } - - /************************************* * Machine init *************************************/ @@ -647,6 +652,17 @@ void atlantis_state::machine_reset() m_serial_count = 0; m_irq_state = 0; memset(board_ctrl, 0, sizeof(board_ctrl)); + m_adc_ready_timer->reset(); +} + +/************************************* +* Timer +*************************************/ +void atlantis_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) +{ + // ADC Ready Timer + board_ctrl[STATUS] |= (1 << A2D_IRQ_SHIFT); + update_asic_irq(); } /************************************* @@ -825,8 +841,7 @@ static MACHINE_CONFIG_START( mwskins ) //MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DSIO, 0) MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DENVER, 0) MCFG_DCS2_AUDIO_DRAM_IN_MB(8) - //MCFG_DCS2_AUDIO_POLLING_OFFSET(0) /* no place to hook :-( */ - //MCFG_DCS2_AUDIO_DAC_EXT_FREQ(1000000.0) + MCFG_DCS2_AUDIO_POLLING_OFFSET(0x200d) MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0) MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_STANDARD) diff --git a/src/mame/drivers/vegas.cpp b/src/mame/drivers/vegas.cpp index 753b764f90e..50c95e2fdac 100644 --- a/src/mame/drivers/vegas.cpp +++ b/src/mame/drivers/vegas.cpp @@ -43,7 +43,9 @@ Sound FIFO empty | | IOASIC Summary | | | -------(0x0008)--->| |----------(0x04)--->| | | |__________| |__________| | - | + NSS/Hi-Link (0x08) | + A2D IRQ (0x02) | + SIO Watchdog (0x01) | +-------------------------------------------------------------------------------+ | | __________ __________ @@ -63,7 +65,6 @@ -------(0x0010)--->| | |__________| |__________| - *************************************************************************** PCB Summary: @@ -320,7 +321,8 @@ public: m_ethernet(*this, "ethernet"), m_dcs(*this, "dcs"), m_ioasic(*this, "ioasic"), - m_io_analog(*this, "AN.%u", 0) + m_io_analog(*this, "AN.%u", 0), + m_a2d_shift(0) { } required_device m_maincpu; @@ -330,7 +332,7 @@ public: required_device m_dcs; required_device m_ioasic; optional_ioport_array<8> m_io_analog; - + int m_a2d_shift; uint8_t m_vblank_state; uint8_t m_cpuio_data[4]; uint8_t m_sio_irq_clear; @@ -340,6 +342,7 @@ public: uint8_t m_pending_analog_read; uint8_t m_cmos_unlocked; uint8_t m_dcs_idma_cs; + uint32_t m_i40_data; DECLARE_WRITE_LINE_MEMBER(vblank_assert); DECLARE_DRIVER_INIT(gauntleg); @@ -358,7 +361,8 @@ public: void update_sio_irqs(); - + DECLARE_WRITE_LINE_MEMBER(vegas_state::watchdog_reset); + DECLARE_WRITE_LINE_MEMBER(vegas_state::watchdog_irq); DECLARE_WRITE32_MEMBER(timekeeper_w); DECLARE_READ32_MEMBER(timekeeper_r); void reset_sio(void); @@ -381,8 +385,12 @@ public: DECLARE_WRITE_LINE_MEMBER(ethernet_interrupt); DECLARE_WRITE_LINE_MEMBER(ioasic_irq); DECLARE_READ32_MEMBER(unknown_r); -}; + DECLARE_WRITE32_MEMBER(i40_w); + DECLARE_CUSTOM_INPUT_MEMBER(i40_r); + + std::string sioIRQString(uint8_t data); +}; /************************************* * @@ -421,6 +429,7 @@ void vegas_state::machine_start() save_item(NAME(m_sio_led_state)); save_item(NAME(m_pending_analog_read)); save_item(NAME(m_cmos_unlocked)); + save_item(NAME(m_i40_data)); } @@ -437,8 +446,37 @@ void vegas_state::machine_reset() memset(m_cpuio_data, 0, ARRAY_LENGTH(m_cpuio_data)); // Clear SIO registers reset_sio(); + m_i40_data = 0; } +/************************************* +* Watchdog interrupts +*************************************/ +WRITE_LINE_MEMBER(vegas_state::watchdog_irq) +{ + if (state && !(m_sio_irq_state & 0x01)) { + logerror("%s: vegas_state::watchdog_irq state = %i\n", machine().describe_context(), state); + m_sio_irq_state |= 0x01; + update_sio_irqs(); + } + else if (!state && (m_sio_irq_state & 0x01)) { + //logerror("%s: vegas_state::watchdog_irq state = %i\n", machine().describe_context(), state); + m_sio_irq_state &= ~0x01; + update_sio_irqs(); + } +} + +/************************************* +* Watchdog Reset +*************************************/ +WRITE_LINE_MEMBER(vegas_state::watchdog_reset) +{ + if (state) { + //printf("vegas_state::watchdog_reset!!!\n"); + logerror("vegas_state::watchdog_reset!!!\n"); + machine().schedule_soft_reset(); + } +} /************************************* * @@ -491,6 +529,15 @@ READ32_MEMBER( vegas_state::timekeeper_r ) * SIO interrupts * *************************************/ +std::string vegas_state::sioIRQString(uint8_t data) +{ + std::string sioBitDef[6] = { "SIO_WD", "A2D", "IOASIC", "NSS", "ETHER", "VSYNC" }; + std::string sioBitSel = ""; + for (int i = 0; i < 6; i++) + if (data & (1 << i)) sioBitSel += " " + sioBitDef[i]; + return sioBitSel; + +} void vegas_state::update_sio_irqs() { @@ -500,17 +547,26 @@ void vegas_state::update_sio_irqs() else { m_nile->pci_intr_c(CLEAR_LINE); } - //logerror("update_sio_irqs: m_sio_irq_state: %02x\n", m_sio_irq_state); + if (LOG_SIO) { + std::string sioEnable = sioIRQString(m_sio_irq_enable); + std::string sioState = sioIRQString(m_sio_irq_state); + logerror("update_sio_irqs: irq_enable: %02x %s irq_state: %02x %s\n", m_sio_irq_enable, sioEnable, m_sio_irq_state, sioState); + } } WRITE_LINE_MEMBER(vegas_state::vblank_assert) { + if (LOG_SIO) + logerror("vblank_assert: state: %d\n", state); if (!m_vblank_state && state) { m_sio_irq_state |= 0x20; update_sio_irqs(); } + else if (m_vblank_state && !state) { + m_sio_irq_state &= ~0x20; + } m_vblank_state = state; } @@ -556,14 +612,26 @@ READ8_MEMBER(vegas_state::sio_r) case 1: // Interrupt Enable result = m_sio_irq_enable; + if (LOG_SIO) { + std::string sioBitSel = sioIRQString(result); + logerror("%08X: sio_r: INTR ENABLE 0x%02x %s\n", machine().device("maincpu")->safe_pc(), result, sioBitSel); + } break; case 2: // Interrupt Cause result = m_sio_irq_state & m_sio_irq_enable; + if (LOG_SIO) { + std::string sioBitSel = sioIRQString(result); + logerror("%08X: sio_r: INTR CAUSE 0x%02x %s\n", machine().device("maincpu")->safe_pc(), result, sioBitSel); + } break; case 3: // Interrupt Status result = m_sio_irq_state; + if (LOG_SIO) { + std::string sioBitSel = sioIRQString(result); + logerror("%08X: sio_r: INTR STATUS 0x%02x %s\n", machine().device("maincpu")->safe_pc(), result, sioBitSel); + } break; case 4: // LED @@ -600,7 +668,7 @@ READ8_MEMBER(vegas_state::sio_r) break; } } - if (LOG_SIO) + if (LOG_SIO && index != 0x4) logerror("%08X: sio_r: offset: %08x index: %d result: %02X\n", machine().device("maincpu")->safe_pc(), offset, index, result); return result; } @@ -608,6 +676,7 @@ READ8_MEMBER(vegas_state::sio_r) WRITE8_MEMBER(vegas_state::sio_w) { + // Bit 0 of data is used to program the 6016 FPGA in programming mode (m_cpio_data[3](Bit 0)==0) if (m_cpuio_data[3] & 0x1) { int index = offset >> 12; switch (index) { @@ -615,21 +684,20 @@ WRITE8_MEMBER(vegas_state::sio_w) if (LOG_SIO) logerror("sio_w: Reset Control offset: %08x index: %d data: %02X\n", offset, index, data); // Reset Control: Bit 0=>Reset IOASIC, Bit 1=>Reset NSS Connection, Bit 2=>Reset SMC, Bit 3=>Reset VSYNC, Bit 4=>VSYNC Polarity - m_sio_irq_clear = data; - /* bit 0x01 seems to be used to reset the IOASIC */ + /* bit 0x01 is used to reset the IOASIC */ if (!(data & 0x01)) { m_ioasic->ioasic_reset(); m_dcs->reset_w(data & 0x01); } - - /* they toggle bit 0x08 low to reset the VBLANK */ + /* toggle bit 0x08 low to reset the VBLANK */ if (!(data & 0x08)) { m_sio_irq_state &= ~0x20; update_sio_irqs(); } + m_sio_irq_clear = data; break; case 1: // Interrupt Enable @@ -639,13 +707,18 @@ WRITE8_MEMBER(vegas_state::sio_w) // Bit 3 => NSS / Hi-Link // Bit 4 => Ethernet // Bit 5 => Vsync - if (LOG_SIO) - logerror("sio_w: Interrupt Enable offset: %08x index: %d data: %02X\n", offset, index, data); + if (LOG_SIO) { + std::string sioBitSel = sioIRQString(data); + logerror("sio_w: Interrupt Enable 0x%02x %s\n", data, sioBitSel); + //logerror("sio_w: Interrupt Enable offset: %08x index: %d data: %02X\n", offset, index, data); + } m_sio_irq_enable = data; update_sio_irqs(); break; case 4: // LED + if (LOG_SIO) + logerror("sio_w: LED offset: %08x index: %d data: %02X\n", offset, index, data); m_sio_led_state = data; break; case 6: @@ -654,11 +727,12 @@ WRITE8_MEMBER(vegas_state::sio_w) break; case 7: // Watchdog - space.device().execute().eat_cycles(100); + m_timekeeper->watchdog_write(space, offset, data); + if (LOG_SIO) + logerror("sio_w: Watchdog: %08x index: %d data: %02X\n", offset, index, data); + //space.device().execute().eat_cycles(100); break; } - if (LOG_SIO && index != 6) - logerror("sio_w: offset: %08x index: %d data: %02X\n", offset, index, data); } } @@ -674,24 +748,64 @@ WRITE8_MEMBER(vegas_state::cpu_io_w) // 1: PLD Config / Clock Gen // 2: PLD Status / Jammma Serial Sense // 3: System Reset Bit 0=>enable sio, Bit 1=>enable ide, Bit 2=>enable PCI - if (1 && offset != 0) - logerror("%08X:cpuio write to offset %X = %02X\n", machine().device("maincpu")->safe_pc(), offset, data); - if (offset < 4) - m_cpuio_data[offset] = data; - if (offset == 1) + m_cpuio_data[offset] = data; + switch (offset) { + case 0: + { + char digit = 'U'; + switch (data & 0xff) { + case 0xc0: digit = '0'; break; + case 0xf9: digit = '1'; break; + case 0xa4: digit = '2'; break; + case 0xb0: digit = '3'; break; + case 0x99: digit = '4'; break; + case 0x92: digit = '5'; break; + case 0x82: digit = '6'; break; + case 0xf8: digit = '7'; break; + case 0x80: digit = '8'; break; + case 0x90: digit = '9'; break; + case 0x88: digit = 'A'; break; + case 0x83: digit = 'B'; break; + case 0xc6: digit = 'C'; break; + case 0xa7: digit = 'c'; break; + case 0xa1: digit = 'D'; break; + case 0x86: digit = 'E'; break; + case 0x87: digit = 'F'; break; + case 0x7f: digit = '.'; break; + case 0xf7: digit = '_'; break; + case 0xbf: digit = '|'; break; + case 0xfe: digit = '-'; break; + case 0xff: digit = 'Z'; break; + } + if (LOG_SIO) { + popmessage("System LED: %C", digit); + logerror("%08X: cpu_io_w System LED offset %X = %02X '%c'\n", machine().device("maincpu")->safe_pc(), offset, data, digit); + } + } + break; + case 1: m_cpuio_data[2] = (m_cpuio_data[2] & ~0x02) | ((m_cpuio_data[1] & 0x01) << 1) | (m_cpuio_data[1] & 0x01); - if (offset == 1) { if (!(data & 0x1)) { // Need to clear this register while programming SIO FPGA so that fpga config data doesn't register in sio_w m_cpuio_data[3] &= ~0x1; // Reset the SIO registers reset_sio(); } - } - if (offset == 3) { - if (!(data & 0x2)) { - // Reset IDE - } + if (LOG_SIO) + logerror("%08X: cpu_io_w PLD Config offset %X = %02X\n", machine().device("maincpu")->safe_pc(), offset, data); + break; + case 2: + if (LOG_SIO && (m_cpuio_data[3] & 0x1)) + logerror("%08X: cpu_io_w PLD Status / Jamma Serial Sense offset %X = %02X\n", machine().device("maincpu")->safe_pc(), offset, data); + break; + case 3: + // Bit 0: Enable SIO, Bit 1: Enable SIO_R0/IDE, Bit 2: Enable PCI + if (LOG_SIO) + logerror("%08X: cpu_io_w System Reset offset %X = %02X\n", machine().device("maincpu")->safe_pc(), offset, data); + break; + default: + logerror("%08X: cpu_io_w unknown offset %X = %02X\n", machine().device("maincpu")->safe_pc(), offset, data); + break; } } @@ -700,8 +814,8 @@ READ8_MEMBER( vegas_state::cpu_io_r ) uint32_t result = 0; if (offset < 4) result = m_cpuio_data[offset]; - if (LOG_SIO && offset != 2) - logerror("%08X:cpuio read from offset %X = %02X\n", machine().device("maincpu")->safe_pc(), offset, result); + if (LOG_SIO && !(offset == 2 && !(m_cpuio_data[3] & 0x1))) + logerror("%08X:cpu_io_r offset %X = %02X\n", machine().device("maincpu")->safe_pc(), offset, result); return result; } @@ -715,15 +829,28 @@ READ8_MEMBER( vegas_state::cpu_io_r ) READ32_MEMBER( vegas_state::analog_port_r ) { - return m_pending_analog_read; + //logerror("%08X: analog_port_r = %08X & %08X\n", machine().device("maincpu")->safe_pc(), m_pending_analog_read, mem_mask); + // Clear interrupt + if (m_sio_irq_enable & 0x02) { + m_sio_irq_state &= ~0x02; + update_sio_irqs(); + } + // TODO: Need to look at the proper shift value for sf2049 + return m_pending_analog_read << (m_a2d_shift << 0); } WRITE32_MEMBER( vegas_state::analog_port_w ) { - if (data < 8 || data > 15) - logerror("%08X:Unexpected analog port select = %08X\n", safe_pc(), data); - m_pending_analog_read = m_io_analog[data & 7].read_safe(0); + uint32_t shift_data = data >> m_a2d_shift; + int index = shift_data & 0x7; + m_pending_analog_read = (m_io_analog[index].read_safe(0)); + //logerror("%08X: analog_port_w = %08X & %08X index = %d\n", machine().device("maincpu")->safe_pc(), data, mem_mask, index); + if (m_sio_irq_enable & 0x02) { + m_sio_irq_state |= 0x02; + update_sio_irqs(); + } + } @@ -746,6 +873,7 @@ READ32_MEMBER( vegas_state::ethernet_r ) result |= m_ethernet->read(space, offset * 2 + 0, mem_mask); if (ACCESSING_BITS_16_31) result |= m_ethernet->read(space, offset * 2 + 1, mem_mask >> 16) << 16; + logerror("ethernet_r: offset %08x = %08x\n", offset, result); return result; } @@ -756,6 +884,7 @@ WRITE32_MEMBER( vegas_state::ethernet_w ) m_ethernet->write(space, offset * 2 + 0, data, mem_mask); if (ACCESSING_BITS_16_31) m_ethernet->write(space, offset * 2 + 1, data >> 16, mem_mask >> 16); + logerror("ethernet_w: offset %08x = %08x & %08x\n", offset, data, mem_mask); } @@ -772,6 +901,61 @@ READ32_MEMBER(vegas_state::unknown_r) return result; } +/************************************* +* Optical 49 Way Joystick I40 Board +*************************************/ +WRITE32_MEMBER(vegas_state::i40_w) +{ + //printf("i40_w: data = %08x\n", data); + //logerror("i40_w: data = %08x\n", data); + m_i40_data = data; +} + +CUSTOM_INPUT_MEMBER(vegas_state::i40_r) +{ + static const uint8_t translate49[7] = { 0x8, 0xc, 0xe, 0xf, 0x3, 0x1, 0x0 }; + int index = m_i40_data & 0xf; + uint8_t data = 0; + switch (index) { + case 0: + data = translate49[ioport("49WAYX_P1")->read() >> 4]; + break; + case 1: + data = translate49[ioport("49WAYY_P1")->read() >> 4]; + break; + case 2: + data = translate49[ioport("49WAYX_P2")->read() >> 4]; + break; + case 3: + data = translate49[ioport("49WAYY_P2")->read() >> 4]; + break; + case 4: + data = translate49[ioport("49WAYX_P3")->read() >> 4]; + break; + case 5: + data = translate49[ioport("49WAYY_P3")->read() >> 4]; + break; + case 6: + data = translate49[ioport("49WAYX_P4")->read() >> 4]; + break; + case 7: + data = translate49[ioport("49WAYY_P4")->read() >> 4]; + break; + case 10: + case 11: + case 12: + // I40 Detection + data = ~index & 0xf; + break; + default: + break; + } + //if (m_i40_data & 0x1000) + // printf("%08X: i40_r: select: %x index: %d data: %x\n", machine().device("maincpu")->safe_pc(), m_i40_data, index, data); + //m_i40_data &= ~0x1000; + return data; +} + /************************************* * * Input ports @@ -881,6 +1065,16 @@ static INPUT_PORTS_START( vegas_common ) PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4) PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4) PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED ) + + PORT_START("AN.0") PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("AN.1") PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("AN.2") PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("AN.3") PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("AN.4") PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("AN.5") PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("AN.6") PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("AN.7") PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + INPUT_PORTS_END @@ -994,7 +1188,7 @@ static INPUT_PORTS_START( warfa ) PORT_DIPSETTING( 0x4000, "Medium Res 512x384" ) PORT_DIPSETTING( 0x0000, "VGA Res 640x480" ) - PORT_MODIFY("IN1") + PORT_MODIFY("IN1") PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_CODE(KEYCODE_J) PORT_NAME("Trigger") PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_CODE(KEYCODE_K) PORT_NAME("Discard") PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_CODE(KEYCODE_L) PORT_NAME("Jump") @@ -1004,29 +1198,12 @@ static INPUT_PORTS_START( warfa ) PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_CODE(KEYCODE_A) PORT_NAME("Dodge Left") PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_CODE(KEYCODE_D) PORT_NAME("Dodge Right") - PORT_START("AN.0") + PORT_MODIFY("AN.0") PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) - PORT_START("AN.1") + PORT_MODIFY("AN.1") PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) - PORT_START("AN.2") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.3") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.4") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.5") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.6") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.7") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) INPUT_PORTS_END @@ -1048,29 +1225,15 @@ static INPUT_PORTS_START( roadburn ) PORT_DIPSETTING( 0x0200, "Medium Res 512x384" ) PORT_DIPSETTING( 0x0000, "VGA Res 640x480" ) - PORT_START("AN.0") /* Accel */ + PORT_MODIFY("AN.0") /* Accel */ PORT_BIT( 0xff, 0x80, IPT_PEDAL ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(100) PORT_KEYDELTA(20) - PORT_START("AN.1") /* Steer */ + PORT_MODIFY("AN.1") /* Steer */ PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) - PORT_START("AN.2") /* Brake */ + PORT_MODIFY("AN.2") /* Seat Tilt */ PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) - PORT_START("AN.3") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.4") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.5") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.6") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.7") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) INPUT_PORTS_END @@ -1083,39 +1246,30 @@ static INPUT_PORTS_START( nbashowt ) PORT_DIPSETTING( 0x0000, "CMOS" ) PORT_DIPNAME( 0x000e, 0x000e, DEF_STR( Coinage ) ) PORT_DIPSETTING( 0x000e, "Mode 1" ) - PORT_DIPSETTING( 0x0008, "Mode 2" ) - PORT_DIPSETTING( 0x0009, "Mode 3" ) - PORT_DIPSETTING( 0x0002, "Mode 4" ) - PORT_DIPSETTING( 0x000c, "Mode ECA" ) -// PORT_DIPSETTING( 0x0004, "Not Used 1" ) /* Marked as Unused in the manual */ -// PORT_DIPSETTING( 0x0008, "Not Used 2" ) /* Marked as Unused in the manual */ + PORT_DIPSETTING( 0x000c, "Mode 2" ) + PORT_DIPSETTING( 0x000a, "Mode 3" ) + PORT_DIPSETTING( 0x0008, "Mode 4" ) + PORT_DIPSETTING( 0x0006, "Mode 5") + PORT_DIPSETTING( 0x0004, "Mode 6") + PORT_DIPSETTING( 0x0002, "Mode 7") PORT_DIPSETTING( 0x0000, DEF_STR( Free_Play ) ) PORT_DIPNAME( 0x0030, 0x0030, "Curency Type" ) PORT_DIPSETTING( 0x0030, DEF_STR( USA ) ) PORT_DIPSETTING( 0x0020, DEF_STR( French ) ) PORT_DIPSETTING( 0x0010, DEF_STR( German ) ) -// PORT_DIPSETTING( 0x0000, "Not Used" ) /* Marked as Unused in the manual */ PORT_DIPSETTING( 0x0000, DEF_STR( Free_Play ) ) - PORT_DIPNAME( 0x0040, 0x0000, DEF_STR( Unknown ) ) /* Marked as Unused in the manual */ - PORT_DIPSETTING( 0x0040, "0" ) - PORT_DIPSETTING( 0x0000, "1" ) - PORT_DIPNAME( 0x0080, 0x0080, "Game" ) + PORT_DIPUNUSED( 0x0040, 0x0040 ) + PORT_DIPNAME( 0x0080, 0x0080, "Game Powerup" ) PORT_DIPSETTING( 0x0080, "NBA Showtime" ) - PORT_DIPSETTING( 0x0000, "Blitz 99" ) + PORT_DIPSETTING( 0x0000, "NFL Blitz" ) PORT_DIPNAME( 0x0100, 0x0100, "Joysticks" ) PORT_DIPSETTING( 0x0100, "8-Way" ) PORT_DIPSETTING( 0x0000, "49-Way" ) - PORT_DIPNAME( 0x0600, 0x0200, "Graphics Mode" ) - PORT_DIPSETTING( 0x0200, "512x385 @ 25KHz" ) - PORT_DIPSETTING( 0x0400, "512x256 @ 15KHz" ) -// PORT_DIPSETTING( 0x0600, "0" ) /* Marked as Unused in the manual */ -// PORT_DIPSETTING( 0x0000, "3" ) /* Marked as Unused in the manual */ - PORT_DIPNAME( 0x1800, 0x1800, "Graphics Speed" ) - PORT_DIPSETTING( 0x0000, "45 MHz" ) - PORT_DIPSETTING( 0x0800, "47 MHz" ) - PORT_DIPSETTING( 0x1000, "49 MHz" ) - PORT_DIPSETTING( 0x1800, "51 MHz" ) - PORT_DIPNAME( 0x2000, 0x0000, "Number of Players" ) + PORT_DIPNAME( 0x0200, 0x0200, "Graphics Mode" ) + PORT_DIPSETTING( 0x0200, "Med Res" ) + PORT_DIPSETTING( 0x0000, "Low Res" ) + PORT_DIPUNUSED( 0x01c00, 0x01c00 ) + PORT_DIPNAME( 0x2000, 0x2000, "Number of Players" ) PORT_DIPSETTING( 0x2000, "2" ) PORT_DIPSETTING( 0x0000, "4" ) PORT_DIPNAME( 0x4000, 0x0000, "Power On Self Test" ) @@ -1124,111 +1278,107 @@ static INPUT_PORTS_START( nbashowt ) PORT_DIPNAME( 0x8000, 0x8000, "Test Switch" ) PORT_DIPSETTING( 0x8000, DEF_STR( Off ) ) PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) -INPUT_PORTS_END - - -static INPUT_PORTS_START( sf2049 ) - PORT_INCLUDE(vegas_common) - - PORT_MODIFY("DIPS") - PORT_DIPNAME( 0x0003, 0x0003, "Test Mode" ) - PORT_DIPSETTING( 0x0003, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x0002, "Disk-based Test" ) - PORT_DIPSETTING( 0x0001, "EPROM-based Test" ) - PORT_DIPSETTING( 0x0000, "Interactive Diagnostics" ) - PORT_DIPNAME( 0x0080, 0x0080, "PM Dump" ) - PORT_DIPSETTING( 0x0080, "Watchdog resets only" ) - PORT_DIPSETTING( 0x0000, "All resets" ) - PORT_DIPNAME( 0x0100, 0x0200, "Resolution" ) - PORT_DIPSETTING( 0x0000, "Standard Res 512x256" ) - PORT_DIPSETTING( 0x0200, "Medium Res 512x384" ) - PORT_DIPSETTING( 0x0300, "VGA Res 640x480" ) - - PORT_START("AN.0") /* Steer */ - PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(0x10, 0xf0) PORT_SENSITIVITY(25) PORT_KEYDELTA(5) - - PORT_START("AN.1") /* Accel */ - PORT_BIT( 0xff, 0x80, IPT_PEDAL ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(20) - - PORT_START("AN.2") /* Brake */ - PORT_BIT( 0xff, 0x80, IPT_PEDAL2 ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(100) - - PORT_START("AN.3") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.4") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.5") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.6") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.7") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) -INPUT_PORTS_END + PORT_MODIFY("IN1") + PORT_BIT( 0x000f, IP_ACTIVE_LOW, IPT_UNUSED) // P1 Joystick + PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) + PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) + PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) + PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED ) + PORT_BIT( 0x0f00, IP_ACTIVE_LOW, IPT_UNUSED) // P2 Joystick + PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) + PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) + PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) + PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED ) -static INPUT_PORTS_START( sf2049se ) - PORT_INCLUDE(vegas_common) + PORT_MODIFY("IN2") + PORT_BIT( 0x000f, IP_ACTIVE_LOW, IPT_UNUSED) // P3 Joystick + PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3) + PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3) + PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3) + PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED ) + PORT_BIT( 0x0f00, IP_ACTIVE_LOW, IPT_SPECIAL) PORT_CUSTOM_MEMBER(DEVICE_SELF, vegas_state, i40_r, nullptr) + PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4) + PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4) + PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4) + PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED ) - PORT_MODIFY("DIPS") + PORT_START("49WAYX_P1") + PORT_BIT( 0xff, 0x38, IPT_AD_STICK_X ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) - PORT_START("AN.0") /* Steer */ - PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(0x10, 0xf0) PORT_SENSITIVITY(25) PORT_KEYDELTA(5) + PORT_START("49WAYY_P1") + PORT_BIT( 0xff, 0x38, IPT_AD_STICK_Y ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) - PORT_START("AN.1") /* Accel */ - PORT_BIT( 0xff, 0x80, IPT_PEDAL ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(20) + PORT_START("49WAYX_P2") + PORT_BIT(0xff, 0x38, IPT_AD_STICK_X) PORT_MINMAX(0x00, 0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2) - PORT_START("AN.2") /* Brake */ - PORT_BIT( 0xff, 0x80, IPT_PEDAL2 ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(100) + PORT_START("49WAYY_P2") + PORT_BIT(0xff, 0x38, IPT_AD_STICK_Y) PORT_MINMAX(0x00, 0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2) - PORT_START("AN.3") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("49WAYX_P3") + PORT_BIT(0xff, 0x38, IPT_AD_STICK_X) PORT_MINMAX(0x00, 0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(3) - PORT_START("AN.4") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("49WAYY_P3") + PORT_BIT(0xff, 0x38, IPT_AD_STICK_Y) PORT_MINMAX(0x00, 0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(3) - PORT_START("AN.5") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("49WAYX_P4") + PORT_BIT(0xff, 0x38, IPT_AD_STICK_X) PORT_MINMAX(0x00, 0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(4) - PORT_START("AN.6") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_START("49WAYY_P4") + PORT_BIT(0xff, 0x38, IPT_AD_STICK_Y) PORT_MINMAX(0x00, 0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(4) - PORT_START("AN.7") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) INPUT_PORTS_END -static INPUT_PORTS_START( sf2049te ) +static INPUT_PORTS_START( sf2049 ) PORT_INCLUDE(vegas_common) PORT_MODIFY("DIPS") + PORT_DIPNAME( 0x0003, 0x0003, "Test Mode" ) + PORT_DIPSETTING( 0x0003, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0002, "Disk-based Test" ) + PORT_DIPSETTING( 0x0001, "EPROM-based Test" ) + PORT_DIPSETTING( 0x0000, "Interactive Diagnostics" ) + PORT_DIPNAME( 0x0080, 0x0080, "PM Dump" ) + PORT_DIPSETTING( 0x0080, "Watchdog resets only" ) + PORT_DIPSETTING( 0x0000, "All resets" ) + PORT_DIPNAME( 0x0300, 0x0200, "Resolution" ) + PORT_DIPSETTING( 0x0300, "Standard Res 512x256" ) + PORT_DIPSETTING( 0x0200, "Medium Res 512x384" ) + PORT_DIPSETTING( 0x0000, "VGA Res 640x480" ) - PORT_START("AN.0") /* Steer */ - PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(0x10, 0xf0) PORT_SENSITIVITY(25) PORT_KEYDELTA(5) - - PORT_START("AN.1") /* Accel */ - PORT_BIT( 0xff, 0x80, IPT_PEDAL ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(20) - - PORT_START("AN.2") /* Brake */ - PORT_BIT( 0xff, 0x80, IPT_PEDAL2 ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(100) + PORT_MODIFY("SYSTEM") + PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_START2 ) // Gear Reverse - PORT_START("AN.3") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_MODIFY("IN1") + PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1) PORT_8WAY + PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1) PORT_8WAY + PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1) PORT_8WAY + PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1) PORT_8WAY + PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) + PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) + PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) + PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED ) + PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(2) // Gear 1 + PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) // Gear 2 + PORT_BIT( 0x0400, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2) // Gear 3 + PORT_BIT( 0x0800, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2) // Gear 4 + PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) + PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) + PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) + PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED ) - PORT_START("AN.4") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_MODIFY("AN.2") /* Accel */ + PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(100) - PORT_START("AN.5") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_MODIFY("AN.3") /* Clutch */ + PORT_BIT( 0xff, 0x00, IPT_PEDAL3 ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(20) - PORT_START("AN.6") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_MODIFY("AN.6") /* Brake */ + PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(20) - PORT_START("AN.7") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) + PORT_MODIFY("AN.7") /* Steer */ + PORT_BIT(0xff, 0x80, IPT_PADDLE) PORT_MINMAX(0x10, 0xf0) PORT_SENSITIVITY(25) PORT_KEYDELTA(5) INPUT_PORTS_END @@ -1237,29 +1387,15 @@ static INPUT_PORTS_START( cartfury ) PORT_MODIFY("DIPS") - PORT_START("AN.0") /* Steer */ + PORT_MODIFY("AN.0") /* Steer */ PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(0x10, 0xf0) PORT_SENSITIVITY(25) PORT_KEYDELTA(5) - PORT_START("AN.1") /* Accel */ + PORT_MODIFY("AN.1") /* Accel */ PORT_BIT( 0xff, 0x80, IPT_PEDAL ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(20) - PORT_START("AN.2") /* Brake */ + PORT_MODIFY("AN.2") /* Brake */ PORT_BIT( 0xff, 0x80, IPT_PEDAL2 ) PORT_MINMAX(0x00, 0xff) PORT_SENSITIVITY(25) PORT_KEYDELTA(100) - PORT_START("AN.3") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.4") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.5") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.6") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) - - PORT_START("AN.7") - PORT_BIT( 0xff, 0x80, IPT_SPECIAL ) INPUT_PORTS_END /************************************* @@ -1337,6 +1473,8 @@ static MACHINE_CONFIG_START( vegascore ) MCFG_VOODOO_VBLANK_CB(DEVWRITELINE(":", vegas_state, vblank_assert)) MCFG_M48T37_ADD("timekeeper") + MCFG_M48T37_RESET_HANDLER(WRITELINE(vegas_state, watchdog_reset)) + MCFG_M48T37_IRQ_HANDLER(WRITELINE(vegas_state, watchdog_irq)) MCFG_SMC91C94_ADD("ethernet") MCFG_SMC91C94_IRQ_CALLBACK(WRITELINE(vegas_state, ethernet_interrupt)) @@ -1466,7 +1604,7 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( roadburn, vegas32m ) MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DSIO, 0) MCFG_DCS2_AUDIO_DRAM_IN_MB(4) - MCFG_DCS2_AUDIO_POLLING_OFFSET(0) /* no place to hook :-( */ + MCFG_DCS2_AUDIO_POLLING_OFFSET(0x200a) MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0) MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_STANDARD) @@ -1482,10 +1620,12 @@ static MACHINE_CONFIG_DERIVED( nbashowt, vegasban ) MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0) MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_MACE) - MCFG_MIDWAY_IOASIC_UPPER(528/* or 478 or 487 */) + // 528 494 478 development pic, 487 NBA + MCFG_MIDWAY_IOASIC_UPPER(487/* or 478 or 487 */) MCFG_MIDWAY_IOASIC_YEAR_OFFS(80) MCFG_MIDWAY_IOASIC_IRQ_CALLBACK(WRITELINE(vegas_state, ioasic_irq)) - MCFG_MIDWAY_IOASIC_AUTO_ACK(1) + //MCFG_MIDWAY_IOASIC_AUTO_ACK(1) + MCFG_MIDWAY_IOASIC_AUX_OUT_CB(WRITE32(vegas_state, i40_w)) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( nbanfl, vegasban ) @@ -1497,7 +1637,7 @@ static MACHINE_CONFIG_DERIVED( nbanfl, vegasban ) MCFG_MIDWAY_IOASIC_UPPER(498/* or 478 or 487 */) MCFG_MIDWAY_IOASIC_YEAR_OFFS(80) MCFG_MIDWAY_IOASIC_IRQ_CALLBACK(WRITELINE(vegas_state, ioasic_irq)) - MCFG_MIDWAY_IOASIC_AUTO_ACK(1) + //MCFG_MIDWAY_IOASIC_AUTO_ACK(1) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( nbagold, vegasban) @@ -1506,15 +1646,16 @@ static MACHINE_CONFIG_DERIVED( nbagold, vegasban) MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0) MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_GAUNTDL) - MCFG_MIDWAY_IOASIC_UPPER(494 /* ??? */) + MCFG_MIDWAY_IOASIC_UPPER( 494 /* 494 ??? */) MCFG_MIDWAY_IOASIC_YEAR_OFFS(80) MCFG_MIDWAY_IOASIC_IRQ_CALLBACK(WRITELINE(vegas_state, ioasic_irq)) - MCFG_MIDWAY_IOASIC_AUTO_ACK(1) + //MCFG_MIDWAY_IOASIC_AUTO_ACK(1) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( sf2049 , denver ) MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DENVER, 0) - MCFG_DCS2_AUDIO_DRAM_IN_MB(8) + MCFG_DCS2_AUDIO_DRAM_IN_MB(16) + MCFG_DCS2_AUDIO_POLLING_OFFSET(0x200d) MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0) MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_STANDARD) @@ -1526,7 +1667,7 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( sf2049se, denver ) MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DENVER, 0) - MCFG_DCS2_AUDIO_DRAM_IN_MB(8) + MCFG_DCS2_AUDIO_DRAM_IN_MB(16) MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0) MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_SFRUSHRK) @@ -1538,7 +1679,7 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( sf2049te, denver ) MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DENVER, 0) - MCFG_DCS2_AUDIO_DRAM_IN_MB(8) + MCFG_DCS2_AUDIO_DRAM_IN_MB(16) MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0) MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_SFRUSHRK) @@ -1554,7 +1695,7 @@ static MACHINE_CONFIG_DERIVED( cartfury, vegasv3 ) MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0) MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_CARNEVIL) - MCFG_MIDWAY_IOASIC_UPPER(495/* others? */) + MCFG_MIDWAY_IOASIC_UPPER(433/* 495 others? */) MCFG_MIDWAY_IOASIC_YEAR_OFFS(80) MCFG_MIDWAY_IOASIC_IRQ_CALLBACK(WRITELINE(vegas_state, ioasic_irq)) MCFG_MIDWAY_IOASIC_AUTO_ACK(1) @@ -1914,16 +2055,19 @@ DRIVER_INIT_MEMBER(vegas_state,nbanfl) DRIVER_INIT_MEMBER(vegas_state,sf2049) { + m_a2d_shift = 4; } DRIVER_INIT_MEMBER(vegas_state,sf2049se) { + m_a2d_shift = 4; } DRIVER_INIT_MEMBER(vegas_state,sf2049te) { + m_a2d_shift = 4; } @@ -1965,8 +2109,8 @@ GAME( 2000, nbagold , 0, nbagold, nbashowt, vegas_state, nbanfl, ROT /* Durango + Denver SIO + Voodoo 3 */ GAME( 1998, sf2049, 0, sf2049, sf2049, vegas_state, sf2049, ROT0, "Atari Games", "San Francisco Rush 2049", MACHINE_NO_SOUND | MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) -GAME( 1998, sf2049se, sf2049, sf2049se, sf2049se, vegas_state, sf2049se, ROT0, "Atari Games", "San Francisco Rush 2049: Special Edition", MACHINE_NO_SOUND | MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) -GAME( 1998, sf2049te, sf2049, sf2049te, sf2049te, vegas_state, sf2049te, ROT0, "Atari Games", "San Francisco Rush 2049: Tournament Edition", MACHINE_NO_SOUND | MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE) +GAME( 1998, sf2049se, sf2049, sf2049se, sf2049, vegas_state, sf2049se, ROT0, "Atari Games", "San Francisco Rush 2049: Special Edition", MACHINE_NO_SOUND | MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) +GAME( 1998, sf2049te, sf2049, sf2049te, sf2049, vegas_state, sf2049te, ROT0, "Atari Games", "San Francisco Rush 2049: Tournament Edition", MACHINE_NO_SOUND | MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE) /* Durango + Vegas SIO + Voodoo 3 */ GAME( 2000, cartfury, 0, cartfury, cartfury, vegas_state, cartfury, ROT0, "Midway Games", "Cart Fury", MACHINE_NO_SOUND | MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE ) -- cgit v1.2.3