From 530bced66c51a000e45346ebd0f0567f49baa5ae Mon Sep 17 00:00:00 2001 From: mooglyguy Date: Tue, 4 Jun 2019 04:57:35 +0200 Subject: -dpb7000: Main screen turn on. [Ryan Holtz, Mark Nias] * Hooked up CSR, control bus, and system control registers. * Hooked up Auto-Start switch and both banks of config switches. * Hooked up CRTC chargen, using the chargen ROM from bw12 until a proper dump of the DPB's chargen ROM is available. When Auto-Start is enabled, prints a greeting string to the VDU and then sits in a tight loop waiting for a REQ B interrupt, most likely from the Disk Sequence Card. (nw) --- src/mame/drivers/dpb7000.cpp | 234 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 230 insertions(+), 4 deletions(-) diff --git a/src/mame/drivers/dpb7000.cpp b/src/mame/drivers/dpb7000.cpp index 4e6fdbed0f0..a326544cd40 100644 --- a/src/mame/drivers/dpb7000.cpp +++ b/src/mame/drivers/dpb7000.cpp @@ -15,6 +15,7 @@ #include "machine/com8116.h" #include "machine/input_merger.h" #include "video/mc6845.h" +#include "emupal.h" #include "screen.h" class dpb7000_state : public driver_device @@ -28,7 +29,13 @@ public: , m_brg(*this, "brg") , m_rs232(*this, "rs232") , m_crtc(*this, "crtc") + , m_palette(*this, "palette") + , m_vdu_ram(*this, "vduram") + , m_vdu_char_rom(*this, "vduchar") , m_baud_dip(*this, "BAUD") + , m_auto_start(*this, "AUTOSTART") + , m_config_sw12(*this, "CONFIGSW12") + , m_config_sw34(*this, "CONFIGSW34") { } @@ -42,6 +49,24 @@ private: DECLARE_READ16_MEMBER(bus_error_r); DECLARE_WRITE16_MEMBER(bus_error_w); + + DECLARE_WRITE8_MEMBER(csr_w); + + DECLARE_READ16_MEMBER(cpu_ctrlbus_r); + DECLARE_WRITE16_MEMBER(cpu_ctrlbus_w); + + enum : uint16_t + { + SYSCTRL_AUTO_START = 0x0001, + SYSCTRL_REQ_B_OUT = 0x0020, + SYSCTRL_REQ_A_OUT = 0x0040, + SYSCTRL_REQ_A_IN = 0x0080, + SYSCTRL_REQ_B_IN = 0x8000 + }; + + DECLARE_READ16_MEMBER(cpu_sysctrl_r); + DECLARE_WRITE16_MEMBER(cpu_sysctrl_w); + MC6845_UPDATE_ROW(crtc_update_row); MC6845_ON_UPDATE_ADDR_CHANGED(crtc_addr_changed); @@ -51,18 +76,31 @@ private: required_device m_brg; required_device m_rs232; required_device m_crtc; + required_device m_palette; + required_shared_ptr m_vdu_ram; + required_memory_region m_vdu_char_rom; required_ioport m_baud_dip; + required_ioport m_auto_start; + required_ioport m_config_sw12; + required_ioport m_config_sw34; + + uint8_t m_csr; + uint16_t m_sys_ctrl; }; void dpb7000_state::main_map(address_map &map) { map(0x000000, 0x07ffff).rom().region("monitor", 0); map(0xb00000, 0xb7ffff).rw(FUNC(dpb7000_state::bus_error_r), FUNC(dpb7000_state::bus_error_w)); - map(0xb80000, 0xbfffff).ram(); // NB: There's probably more RAM than this. + map(0xb80000, 0xbfffff).ram(); + map(0xffe000, 0xffefff).ram().share("vduram").umask16(0x00ff); map(0xfff801, 0xfff801).rw(m_crtc, FUNC(sy6545_1_device::status_r), FUNC(sy6545_1_device::address_w)).cswidth(16); map(0xfff803, 0xfff803).rw(m_crtc, FUNC(sy6545_1_device::register_r), FUNC(sy6545_1_device::register_w)).cswidth(16); map(0xfff805, 0xfff805).rw(m_acia[0], FUNC(acia6850_device::status_r), FUNC(acia6850_device::control_w)).cswidth(16); map(0xfff807, 0xfff807).rw(m_acia[0], FUNC(acia6850_device::data_r), FUNC(acia6850_device::data_w)).cswidth(16); + map(0xfff809, 0xfff809).w(FUNC(dpb7000_state::csr_w)).cswidth(16); + map(0xfff80a, 0xfff80b).rw(FUNC(dpb7000_state::cpu_ctrlbus_r), FUNC(dpb7000_state::cpu_ctrlbus_w)); + map(0xfff80c, 0xfff80d).rw(FUNC(dpb7000_state::cpu_sysctrl_r), FUNC(dpb7000_state::cpu_sysctrl_w)); map(0xfff811, 0xfff811).rw(m_acia[1], FUNC(acia6850_device::status_r), FUNC(acia6850_device::control_w)).cswidth(16); map(0xfff813, 0xfff813).rw(m_acia[1], FUNC(acia6850_device::data_r), FUNC(acia6850_device::data_w)).cswidth(16); map(0xfff815, 0xfff815).rw(m_acia[2], FUNC(acia6850_device::status_r), FUNC(acia6850_device::control_w)).cswidth(16); @@ -87,19 +125,152 @@ static INPUT_PORTS_START( dpb7000 ) PORT_DIPSETTING( 0x0c, "4800") PORT_DIPSETTING( 0x0e, "9600") PORT_DIPSETTING( 0x0f, "19200") + + PORT_START("AUTOSTART") + PORT_DIPNAME( 0x0001, 0x0000, "Auto-Start" ) + PORT_DIPSETTING( 0x0000, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0001, DEF_STR( On ) ) + PORT_BIT( 0xfffe, IP_ACTIVE_HIGH, IPT_UNUSED ) + + PORT_START("CONFIGSW12") + PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:8") + PORT_DIPSETTING( 0x0001, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:7") + PORT_DIPSETTING( 0x0002, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:6") + PORT_DIPSETTING( 0x0004, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:5") + PORT_DIPSETTING( 0x0008, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:4") + PORT_DIPSETTING( 0x0010, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:3") + PORT_DIPSETTING( 0x0020, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:2") + PORT_DIPSETTING( 0x0040, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:1") + PORT_DIPSETTING( 0x0080, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:8") + PORT_DIPSETTING( 0x0100, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:7") + PORT_DIPSETTING( 0x0200, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:6") + PORT_DIPSETTING( 0x0400, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:5") + PORT_DIPSETTING( 0x0800, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:4") + PORT_DIPSETTING( 0x1000, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:3") + PORT_DIPSETTING( 0x2000, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:2") + PORT_DIPSETTING( 0x4000, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:1") + PORT_DIPSETTING( 0x8000, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + + PORT_START("CONFIGSW34") + PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:8") + PORT_DIPSETTING( 0x0001, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:7") + PORT_DIPSETTING( 0x0002, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:6") + PORT_DIPSETTING( 0x0004, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:5") + PORT_DIPSETTING( 0x0008, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:4") + PORT_DIPSETTING( 0x0010, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:3") + PORT_DIPSETTING( 0x0020, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:2") + PORT_DIPSETTING( 0x0040, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW3:1") + PORT_DIPSETTING( 0x0080, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:8") + PORT_DIPSETTING( 0x0100, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:7") + PORT_DIPSETTING( 0x0200, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:6") + PORT_DIPSETTING( 0x0400, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:5") + PORT_DIPSETTING( 0x0800, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:4") + PORT_DIPSETTING( 0x1000, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:3") + PORT_DIPSETTING( 0x2000, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:2") + PORT_DIPSETTING( 0x4000, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) + PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW4:1") + PORT_DIPSETTING( 0x8000, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) INPUT_PORTS_END void dpb7000_state::machine_start() { + save_item(NAME(m_csr)); + save_item(NAME(m_sys_ctrl)); } void dpb7000_state::machine_reset() { m_brg->stt_w(m_baud_dip->read()); + m_csr = 0; } MC6845_UPDATE_ROW(dpb7000_state::crtc_update_row) { + const pen_t *pen = m_palette->pens(); + const uint8_t *char_rom = m_vdu_char_rom->base(); + + for (int column = 0; column < x_count; column++) + { + uint8_t code = (uint8_t)m_vdu_ram[((ma + column) & 0x7ff)]; + uint16_t addr = code << 4 | (ra & 0x0f); + uint8_t data = char_rom[addr & 0xfff]; + + if (column == cursor_x) + { + data = 0xff; + } + + for (int bit = 0; bit < 8; bit++) + { + int x = (column * 8) + bit; + int color = BIT(data, 7) && de; + + bitmap.pix32(vbp + y, hbp + x) = pen[color]; + + data <<= 1; + } + } } MC6845_ON_UPDATE_ADDR_CHANGED(dpb7000_state::crtc_addr_changed) @@ -127,6 +298,54 @@ WRITE16_MEMBER(dpb7000_state::bus_error_w) } } +WRITE8_MEMBER(dpb7000_state::csr_w) +{ + logerror("%s: Card Select write: %02x\n", machine().describe_context(), data & 0x0f); + m_csr = data & 0x0f; +} + +READ16_MEMBER(dpb7000_state::cpu_ctrlbus_r) +{ + uint16_t ret = 0; + switch (m_csr) + { + case 12: + ret = m_config_sw34->read(); + logerror("%s: CPU read from Control Bus, Config Switches 1/2: %04x\n", machine().describe_context(), ret); + break; + case 14: + ret = m_config_sw12->read(); + logerror("%s: CPU read from Control Bus, Config Switches 3/4: %04x\n", machine().describe_context(), ret); + break; + default: + logerror("%s: CPU read from Control Bus, unknown CSR %d\n", machine().describe_context(), m_csr); + break; + } + return ret; +} + +WRITE16_MEMBER(dpb7000_state::cpu_ctrlbus_w) +{ + logerror("%s: CPU to Control Bus write: %04x\n", machine().describe_context(), data); +} + +READ16_MEMBER(dpb7000_state::cpu_sysctrl_r) +{ + const uint16_t ctrl = m_sys_ctrl &~ SYSCTRL_AUTO_START; + const uint16_t auto_start = m_auto_start->read() ? SYSCTRL_AUTO_START : 0; + const uint16_t ret = ctrl | auto_start; + logerror("%s: CPU read from System Control: %04x\n", machine().describe_context(), ret); + return ret; +} + +WRITE16_MEMBER(dpb7000_state::cpu_sysctrl_w) +{ + const uint16_t mask = (SYSCTRL_REQ_A_OUT | SYSCTRL_REQ_B_OUT); + logerror("%s: CPU to Control Bus write: %04x\n", machine().describe_context(), data); + m_sys_ctrl &= ~mask; + m_sys_ctrl |= (data & mask); +} + void dpb7000_state::dpb7000(machine_config &config) { M68000(config, m_maincpu, 16_MHz_XTAL / 2); @@ -145,7 +364,7 @@ void dpb7000_state::dpb7000(machine_config &config) ACIA6850(config, m_acia[2], 0); m_acia[2]->irq_handler().set(m_p_int, FUNC(input_merger_device::in_w<1>)); - RS232_PORT(config, m_rs232, default_rs232_devices, "terminal"); + RS232_PORT(config, m_rs232, default_rs232_devices, nullptr); m_rs232->rxd_handler().set(m_acia[0], FUNC(acia6850_device::write_rxd)); m_rs232->dcd_handler().set(m_acia[0], FUNC(acia6850_device::write_dcd)); m_rs232->cts_handler().set(m_acia[0], FUNC(acia6850_device::write_cts)); @@ -164,8 +383,12 @@ void dpb7000_state::dpb7000(machine_config &config) screen.set_visarea(0, 639, 0, 479); // Not accurate screen.set_screen_update("crtc", FUNC(mc6845_device::screen_update)); - SY6545_1(config, m_crtc, 22.248_MHz_XTAL / 8); - m_crtc->set_char_width(9); + PALETTE(config, m_palette, palette_device::MONOCHROME); + + // The 6545's clock is driven by the QD output of a 4-bit binary counter, which has its preset wired to 0010. + // It therefore operates as a divide-by-six counter for the master clock of 22.248MHz. + SY6545_1(config, m_crtc, 22.248_MHz_XTAL / 6); + m_crtc->set_char_width(8); m_crtc->set_show_border_area(false); m_crtc->set_screen("screen"); m_crtc->set_update_row_callback(FUNC(dpb7000_state::crtc_update_row), this); @@ -191,6 +414,9 @@ ROM_START( dpb7000 ) ROM_LOAD16_BYTE("01616a-hcd-9c0e.bin", 0x60000, 0x8000, CRC(938cb614) SHA1(ea7ea8a13e0ab1497691bab53090296ba51d271f)) ROM_LOAD16_BYTE("01616a-gcd-3ab8.bin", 0x70001, 0x8000, CRC(e9c21438) SHA1(1784ab2de1bb6023565b2e27872a0fcda25e1b1f)) ROM_LOAD16_BYTE("01616a-gad-397d.bin", 0x70000, 0x8000, CRC(0b95f9ed) SHA1(77126ee6c1f3dcdb8aa669ab74ff112e3f01918a)) + + ROM_REGION(0x1000, "vduchar", 0) + ROM_LOAD( "bw14char.ic1", 0x0000, 0x1000, BAD_DUMP CRC(f9dd68b5) SHA1(50132b759a6d84c22c387c39c0f57535cd380411) ) ROM_END COMP( 1981, dpb7000, 0, 0, dpb7000, dpb7000, dpb7000_state, empty_init, "Quantel", "DPB-7000", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW ) -- cgit v1.2.3