From 4bc6160200f8c3fcb30d05f63128c0b886703ad8 Mon Sep 17 00:00:00 2001 From: MooglyGuy Date: Sun, 10 Feb 2019 01:54:29 +0100 Subject: -r4000: Added the ability to CTC and CFC from unknown fpr30, which IRIX does often, nw --- src/devices/cpu/mips/r4000.cpp | 6 ++++++ src/devices/cpu/mips/r4000.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/src/devices/cpu/mips/r4000.cpp b/src/devices/cpu/mips/r4000.cpp index b1d5274cc1a..53052ebd14a 100644 --- a/src/devices/cpu/mips/r4000.cpp +++ b/src/devices/cpu/mips/r4000.cpp @@ -171,6 +171,7 @@ void r4000_base_device::device_start() state_add(MIPS3_LO, "LO", m_lo).formatstr("%016X"); // floating point registers + state_add(MIPS3_FCR30, "FCR30", m_fcr30).formatstr("%08X"); state_add(MIPS3_FCR31, "FCR31", m_fcr31).formatstr("%08X"); for (unsigned i = 0; i < 32; i++) state_add(MIPS3_F0 + i, util::string_format("F%d", i).c_str(), m_f[i]); @@ -1668,6 +1669,7 @@ void r4000_base_device::cp1_execute(u32 const op) switch (RDREG) { case 0: m_r[RTREG] = m_fcr0; break; + case 30: m_r[RTREG] = m_fcr30; break; case 31: m_r[RTREG] = m_fcr31; break; default: @@ -1697,6 +1699,10 @@ void r4000_base_device::cp1_execute(u32 const op) case 0: // register is read-only break; + case 30: // unknown + m_fcr30 = u32(m_r[RTREG]); + break; + case 31: m_fcr31 = u32(m_r[RTREG]); diff --git a/src/devices/cpu/mips/r4000.h b/src/devices/cpu/mips/r4000.h index d067d305a5f..5e9a9dc53ed 100644 --- a/src/devices/cpu/mips/r4000.h +++ b/src/devices/cpu/mips/r4000.h @@ -275,6 +275,7 @@ protected: MIPS3_PC = 96, MIPS3_HI, MIPS3_LO, + MIPS3_FCR30, MIPS3_FCR31, }; @@ -409,6 +410,7 @@ protected: // cp1 state u64 m_f[32]; // floating point registers u32 m_fcr0; // implementation and revision register + u32 m_fcr30; // unknown u32 m_fcr31; // control/status register // experimental icache state -- cgit v1.2.3