From 42b3be59355a477ea1a8c3372cc4954680a47348 Mon Sep 17 00:00:00 2001 From: AJR Date: Wed, 10 Jul 2019 19:19:48 -0400 Subject: m37710: Fix UART control register 1 writes and raveracw regression (nw) --- src/devices/cpu/m37710/m37710.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/devices/cpu/m37710/m37710.cpp b/src/devices/cpu/m37710/m37710.cpp index 7d6d79a9403..9b92f18cc8c 100644 --- a/src/devices/cpu/m37710/m37710.cpp +++ b/src/devices/cpu/m37710/m37710.cpp @@ -631,7 +631,7 @@ uint8_t m37710_cpu_device::uart1_ctrl_reg0_r() LOGMASKED(LOG_UART, "uart1_ctrl_reg0_r: UART1 transmit/recv ctrl 0 = %x (PC=%x)\n", m_uart_ctrl_reg0[1], REG_PB<<16 | REG_PC); //return m_uart_ctrl_reg0[1]; - return 0xff; // not hooked up yet + return 0x08; // not hooked up yet } void m37710_cpu_device::uart1_ctrl_reg0_w(uint8_t data) @@ -652,7 +652,7 @@ void m37710_cpu_device::uart0_ctrl_reg1_w(uint8_t data) { LOGMASKED(LOG_UART, "uart0_ctrl_reg0_w %x: UART0 transmit/recv ctrl 1 = %x\n", data, m_uart_ctrl_reg1[0]); - m_uart_ctrl_reg1[0] = data; + m_uart_ctrl_reg1[0] = (m_uart_ctrl_reg1[0] & (BIT(data, 2) ? 0xfa : 0x0a)) | (data & 0x05); } uint8_t m37710_cpu_device::uart1_ctrl_reg1_r() @@ -666,7 +666,7 @@ void m37710_cpu_device::uart1_ctrl_reg1_w(uint8_t data) { LOGMASKED(LOG_UART, "uart1_ctrl_reg1_w %x: UART1 transmit/recv ctrl 1 = %x\n", data, m_uart_ctrl_reg1[1]); - m_uart_ctrl_reg1[1] = data; + m_uart_ctrl_reg1[1] = (m_uart_ctrl_reg1[1] & (BIT(data, 2) ? 0xfa : 0x0a)) | (data & 0x05); } uint16_t m37710_cpu_device::uart0_rbuf_r() -- cgit v1.2.3