From 418eb33cdeffa3f1a26cc9952015be1062c76016 Mon Sep 17 00:00:00 2001 From: hap Date: Sun, 8 Jan 2023 18:35:03 +0100 Subject: pic16c5x: shorthand variable types --- src/devices/cpu/pic16c5x/16c5xdsm.cpp | 30 ++++----- src/devices/cpu/pic16c5x/pic16c5x.cpp | 122 ++++++++++++++++++---------------- src/devices/cpu/pic16c5x/pic16c5x.h | 92 ++++++++++++------------- 3 files changed, 127 insertions(+), 117 deletions(-) diff --git a/src/devices/cpu/pic16c5x/16c5xdsm.cpp b/src/devices/cpu/pic16c5x/16c5xdsm.cpp index ecc0aba2ef0..5f906b6b9cd 100644 --- a/src/devices/cpu/pic16c5x/16c5xdsm.cpp +++ b/src/devices/cpu/pic16c5x/16c5xdsm.cpp @@ -104,11 +104,11 @@ pic16c5x_disassembler::pic16c5x_disassembler() throw std::logic_error(util::string_format("Invalid instruction encoding '%s %s'\n", ops[0],ops[1])); } } - if (bit != -1 ) + if (bit != -1) { throw std::logic_error(util::string_format("not enough bits in encoding '%s %s' %d\n", ops[0],ops[1],bit)); } - while (isspace((uint8_t)*p)) p++; + while (isspace((u8)*p)) p++; Op.emplace_back(mask, bits, *p, ops[0], ops[1]); ops += 2; @@ -123,13 +123,12 @@ offs_t pic16c5x_disassembler::disassemble(std::ostream &stream, offs_t pc, const int cnt = 1; int code; int bit; - //char *buffertmp; const char *cp; // character pointer in OpFormats - uint32_t flags = 0; + u32 flags = 0; op = -1; // no matching opcode code = opcodes.r16(pc); - for ( i = 0; i < int(Op.size()); i++) + for (i = 0; i < int(Op.size()); i++) { if ((code & Op[i].mask) == Op[i].bits) { @@ -141,12 +140,13 @@ offs_t pic16c5x_disassembler::disassemble(std::ostream &stream, offs_t pc, const op = i; } } + if (op == -1) { util::stream_format(stream, "???? dw %04Xh",code); return cnt | SUPPORTED; } - //buffertmp = buffer; + if (Op[op].extcode) // Actually, theres no double length opcodes { bit = 27; @@ -168,14 +168,14 @@ offs_t pic16c5x_disassembler::disassemble(std::ostream &stream, offs_t pc, const // osd_printf_debug("{%c/%d}",*cp,bit); switch (*cp) { - case 'a': a <<=1; a |= ((code & (1< pic16c5x_device::create_disassembler() void pic16c5x_device::update_internalram_ptr() { - m_internalram = (uint8_t *)space(AS_DATA).get_write_ptr(0x00); + m_internalram = (u8 *)space(AS_DATA).get_write_ptr(0x00); } @@ -293,7 +293,7 @@ void pic16c5x_device::update_internalram_ptr() #define M_RDRAM(A) (((A) < 9) ? m_internalram[A] : m_data.read_byte(A)) #define M_WRTRAM(A,V) do { if ((A) < 9) m_internalram[A] = (V); else m_data.write_byte(A,V); } while (0) -#define CLR(flagreg, flag) (flagreg &= uint8_t(~flag)) +#define CLR(flagreg, flag) (flagreg &= u8(~flag)) #define SET(flagreg, flag) (flagreg |= (flag)) #define ADDR (m_opcode.b.l & 0x1f) @@ -303,8 +303,10 @@ void pic16c5x_device::update_internalram_ptr() void pic16c5x_device::calc_zero_flag() { - if (m_ALU == 0) SET(STATUS, Z_FLAG); - else CLR(STATUS, Z_FLAG); + if (m_ALU == 0) + SET(STATUS, Z_FLAG); + else + CLR(STATUS, Z_FLAG); } void pic16c5x_device::CALCULATE_ADD_CARRY() @@ -355,14 +357,14 @@ void pic16c5x_device::set_pc(offs_t addr) PCL = m_PC & 0xff; } -uint16_t pic16c5x_device::pop_stack() +u16 pic16c5x_device::pop_stack() { - uint16_t data = m_STACK[1]; + u16 data = m_STACK[1]; m_STACK[1] = m_STACK[0]; return data & m_program_mask; } -void pic16c5x_device::push_stack(uint16_t data) +void pic16c5x_device::push_stack(u16 data) { m_STACK[0] = m_STACK[1]; m_STACK[1] = data & m_program_mask; @@ -370,9 +372,9 @@ void pic16c5x_device::push_stack(uint16_t data) -uint8_t pic16c5x_device::get_regfile(offs_t addr) // Read from internal memory +u8 pic16c5x_device::get_regfile(offs_t addr) // Read from internal memory { - uint8_t data = 0; + u8 data = 0; if (addr == 0) { // Indirect addressing addr = FSR & m_data_mask; @@ -402,7 +404,7 @@ uint8_t pic16c5x_device::get_regfile(offs_t addr) // Read from internal memory else { data = m_read_a(PIC16C5x_PORTA, 0xff); data &= m_TRISA; - data |= (uint8_t(~m_TRISA) & PORTA); + data |= (u8(~m_TRISA) & PORTA); data &= 0x0f; // 4-bit port (only lower 4 bits used) } break; @@ -415,7 +417,7 @@ uint8_t pic16c5x_device::get_regfile(offs_t addr) // Read from internal memory else if (m_picmodel != 0x1655) { // B is output-only on 1655 data = m_read_b(PIC16C5x_PORTB, 0xff); data &= m_TRISB; - data |= (uint8_t(~m_TRISB) & PORTB); + data |= (u8(~m_TRISB) & PORTB); } break; @@ -427,7 +429,7 @@ uint8_t pic16c5x_device::get_regfile(offs_t addr) // Read from internal memory else if ((m_picmodel == 0x16C55) || (m_picmodel == 0x16C57)) { data = m_read_c(PIC16C5x_PORTC, 0xff); data &= m_TRISC; - data |= (uint8_t(~m_TRISC) & PORTC); + data |= (u8(~m_TRISC) & PORTC); } else { // PIC16C54, PIC16C56, PIC16C58 data = M_RDRAM(addr); @@ -451,7 +453,7 @@ uint8_t pic16c5x_device::get_regfile(offs_t addr) // Read from internal memory return data; } -void pic16c5x_device::store_regfile(offs_t addr, uint8_t data) // Write to internal memory +void pic16c5x_device::store_regfile(offs_t addr, u8 data) // Write to internal memory { if (addr == 0) { // Indirect addressing addr = FSR & m_data_mask; @@ -483,14 +485,14 @@ void pic16c5x_device::store_regfile(offs_t addr, uint8_t data) // Write to inter case 3: // on GI PIC165x, high bits are 1 if (m_picmodel == 0x1650 || m_picmodel == 0x1654 || m_picmodel == 0x1655) - STATUS = data | uint8_t(~m_status_mask); + STATUS = data | u8(~m_status_mask); else - STATUS = (STATUS & (TO_FLAG | PD_FLAG)) | (data & uint8_t(~(TO_FLAG | PD_FLAG))); + STATUS = (STATUS & (TO_FLAG | PD_FLAG)) | (data & u8(~(TO_FLAG | PD_FLAG))); break; case 4: // high bits are 1 - FSR = data | uint8_t(~m_data_mask); + FSR = data | u8(~m_data_mask); break; case 5: @@ -500,7 +502,7 @@ void pic16c5x_device::store_regfile(offs_t addr, uint8_t data) // Write to inter } else if (m_picmodel != 0x1655) { // A is input-only on 1655 data &= 0x0f; // 4-bit port (only lower 4 bits used) - m_write_a(PIC16C5x_PORTA, data & uint8_t(~m_TRISA) & 0x0f, uint8_t(~m_TRISA) & 0x0f); + m_write_a(PIC16C5x_PORTA, data & u8(~m_TRISA) & 0x0f, u8(~m_TRISA) & 0x0f); } PORTA = data; break; @@ -511,7 +513,7 @@ void pic16c5x_device::store_regfile(offs_t addr, uint8_t data) // Write to inter m_write_b(PIC16C5x_PORTB, data, 0xff); } else { - m_write_b(PIC16C5x_PORTB, data & uint8_t(~m_TRISB), uint8_t(~m_TRISB)); + m_write_b(PIC16C5x_PORTB, data & u8(~m_TRISB), u8(~m_TRISB)); } PORTB = data; break; @@ -522,7 +524,7 @@ void pic16c5x_device::store_regfile(offs_t addr, uint8_t data) // Write to inter m_write_c(PIC16C5x_PORTC, data, 0xff); } else if ((m_picmodel == 0x16C55) || (m_picmodel == 0x16C57)) { - m_write_c(PIC16C5x_PORTC, data & uint8_t(~m_TRISC), uint8_t(~m_TRISC)); + m_write_c(PIC16C5x_PORTC, data & u8(~m_TRISC), u8(~m_TRISC)); } PORTC = data; // also writes to RAM break; @@ -542,7 +544,7 @@ void pic16c5x_device::store_regfile(offs_t addr, uint8_t data) // Write to inter } -void pic16c5x_device::store_result(offs_t addr, uint8_t data) +void pic16c5x_device::store_result(offs_t addr, u8 data) { if (m_opcode.b.l & 0x20) store_regfile(addr, data); @@ -651,7 +653,7 @@ void pic16c5x_device::clrwdt() void pic16c5x_device::comf() { - m_ALU = uint8_t(~(get_regfile(ADDR))); + m_ALU = u8(~(get_regfile(ADDR))); store_result(ADDR, m_ALU); calc_zero_flag(); } @@ -745,23 +747,29 @@ void pic16c5x_device::retlw() void pic16c5x_device::rlf() { m_ALU = get_regfile(ADDR); - uint8_t bit7 = m_ALU & 0x80; + u8 bit7 = m_ALU & 0x80; m_ALU <<= 1; if (STATUS & C_FLAG) m_ALU |= 1; store_result(ADDR, m_ALU); - if (bit7) SET(STATUS, C_FLAG); - else CLR(STATUS, C_FLAG); + + if (bit7) + SET(STATUS, C_FLAG); + else + CLR(STATUS, C_FLAG); } void pic16c5x_device::rrf() { m_ALU = get_regfile(ADDR); - uint8_t bit0 = m_ALU & 1; + u8 bit0 = m_ALU & 1; m_ALU >>= 1; if (STATUS & C_FLAG) m_ALU |= 0x80; store_result(ADDR, m_ALU); - if (bit0) SET(STATUS, C_FLAG); - else CLR(STATUS, C_FLAG); + + if (bit0) + SET(STATUS, C_FLAG); + else + CLR(STATUS, C_FLAG); } void pic16c5x_device::sleepic() @@ -784,7 +792,7 @@ void pic16c5x_device::subwf() void pic16c5x_device::swapf() { - uint8_t reg = get_regfile(ADDR); + u8 reg = get_regfile(ADDR); m_ALU = reg << 4 | reg >> 4; store_result(ADDR, m_ALU); } @@ -796,14 +804,14 @@ void pic16c5x_device::tris() case 5: if (m_TRISA != m_W) { m_TRISA = m_W | 0xf0; - m_write_a(PIC16C5x_PORTA, PORTA & uint8_t(~m_TRISA) & 0x0f, uint8_t(~m_TRISA) & 0x0f); + m_write_a(PIC16C5x_PORTA, PORTA & u8(~m_TRISA) & 0x0f, u8(~m_TRISA) & 0x0f); } break; case 6: if (m_TRISB != m_W) { m_TRISB = m_W; - m_write_b(PIC16C5x_PORTB, PORTB & uint8_t(~m_TRISB), uint8_t(~m_TRISB)); + m_write_b(PIC16C5x_PORTB, PORTB & u8(~m_TRISB), u8(~m_TRISB)); } break; @@ -811,7 +819,7 @@ void pic16c5x_device::tris() if ((m_picmodel == 0x16C55) || (m_picmodel == 0x16C57)) { if (m_TRISC != m_W) { m_TRISC = m_W; - m_write_c(PIC16C5x_PORTC, PORTC & uint8_t(~m_TRISC), uint8_t(~m_TRISC)); + m_write_c(PIC16C5x_PORTC, PORTC & u8(~m_TRISC), u8(~m_TRISC)); } } else { @@ -841,7 +849,6 @@ void pic16c5x_device::xorwf() - /*********************************************************************** * Opcode Table (Cycles, Instruction) ***********************************************************************/ @@ -973,6 +980,7 @@ void pic16c5x_device::device_start() m_rtcc = 0; m_count_cycles = 0; m_inst_cycles = 0; + m_debugger_temp = 0; // save states save_item(NAME(m_PC)); @@ -1028,7 +1036,7 @@ void pic16c5x_device::state_import(const device_state_entry &entry) switch (entry.index()) { case PIC16C5x_STR: - STATUS = m_debugger_temp | uint8_t(~m_status_mask); + STATUS = m_debugger_temp | u8(~m_status_mask); break; case PIC16C5x_TMR0: TMR0 = m_debugger_temp; @@ -1046,7 +1054,7 @@ void pic16c5x_device::state_import(const device_state_entry &entry) PORTD = m_debugger_temp; break; case PIC16C5x_FSR: - FSR = m_debugger_temp | uint8_t(~m_data_mask); + FSR = m_debugger_temp | u8(~m_data_mask); break; case PIC16C5x_PSCL: m_prescaler = m_debugger_temp; @@ -1059,7 +1067,7 @@ void pic16c5x_device::state_export(const device_state_entry &entry) switch (entry.index()) { case PIC16C5x_STR: - m_debugger_temp = STATUS | uint8_t(~m_status_mask); + m_debugger_temp = STATUS | u8(~m_status_mask); break; case PIC16C5x_TMR0: m_debugger_temp = TMR0; @@ -1077,7 +1085,7 @@ void pic16c5x_device::state_export(const device_state_entry &entry) m_debugger_temp = PORTD; break; case PIC16C5x_FSR: - m_debugger_temp = FSR | uint8_t(~m_data_mask); + m_debugger_temp = FSR | u8(~m_data_mask); break; } } @@ -1112,7 +1120,7 @@ void pic16c5x_device::state_string_export(const device_state_entry &entry, std:: * Reset registers to their initial values ****************************************************************************/ -void pic16c5x_device::pic16c5x_reset_regs() +void pic16c5x_device::reset_regs() { m_CONFIG = m_temp_config; m_TRISA = 0xff; @@ -1128,13 +1136,13 @@ void pic16c5x_device::pic16c5x_reset_regs() m_count_cycles = 0; } -void pic16c5x_device::pic16c5x_soft_reset() +void pic16c5x_device::watchdog_reset() { SET(STATUS, TO_FLAG | PD_FLAG | Z_FLAG | DC_FLAG | C_FLAG); - pic16c5x_reset_regs(); + reset_regs(); } -void pic16c5x_device::set_config(uint16_t data) +void pic16c5x_device::set_config(u16 data) { logerror("Writing %04x to the PIC16C5x config register\n", data); m_temp_config = data; @@ -1143,7 +1151,7 @@ void pic16c5x_device::set_config(uint16_t data) void pic16c5x_device::device_reset() { - pic16c5x_reset_regs(); + reset_regs(); CLR(STATUS, PA_REG); SET(STATUS, TO_FLAG | PD_FLAG); store_regfile(3, STATUS); @@ -1155,7 +1163,7 @@ void pic16c5x_device::device_reset() * WatchDog ****************************************************************************/ -void pic16c5x_device::pic16c5x_update_watchdog(int counts) +void pic16c5x_device::update_watchdog(int counts) { /* WatchDog is set up to count 18,000 (0x464f hex) ticks to provide @@ -1167,7 +1175,7 @@ void pic16c5x_device::pic16c5x_update_watchdog(int counts) */ if ((m_opcode.w.l != 3) && (m_opcode.w.l != 4)) { - uint16_t old_WDT = m_WDT; + u16 old_WDT = m_WDT; m_WDT -= counts; @@ -1181,12 +1189,12 @@ void pic16c5x_device::pic16c5x_update_watchdog(int counts) if (m_prescaler >= (1 << PS)) { // Prescale values from 1 to 128 m_prescaler = 0; CLR(STATUS, TO_FLAG); - pic16c5x_soft_reset(); + watchdog_reset(); } } else { CLR(STATUS, TO_FLAG); - pic16c5x_soft_reset(); + watchdog_reset(); } } } @@ -1197,7 +1205,7 @@ void pic16c5x_device::pic16c5x_update_watchdog(int counts) * Update Timer ****************************************************************************/ -void pic16c5x_device::pic16c5x_update_timer(int counts) +void pic16c5x_device::update_timer(int counts) { if (m_delay_timer > 0) { // Timer increment is inhibited int dt = m_delay_timer; @@ -1270,12 +1278,12 @@ void pic16c5x_device::execute_run() (this->*s_opcode_00x[(m_opcode.b.l & 0x1f)].function)(); } - pic16c5x_update_timer(T0CS ? m_count_cycles : m_inst_cycles); + update_timer(T0CS ? m_count_cycles : m_inst_cycles); m_count_cycles = 0; } if (WDTE) { - pic16c5x_update_watchdog(m_inst_cycles); + update_watchdog(m_inst_cycles); } m_icount -= m_inst_cycles; diff --git a/src/devices/cpu/pic16c5x/pic16c5x.h b/src/devices/cpu/pic16c5x/pic16c5x.h index ec89481a5df..3dd2aca758a 100644 --- a/src/devices/cpu/pic16c5x/pic16c5x.h +++ b/src/devices/cpu/pic16c5x/pic16c5x.h @@ -68,7 +68,7 @@ public: * during ROM programming, so should be called in the driver INIT, with * the value if known (available in HEX dumps of the ROM). */ - void set_config(uint16_t data); + void set_config(u16 data); void ram_5(address_map &map); void ram_7(address_map &map); @@ -78,7 +78,7 @@ public: protected: // construction/destruction - pic16c5x_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int program_width, int data_width, int picmodel); + pic16c5x_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int program_width, int data_width, int picmodel); // device-level overrides virtual void device_start() override; @@ -92,11 +92,11 @@ protected: * times. (Each instruction cycle passes through 4 machine states). This * is handled by the cpu execution engine. */ - virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const noexcept override { return (clocks + 4 - 1) / 4; } - virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const noexcept override { return (cycles * 4); } - virtual uint32_t execute_min_cycles() const noexcept override { return 1; } - virtual uint32_t execute_max_cycles() const noexcept override { return 2; } - virtual uint32_t execute_input_lines() const noexcept override { return 1; } + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 4 - 1) / 4; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 4); } + virtual u32 execute_min_cycles() const noexcept override { return 1; } + virtual u32 execute_max_cycles() const noexcept override { return 2; } + virtual u32 execute_input_lines() const noexcept override { return 1; } virtual bool execute_input_edge_triggered(int inputnum) const noexcept override { return inputnum == PIC16C5x_RTCC; } virtual void execute_run() override; virtual void execute_set_input(int line, int state) override; @@ -117,33 +117,33 @@ private: address_space_config m_data_config; /******************** CPU Internal Registers *******************/ - uint16_t m_PC; - uint16_t m_PREVPC; // previous program counter - uint8_t m_W; - uint8_t m_OPTION; - uint16_t m_CONFIG; - uint8_t m_ALU; - uint16_t m_WDT; - uint8_t m_TRISA; - uint8_t m_TRISB; - uint8_t m_TRISC; - uint16_t m_STACK[2]; - uint16_t m_prescaler; // Note: this is really an 8-bit register + u16 m_PC; + u16 m_PREVPC; // previous program counter + u8 m_W; + u8 m_OPTION; + u16 m_CONFIG; + u8 m_ALU; + u16 m_WDT; + u8 m_TRISA; + u8 m_TRISB; + u8 m_TRISC; + u16 m_STACK[2]; + u16 m_prescaler; // Note: this is really an 8-bit register PAIR m_opcode; - uint8_t *m_internalram; + u8 *m_internalram; int m_icount; int m_picmodel; int m_data_width; int m_program_width; int m_delay_timer; - uint16_t m_temp_config; + u16 m_temp_config; int m_rtcc; int m_count_cycles; - uint8_t m_old_data; - uint8_t m_data_mask; - uint16_t m_program_mask; - uint8_t m_status_mask; + u8 m_old_data; + u8 m_data_mask; + u16 m_program_mask; + u8 m_status_mask; int m_inst_cycles; memory_access<11, 1, -1, ENDIANNESS_LITTLE>::cache m_program; @@ -166,7 +166,7 @@ private: typedef void (pic16c5x_device::*pic16c5x_ophandler)(); struct pic16c5x_opcode { - uint8_t cycles; + u8 cycles; pic16c5x_ophandler function; }; static const pic16c5x_opcode s_opcode_main[256]; @@ -178,12 +178,18 @@ private: void CALCULATE_ADD_DIGITCARRY(); void CALCULATE_SUB_CARRY(); void CALCULATE_SUB_DIGITCARRY(); - uint16_t pop_stack(); - void push_stack(uint16_t data); + u16 pop_stack(); + void push_stack(u16 data); void set_pc(offs_t addr); - uint8_t get_regfile(offs_t addr); - void store_regfile(offs_t addr, uint8_t data); - void store_result(offs_t addr, uint8_t data); + u8 get_regfile(offs_t addr); + void store_regfile(offs_t addr, u8 data); + void store_result(offs_t addr, u8 data); + + void reset_regs(); + void watchdog_reset(); + void update_watchdog(int counts); + void update_timer(int counts); + void illegal(); void addwf(); void andwf(); @@ -218,10 +224,6 @@ private: void tris(); void xorlw(); void xorwf(); - void pic16c5x_reset_regs(); - void pic16c5x_soft_reset(); - void pic16c5x_update_watchdog(int counts); - void pic16c5x_update_timer(int counts); }; @@ -229,7 +231,7 @@ class pic16c54_device : public pic16c5x_device { public: // construction/destruction - pic16c54_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + pic16c54_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; @@ -237,7 +239,7 @@ class pic16c55_device : public pic16c5x_device { public: // construction/destruction - pic16c55_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + pic16c55_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; @@ -245,7 +247,7 @@ class pic16c56_device : public pic16c5x_device { public: // construction/destruction - pic16c56_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + pic16c56_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; @@ -253,7 +255,7 @@ class pic16c57_device : public pic16c5x_device { public: // construction/destruction - pic16c57_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + pic16c57_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; @@ -261,7 +263,7 @@ class pic16c58_device : public pic16c5x_device { public: // construction/destruction - pic16c58_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + pic16c58_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; @@ -269,26 +271,26 @@ class pic1650_device : public pic16c5x_device { public: // construction/destruction - pic1650_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + pic1650_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; class pic1654s_device : public pic16c5x_device { public: // construction/destruction - pic1654s_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + pic1654s_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); protected: // 1654S has a /8 clock divider instead of the typical /4 - virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const noexcept override { return (clocks + 8 - 1) / 8; } - virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const noexcept override { return (cycles * 8); } + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 8 - 1) / 8; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 8); } }; class pic1655_device : public pic16c5x_device { public: // construction/destruction - pic1655_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + pic1655_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); }; #endif // MAME_CPU_PIC16C5X_PIC16C5X_H -- cgit v1.2.3