From 3ef2082c5fd3837a19e027c89682beafe52155d2 Mon Sep 17 00:00:00 2001 From: AJR Date: Thu, 25 Nov 2021 09:58:34 -0500 Subject: Add CPU16 and HDD device skeletons for Conner CFP1080S --- scripts/src/bus.lua | 2 + scripts/src/cpu.lua | 11 +- scripts/target/mame/arcade.lua | 1 + scripts/target/mame/mess.lua | 1 + src/devices/bus/nscsi/cfp1080s.cpp | 55 ++++++++++ src/devices/bus/nscsi/cfp1080s.h | 31 ++++++ src/devices/bus/nscsi/devices.cpp | 2 + src/devices/cpu/m68hc16/cpu16.cpp | 202 +++++++++++++++++++++++++++++++++++++ src/devices/cpu/m68hc16/cpu16.h | 95 +++++++++++++++++ 9 files changed, 398 insertions(+), 2 deletions(-) create mode 100644 src/devices/bus/nscsi/cfp1080s.cpp create mode 100644 src/devices/bus/nscsi/cfp1080s.h create mode 100644 src/devices/cpu/m68hc16/cpu16.cpp create mode 100644 src/devices/cpu/m68hc16/cpu16.h diff --git a/scripts/src/bus.lua b/scripts/src/bus.lua index 5be5a3361fb..a5dc95b3a51 100644 --- a/scripts/src/bus.lua +++ b/scripts/src/bus.lua @@ -2646,6 +2646,8 @@ if (BUSES["NSCSI"]~=null) then MAME_DIR .. "src/devices/bus/nscsi/cdu415.h", MAME_DIR .. "src/devices/bus/nscsi/cdu561.cpp", MAME_DIR .. "src/devices/bus/nscsi/cdu561.h", + MAME_DIR .. "src/devices/bus/nscsi/cfp1080s.cpp", + MAME_DIR .. "src/devices/bus/nscsi/cfp1080s.h", MAME_DIR .. "src/devices/bus/nscsi/crd254sh.cpp", MAME_DIR .. "src/devices/bus/nscsi/crd254sh.h", MAME_DIR .. "src/devices/bus/nscsi/cw7501.cpp", diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua index 78f18f4430a..c0ef6eac85d 100644 --- a/scripts/src/cpu.lua +++ b/scripts/src/cpu.lua @@ -3518,10 +3518,17 @@ if opt_tool(CPUS, "MK1") then end -------------------------------------------------- --- Motorola M68HC16 (CPU16) - Disassembler only ---@src/devices/cpu/m68hc16/m68hc16.h,CPUS["M68HC16"] = true +-- Motorola M68HC16 (CPU16) +--@src/devices/cpu/m68hc16/cpu16.h,CPUS["M68HC16"] = true -------------------------------------------------- +if CPUS["M68HC16"] then + files { + MAME_DIR .. "src/devices/cpu/m68hc16/cpu16.cpp", + MAME_DIR .. "src/devices/cpu/m68hc16/cpu16.h", + } +end + if opt_tool(CPUS, "M68HC16") then table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/m68hc16/cpu16dasm.cpp") table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/m68hc16/cpu16dasm.h") diff --git a/scripts/target/mame/arcade.lua b/scripts/target/mame/arcade.lua index 10bceddee6e..dfb86378831 100644 --- a/scripts/target/mame/arcade.lua +++ b/scripts/target/mame/arcade.lua @@ -151,6 +151,7 @@ CPUS["KS0164"] = true --CPUS["COPS1"] = true CPUS["MEG"] = true CPUS["F2MC16"] = true +CPUS["M68HC16"] = true -------------------------------------------------- -- specify available sound cores diff --git a/scripts/target/mame/mess.lua b/scripts/target/mame/mess.lua index 56129bd5f7e..4ef2d162be6 100644 --- a/scripts/target/mame/mess.lua +++ b/scripts/target/mame/mess.lua @@ -170,6 +170,7 @@ CPUS["UPD78K"] = true CPUS["ROMP"] = true CPUS["COPS1"] = true CPUS["MK1"] = true +CPUS["M68HC16"] = true -------------------------------------------------- -- specify available sound cores; some of these are diff --git a/src/devices/bus/nscsi/cfp1080s.cpp b/src/devices/bus/nscsi/cfp1080s.cpp new file mode 100644 index 00000000000..27902389b6a --- /dev/null +++ b/src/devices/bus/nscsi/cfp1080s.cpp @@ -0,0 +1,55 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/******************************************************************************* + + Skeleton device for Conner CFP1080S SCSI hard drive. + + Hardware includes "INDY" and "OCEANVIEW" QFP128 ICs by NCR. The MCU is a + QFP144 type labeled SC415902BFV. + + + Model - Conner CFP1080S + Interface - Fast SCSI-2 + Capacity 1080MB + C/H/S - 2794/8/72-114 + Total Blocks - 2,177,184 + +*******************************************************************************/ + +#include "emu.h" +#include "bus/nscsi/cfp1080s.h" +#include "cpu/m68hc16/cpu16.h" + +DEFINE_DEVICE_TYPE(CFP1080S, cfp1080s_device, "cfp1080s", "Conner CFP1080S") + +cfp1080s_device::cfp1080s_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : nscsi_device(mconfig, CFP1080S, tag, owner, clock) + , nscsi_slot_card_interface(mconfig, *this, DEVICE_SELF) + , m_hdcpu(*this, "hdcpu") +{ +} + +void cfp1080s_device::device_start() +{ +} + +void cfp1080s_device::mem_map(address_map &map) +{ + map(0x00000, 0x1ffff).rom().region("firmware", 0); +} + +void cfp1080s_device::device_add_mconfig(machine_config &config) +{ + MC68HC16Z1(config, m_hdcpu, 8'000'000); // exact type and clock unknown + m_hdcpu->set_addrmap(AS_PROGRAM, &cfp1080s_device::mem_map); +} + +ROM_START(cfp1080s) + ROM_REGION16_BE(0x20000, "firmware", 0) + ROM_LOAD16_WORD_SWAP("conner_cfp1080s.bin", 0x00000, 0x20000, CRC(3254150a) SHA1(605be871e75ff775554fc8ce4e09bc2e35a6db09)) +ROM_END + +const tiny_rom_entry *cfp1080s_device::device_rom_region() const +{ + return ROM_NAME(cfp1080s); +} diff --git a/src/devices/bus/nscsi/cfp1080s.h b/src/devices/bus/nscsi/cfp1080s.h new file mode 100644 index 00000000000..7b7927b72ed --- /dev/null +++ b/src/devices/bus/nscsi/cfp1080s.h @@ -0,0 +1,31 @@ +// license:BSD-3-Clause +// copyright-holders:AJR + +#ifndef MAME_BUS_NSCSI_CFP1080S_H +#define MAME_BUS_NSCSI_CFP1080S_H + +#pragma once + +#include "machine/nscsi_bus.h" + +class cfp1080s_device : public nscsi_device, public nscsi_slot_card_interface +{ +public: + cfp1080s_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + + static constexpr feature_type unemulated_features() { return feature::DISK; } + +protected: + virtual void device_start() override; + virtual void device_add_mconfig(machine_config &config) override; + virtual const tiny_rom_entry *device_rom_region() const override; + +private: + void mem_map(address_map &map); + + required_device m_hdcpu; +}; + +DECLARE_DEVICE_TYPE(CFP1080S, cfp1080s_device) + +#endif // MAME_BUS_NSCSI_CFP1080S_H diff --git a/src/devices/bus/nscsi/devices.cpp b/src/devices/bus/nscsi/devices.cpp index 761cebf3012..1ea66e12c7e 100644 --- a/src/devices/bus/nscsi/devices.cpp +++ b/src/devices/bus/nscsi/devices.cpp @@ -10,6 +10,7 @@ #include "bus/nscsi/cdu75s.h" #include "bus/nscsi/cdu415.h" #include "bus/nscsi/cdu561.h" +#include "bus/nscsi/cfp1080s.h" #include "bus/nscsi/crd254sh.h" #include "bus/nscsi/cw7501.h" #include "bus/nscsi/hd.h" @@ -32,6 +33,7 @@ void default_scsi_devices(device_slot_interface &device) device.option_add("smoc501", SMOC501); device.option_add("aplcd150", APPLECD150); device.option_add("aplcdsc", NSCSI_CDROM_APPLE); + device.option_add("cfp1080s", CFP1080S); } void mac_scsi_devices(device_slot_interface &device) diff --git a/src/devices/cpu/m68hc16/cpu16.cpp b/src/devices/cpu/m68hc16/cpu16.cpp new file mode 100644 index 00000000000..d1096ff91b6 --- /dev/null +++ b/src/devices/cpu/m68hc16/cpu16.cpp @@ -0,0 +1,202 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Motorola MC68HC16/CPU16 emulation + + Currently this device is just a stub with no actual execution core. + +***************************************************************************/ + +#include "emu.h" +#include "cpu16.h" +#include "cpu16dasm.h" + +// device type definition +DEFINE_DEVICE_TYPE(MC68HC16Z1, mc68hc16z1_device, "mc68hc16z1", "Motorola MC68HC16Z1") + +cpu16_device::cpu16_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor map) + : cpu_device(mconfig, type, tag, owner, clock) + , m_program_config("program", ENDIANNESS_BIG, 16, 20, 0, map) + , m_data_config("data", ENDIANNESS_BIG, 16, 20, 0, map) + , m_pc(0) + , m_fwa(0) + , m_fetch_pipe{0, 0, 0} + , m_ccr(0) + , m_d(0) + , m_e(0) + , m_ek(0) + , m_index_regs{0, 0, 0} + , m_sp(0) + , m_hr(0) + , m_ir(0) + , m_am(0) + , m_sl(false) + , m_index_mask{0, 0} + , m_icount(0) +{ +} + +mc68hc16z1_device::mc68hc16z1_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : cpu16_device(mconfig, MC68HC16Z1, tag, owner, clock, address_map_constructor(/* TODO */)) +{ +} + +std::unique_ptr cpu16_device::create_disassembler() +{ + return std::make_unique(); +} + +device_memory_interface::space_config_vector cpu16_device::memory_space_config() const +{ + return space_config_vector { + std::make_pair(AS_PROGRAM, &m_program_config), + std::make_pair(AS_DATA, &m_data_config), + }; +} + +void cpu16_device::debug_set_pcbase(u32 value) +{ + m_fwa = value; + debug_set_pc((value + 6) & 0xffffe); + // TODO: prefetch +} + +void cpu16_device::debug_set_pc(u32 value) +{ + m_pc = value; + m_ccr = (m_ccr & 0xfff0) | (value & 0xf0000) >> 16; +} + +void cpu16_device::debug_set_ccr(u16 value) +{ + m_ccr = value; + m_pc = (value & 0x000f) << 16 | (m_pc & 0x0ffff); +} + +u16 cpu16_device::get_k() noexcept +{ + return u16(m_ek) << 12 + | (m_index_regs[0] & 0xf0000) >> 8 + | (m_index_regs[1] & 0xf0000) >> 12 + | (m_index_regs[2] & 0xf0000) >> 16; +} + +void cpu16_device::set_k(u16 value) noexcept +{ + m_ek = (value & 0xf000) >> 12; + m_index_regs[0] = u32(value & 0x0f00) << 8 | (m_index_regs[0] & 0x0ffff); + m_index_regs[1] = u32(value & 0x00f0) << 12 | (m_index_regs[1] & 0x0ffff); + m_index_regs[2] = u32(value & 0x000f) << 16 | (m_index_regs[2] & 0x0ffff); +} + +void cpu16_device::device_start() +{ + space(AS_PROGRAM).cache(m_cache); + space(has_space(AS_DATA) ? AS_DATA : AS_PROGRAM).specific(m_data); + + set_icountptr(m_icount); + + using namespace std::placeholders; + state_add(CPU16_FWA, "FWA", m_fwa, std::bind(&cpu16_device::debug_set_pcbase, this, _1)).mask(0xffffe); + state_add(CPU16_IPIPEC, "IPIPEC", m_fetch_pipe[2]); + state_add(CPU16_IPIPEB, "IPIPEB", m_fetch_pipe[1]); + state_add(CPU16_IPIPEA, "IPIPEA", m_fetch_pipe[0]); + state_add(CPU16_D, "D", m_d); + state_add(CPU16_A, "A", + [this]() { return (m_d & 0xff00) >> 8; }, + [this](u8 value) { m_d = (m_d & 0x00ff) | u16(value) << 8; }).noshow(); + state_add(CPU16_B, "B", + [this]() { return m_d & 0x00ff; }, + [this](u8 value) { m_d = (m_d & 0xff00) | value; }).noshow(); + state_add(CPU16_E, "E", m_e); + for (int i = 0; i < 3; i++) + { + state_add(CPU16_X + i, util::string_format("%c", 'X' + i).c_str(), m_index_regs[i]).mask(0xfffff); + state_add(CPU16_IX + i, util::string_format("I%c", 'X' + i).c_str(), + [this, i]() { return m_index_regs[i] & 0x0ffff; }, + [this, i](u16 value) { m_index_regs[i] = (m_index_regs[i] & 0xf0000) | value; }).noshow(); + state_add(CPU16_XK + i, util::string_format("%cK", 'X' + i).c_str(), + [this, i]() { return (m_index_regs[i] & 0xf0000) >> 16; }, + [this, i](u8 value) { m_index_regs[i] = (m_index_regs[i] & 0x0ffff) | u32(value) << 16; }).mask(0xf).noshow(); + } + state_add(CPU16_SP, "SP", m_sp).mask(0xfffff); + state_add(CPU16_SK, "SK", + [this]() { return (m_sp & 0xf0000) >> 16; }, + [this](u8 value) { m_sp = (m_sp & 0x0ffff) | u32(value) << 16; }).mask(0xf).noshow(); + state_add(CPU16_PC, "PC", m_pc, std::bind(&cpu16_device::debug_set_pc, this, _1)).mask(0xffffe); + state_add(STATE_GENPC, "GENPC", m_pc, std::bind(&cpu16_device::debug_set_pc, this, _1)).mask(0xffffe).noshow(); + state_add(STATE_GENPCBASE, "CURPC", m_fwa, std::bind(&cpu16_device::debug_set_pcbase, this, _1)).mask(0xffffe).noshow(); + state_add(CPU16_CCR, "CCR", m_ccr, std::bind(&cpu16_device::debug_set_ccr, this, _1)); + state_add(STATE_GENFLAGS, "CURFLAGS", m_ccr, std::bind(&cpu16_device::debug_set_ccr, this, _1)).noshow().formatstr("%13s"); + state_add(CPU16_EK, "EK", m_ek).mask(0xf); + state_add(CPU16_K, "K", std::bind(&cpu16_device::get_k, this), std::bind(&cpu16_device::set_k, this, _1)).noshow(); + state_add(CPU16_HR, "HR", m_hr); + state_add(CPU16_IR, "IR", m_ir); + state_add(CPU16_AM, "AM", m_am).mask(0xfffffffff); + state_add(CPU16_SL, "SL", m_sl); + state_add(CPU16_XMSK, "XMSK", m_index_mask[0]); + state_add(CPU16_YMSK, "YMSK", m_index_mask[1]); + + save_item(NAME(m_fwa)); + save_item(NAME(m_fetch_pipe)); + save_item(NAME(m_ccr)); + save_item(NAME(m_d)); + save_item(NAME(m_e)); + save_item(NAME(m_ek)); + save_item(NAME(m_index_regs)); + save_item(NAME(m_sp)); + save_item(NAME(m_pc)); + save_item(NAME(m_hr)); + save_item(NAME(m_ir)); + save_item(NAME(m_am)); + save_item(NAME(m_sl)); + save_item(NAME(m_index_mask)); +} + +void cpu16_device::device_reset() +{ + m_ccr = 0x80e0 | (m_ccr & 0x7f00); // IP, S, SM initialized + for (u32 &i : m_index_regs) + i &= 0x0ffff; + m_ek = 0; +} + +void cpu16_device::execute_run() +{ + u16 word0 = m_cache.read_word(0x00000); // reserved:ZK:SK:PK + m_pc = m_cache.read_word(0x00002) | u32(word0 & 0x000f) << 16; + m_sp = m_cache.read_word(0x00004) | u32(word0 & 0x00f0) << 12; + m_index_regs[2] = m_cache.read_word(0x00006) | u32(word0 & 0x0f00) << 8; + m_ccr = (m_ccr & 0xfff0) | (word0 & 0x000f); + + m_fwa = m_pc; + debugger_instruction_hook(m_fwa); + + m_icount = 0; +} + +void cpu16_device::execute_set_input(int inputnum, int state) +{ + // TODO +} + +void cpu16_device::state_string_export(const device_state_entry &entry, std::string &str) const +{ + switch (entry.index()) + { + case STATE_GENFLAGS: + str = string_format("%c%c%c%c%c%c%c%c$%d %s", + BIT(m_ccr, 15) ? '.' : 'S', + BIT(m_ccr, 14) ? 'M' : '.', + BIT(m_ccr, 13) ? 'H' : '.', + BIT(m_ccr, 12) ? 'E' : '.', + BIT(m_ccr, 11) ? 'N' : '.', + BIT(m_ccr, 10) ? 'Z' : '.', + BIT(m_ccr, 9) ? 'V' : '.', + BIT(m_ccr, 8) ? 'C' : '.', + BIT(m_ccr, 5, 3), + BIT(m_ccr, 4) ? "SM" : " "); + break; + } +} diff --git a/src/devices/cpu/m68hc16/cpu16.h b/src/devices/cpu/m68hc16/cpu16.h new file mode 100644 index 00000000000..5e2616a4470 --- /dev/null +++ b/src/devices/cpu/m68hc16/cpu16.h @@ -0,0 +1,95 @@ +// license:BSD-3-Clause +// copyright-holders:AJR + +#ifndef MAME_CPU_M68HC16_CPU16_H +#define MAME_CPU_M68HC16_CPU16_H + +#pragma once + +class cpu16_device : public cpu_device +{ +public: + enum + { + CPU16_PC, CPU16_FWA, + CPU16_IPIPEA, CPU16_IPIPEB, CPU16_IPIPEC, + CPU16_CCR, CPU16_K, + CPU16_A, CPU16_B, + CPU16_D, CPU16_E, + CPU16_X, CPU16_Y, CPU16_Z, CPU16_SP, + CPU16_IX, CPU16_IY, CPU16_IZ, + CPU16_XK, CPU16_YK, CPU16_ZK, CPU16_SK, CPU16_EK, + CPU16_HR, CPU16_IR, + CPU16_AM, CPU16_SL, + CPU16_XMSK, CPU16_YMSK + }; + +protected: + // construction/destruction + cpu16_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor map); + + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; + + // device_execute_interface overrides + virtual void execute_run() override; + virtual void execute_set_input(int inputnum, int state) override; + + // device_disasm_interface overrides + virtual std::unique_ptr create_disassembler() override; + + // device_memory_interface overrides + virtual space_config_vector memory_space_config() const override; + + // device_state_interface overrides + virtual void state_string_export(const device_state_entry &entry, std::string &str) const override; + +private: + // register helpers + void debug_set_pcbase(u32 value); + void debug_set_pc(u32 value); + void debug_set_ccr(u16 value); + u16 get_k() noexcept; + void set_k(u16 value) noexcept; + + // address spaces + address_space_config m_program_config; + address_space_config m_data_config; + memory_access<20, 1, 0, ENDIANNESS_BIG>::cache m_cache; + memory_access<20, 1, 0, ENDIANNESS_BIG>::specific m_data; + + // basic registers + u32 m_pc; + u32 m_fwa; + u16 m_fetch_pipe[3]; + u16 m_ccr; + u16 m_d; + u16 m_e; + u8 m_ek; + u32 m_index_regs[3]; + u32 m_sp; + + // MAC registers + u16 m_hr; + u16 m_ir; + u64 m_am; + bool m_sl; + u8 m_index_mask[2]; + + // misc. state + s32 m_icount; +}; + +class mc68hc16z1_device : public cpu16_device +{ +public: + // device type constructor + mc68hc16z1_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); +}; + +// device type declaration +DECLARE_DEVICE_TYPE(MC68HC16Z1, mc68hc16z1_device) + + +#endif // MAME_CPU_M68HC16_CPU16_H -- cgit v1.2.3