From 34c3da3aa2a0c49ac065d1e8f41ff55c60beee44 Mon Sep 17 00:00:00 2001 From: Ted Green Date: Wed, 19 Apr 2017 13:34:47 -0600 Subject: midzeus: Added trackball and keyboard to the grid. Driver reorg and cleanup. (nw) --- src/mame/drivers/midzeus.cpp | 319 +++++++++++++++++++++++++++++++++---------- src/mame/includes/midzeus.h | 18 +-- 2 files changed, 255 insertions(+), 82 deletions(-) diff --git a/src/mame/drivers/midzeus.cpp b/src/mame/drivers/midzeus.cpp index a01338ebdc3..0c92df37b6a 100644 --- a/src/mame/drivers/midzeus.cpp +++ b/src/mame/drivers/midzeus.cpp @@ -37,6 +37,7 @@ The Grid v1.2 10/18/2000 #include "crusnexo.lh" +#define LOG_FW (0) #define CPU_CLOCK XTAL_60MHz @@ -51,7 +52,8 @@ static int32_t gun_x[2], gun_y[2]; static uint8_t crusnexo_leds_select; static uint8_t keypad_select; -static uint8_t bitlatch[10]; +static uint32_t disk_asic[0x10]; +static uint32_t disk_asic_jr[0x10]; static uint8_t cmos_protected; @@ -72,6 +74,8 @@ public: required_device m_zeus; DECLARE_WRITE_LINE_MEMBER(zeus_irq); + DECLARE_READ32_MEMBER(zeus2_timekeeper_r); + DECLARE_WRITE32_MEMBER(zeus2_timekeeper_w); private: }; @@ -109,6 +113,9 @@ MACHINE_RESET_MEMBER(midzeus_state,midzeus) m_maincpu->reset(); cmos_protected = true; + memset(disk_asic_jr, 0x0, 0x10 * 4); + disk_asic_jr[6] = 0xa0; // Rev3 Athens + memset(disk_asic, 0x0, 0x10 * 4); } @@ -144,10 +151,10 @@ WRITE_LINE_MEMBER(midzeus2_state::zeus_irq) WRITE32_MEMBER(midzeus_state::cmos_w) { - if (bitlatch[2] && !cmos_protected) + if (disk_asic_jr[2] && !cmos_protected) COMBINE_DATA(&m_nvram[offset]); else - logerror("%06X:timekeeper_w with bitlatch[2] = %d, cmos_protected = %d\n", space.device().safe_pc(), bitlatch[2], cmos_protected); + logerror("%06X:timekeeper_w with disk_asic_jr[2] = %d, cmos_protected = %d\n", space.device().safe_pc(), disk_asic_jr[2], cmos_protected); cmos_protected = true; } @@ -172,17 +179,17 @@ WRITE32_MEMBER(midzeus_state::cmos_protect_w) * *************************************/ -READ32_MEMBER(midzeus_state::zeus2_timekeeper_r) +READ32_MEMBER(midzeus2_state::zeus2_timekeeper_r) { return m_m48t35->read(space, offset, 0xff) | 0xffffff00; } -WRITE32_MEMBER(midzeus_state::zeus2_timekeeper_w) +WRITE32_MEMBER(midzeus2_state::zeus2_timekeeper_w) { - if (bitlatch[2] && !cmos_protected) + if (disk_asic_jr[2] && !cmos_protected) m_m48t35->write(space, offset, data, 0xff); else - logerror("%s:zeus2_timekeeper_w with bitlatch[2] = %d, cmos_protected = %d\n", machine().describe_context(), bitlatch[2], cmos_protected); + logerror("%s:zeus2_timekeeper_w with disk_asic_jr[2] = %d, cmos_protected = %d\n", machine().describe_context(), disk_asic_jr[2], cmos_protected); cmos_protected = true; } @@ -195,114 +202,198 @@ READ32_MEMBER(midzeus_state::zpram_r) WRITE32_MEMBER(midzeus_state::zpram_w) { - if (bitlatch[2]) + if (disk_asic_jr[2]) COMBINE_DATA(&m_nvram[offset]); else - logerror("%06X:zpram_w with bitlatch[2] = %d\n", space.device().safe_pc(), bitlatch[2]); + logerror("%06X:zpram_w with disk_asic_jr[2] = %d\n", space.device().safe_pc(), disk_asic_jr[2]); } +/************************************* +* +* Disk ASIC registers +* +*************************************/ +READ32_MEMBER(midzeus_state::disk_asic_r) +{ + uint32_t retVal = disk_asic[offset]; + switch (offset) + { + // Sys Control + // Bit 0: zeus reset + // Bit 3: io reset + // Bit 15:8 Version + case 0: + retVal = (retVal & 0xffff00ff) | 0x3300; + break; + // Interrupt Status / Control + // 0x004: IFIFO Interrupt + // 0x200: Firewire + case 1: + retVal = 0x0; + break; + // Test + case 2: + break; + // Wait State Config + case 3: + break; + // IDE Config + case 4: + break; + // PSRAM Config + case 5: + break; + // Unknown + default: + logerror("%06X:disk_asic_r(%X) Unknown\n", space.device().safe_pc(), offset); + break; + } + return retVal; +} + + +WRITE32_MEMBER(midzeus_state::disk_asic_w) +{ + disk_asic[offset] = data; + + switch (offset) + { + // Sys Control + // Bit 0: zeus reset + // Bit 3: io reset + case 0: + break; + // Interrupt Status / Control + // 0x004: IFIFO Interrupt + // 0x200: Enable Firewire interrupt + case 1: + break; + // Test + case 2: + break; + // Wait State Config + case 3: + break; + // IDE Config + case 4: + break; + // PSRAM Config + case 5: + break; + // Unknown + default: + logerror("%06X:disk_asic_w(%X)=%08X Unknown\n", space.device().safe_pc(), offset, data); + break; + } +} + /************************************* * - * Miscellaneous bit latches + * Disk ASIC JR registers * *************************************/ - -READ32_MEMBER(midzeus_state::bitlatches_r) +READ32_MEMBER(midzeus_state::disk_asic_jr_r) { + uint32_t retVal = disk_asic_jr[offset]; switch (offset) { - /* unknown purpose; two bits are apparently used */ + // miscelaneous hw wait states case 1: - return bitlatch[offset] | ~3; - - /* CMOS/ZPRAM extra enable latch; only low bit is used */ + break; + /* CMOS/ZPRAM write enable; only low bit is used */ case 2: - return bitlatch[offset] | ~1; + break; + // return disk_asic_jr[offset] | ~1; - /* unknown purpose; mk4/invasn/thegrid read at startup; invasn freaks if it is 1 at startup */ - /* only low bit is used */ + /* reset status; bit 0 is watchdog reset; mk4/invasn/thegrid read at startup; invasn freaks if it is 1 at startup */ case 3: - return bitlatch[offset] | ~1; + break; + // return disk_asic_jr[offset] | ~1; /* ROM bank selection on Zeus 2; two bits are used */ case 5: - return bitlatch[offset] | ~3; + // return disk_asic_jr[offset] | ~3; - /* unknown purpose; crusnexo reads at startup: if (val & 0xf0) == 0xa0 it affects */ + /* disk asic jr id; crusnexo reads at startup: if (val & 0xf0) == 0xa0 it affects */ /* how the Zeus is used (reg 0x5d is set to 0x54580006) */ /* thegrid does the same, writing either 0xD4580006 or 0xC4180006 depending */ /* this is the value reported as DISK JR ASIC version in thegrid startup test */ + // Set in reset + // a0 = Rev3 Athens + // 90 = Rev2 Athens case 6: - return 0xa0 | ~0xff; + break; /* unknown purpose */ default: - logerror("%06X:bitlatches_r(%X)\n", space.device().safe_pc(), offset); + logerror("%06X:disk_asic_jr_r(%X)\n", space.device().safe_pc(), offset); break; } - return ~0; + return retVal; } -WRITE32_MEMBER(midzeus_state::bitlatches_w) +WRITE32_MEMBER(midzeus_state::disk_asic_jr_w) { - uint32_t oldval = bitlatch[offset]; - bitlatch[offset] = data; + //uint32_t oldval = disk_asic_jr[offset]; + disk_asic_jr[offset] = data; switch (offset) { - /* unknown purpose */ - default: - if (oldval ^ data) - logerror("%06X:bitlatches_w(%X) = %X\n", space.device().safe_pc(), offset, data); - break; - - /* unknown purpose; crusnexo toggles this between 0 and 1 every 20 frames; thegrid writes 1 */ + /* disk asic jr led; crusnexo toggles this between 0 and 1 every 20 frames; thegrid writes 1 */ case 0: if (data != 0 && data != 1) - logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); + logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); break; - /* unknown purpose; mk4/invasn write 1 here at initialization; crusnexo/thegrid write 3 */ + /* miscellaneous hardware wait states; mk4/invasn write 1 here at initialization; crusnexo/thegrid write 3 */ case 1: if (data != 1 && data != 3) - logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); + logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); break; - /* CMOS/ZPRAM extra enable latch; only low bit is used */ + /* CMOS/ZPRAM write enable; only low bit is used */ case 2: break; + /* reset status; bit 0 is watchdog reset; mk4/invasn/thegrid read at startup; invasn freaks if it is 1 at startup */ + case 3: + break; + /* unknown purpose; invasn writes 2 here at startup */ case 4: if (data != 2) - logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); + logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); break; /* ROM bank selection on Zeus 2 */ case 5: - membank("bank1")->set_entry(bitlatch[offset] & 3); + membank("bank1")->set_entry(disk_asic_jr[offset] & 3); break; - /* unknown purpose; crusnexo/thegrid write 1 at startup */ + /* zeus2 ws; 0=zeus access 1 wait state, 2=unlock roms; crusnexo/thegrid write 1 at startup */ case 7: - if (data != 1) - logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); break; - /* unknown purpose; crusnexo writes 4 at startup; thegrid writes 6 */ + /* romsize; crusnexo writes 4 at startup; thegrid writes 6 */ case 8: if (data != 4 && data != 6) - logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); + logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); break; - /* unknown purpose; thegrid writes 1 at startup */ + /* trackball reset; thegrid writes 1 at startup */ case 9: if (data != 1) - logerror("%06X:bitlatches_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); + logerror("%06X:disk_asic_jr_w(%X) = %X (unexpected)\n", space.device().safe_pc(), offset, data); break; + /* unknown purpose */ + default: + //if (oldval ^ data) + logerror("%06X:disk_asic_jr_w(%X) = %X\n", space.device().safe_pc(), offset, data); + break; + } } @@ -358,33 +449,75 @@ WRITE32_MEMBER(midzeus_state::crusnexo_leds_w) /************************************* * - * Link controller access (Zeus 2 only) + * Firewwire access (Zeus 2 only) * *************************************/ - -// read 8d0003, check bit 1, skip some stuff if 0 -// write junk to 9e0000 - -READ32_MEMBER(midzeus_state::linkram_r) +READ32_MEMBER(midzeus_state::firewire_r) { - logerror("%06X:unknown_8a000_r(%02X)\n", space.device().safe_pc(), offset); - if (offset == 0) - return 0x30313042; - else if (offset == 0x3c) - return 0xffffffff; - else if (offset == 0x30) - // ??? - return 0xffffffff; - else if (offset == 0xc) - // ??? - return 0xffffffff; - return m_linkram[offset]; + uint32_t retVal = 0; + if (offset < 0x40) + retVal = m_firewire[offset / 4]; + + switch (offset) { + case 0: + // Version + retVal = 0x30313042; + break; + case 0x0c: + // Interrupt + retVal = 0xf4000000;// &m_firewire[0x10 / 4]; + break; + case 0x30: + // Asynchronous Transmit FIFO Status + // 8:0 space available + retVal = 0x1ff; + break; + case 0x3c: + // General Rx FIFO Status + // 0x80000000 = Empty + // 0x40000000 = Control Data + // 0x20000000 = Packet Complete + retVal = 0x80000000; + break; + case 0xc0: + // General Rx FIFO + retVal = 0x0; + break; + } + if LOG_FW logerror("%06X:firewire_r(%02X)=%08X\n", space.device().safe_pc(), offset, retVal); + return retVal; } -WRITE32_MEMBER(midzeus_state::linkram_w) +WRITE32_MEMBER(midzeus_state::firewire_w) { - logerror("%06X:unknown_8a000_w(%02X) = %08X\n", space.device().safe_pc(), offset, data); - COMBINE_DATA(&m_linkram[offset]); + // 0x08 // Control + // Bit 0: Flush bad packets from Rx FIFO + // Bit 6: IRP2En + // Bit 7: IRP1En + // Bit 8: TrgEn + // Bit 20: Reset Rx + // Bit 21: Reset Tx + // Bit 22: Enable Acknowledge + // Bit 23: Iso Rx Enable + // Bit 24: Iso Rx Enable + // Bit 25: Async Rx Enable + // Bit 26: Async Tx Enable + // Bit 30: Rx Self ID packets + // Bit 31: Rx Packets adddressed to phy + // 0x00200000 Reset Tx + // 0x00100000 Reset Rx + // 0x1c // FIFO Control + // Bit 0:8: ITF Size + // Bit 9:17: ATF Size + // Bit 18:26 Trigger Size + // Bit 29: Clear GRF + // Bit 32: Clear ATF + // 0x20 // Diagnostics + // Bit 31: Enable Snooping + + if (offset < 0x40) + COMBINE_DATA(&m_firewire[offset / 4]); + if LOG_FW logerror("%06X:firewire_w(%02X) = %08X\n", space.device().safe_pc(), offset, data); } @@ -469,6 +602,20 @@ CUSTOM_INPUT_MEMBER(midzeus_state::keypad_r) return bits; } +READ32_MEMBER(midzeus_state::grid_keypad_r) +{ + uint32_t bits = (ioport("KEYPAD")->read() >> ((offset >> 1) << 2)) & 0xf; + return bits; +} + +READ32_MEMBER(midzeus_state::trackball_r) +{ + if (offset==0) + return ioport("TRACKY1")->read(); + else + return ioport("TRACKX1")->read(); +} + /************************************* @@ -587,7 +734,7 @@ static ADDRESS_MAP_START( zeus_map, AS_PROGRAM, 32, midzeus_state ) AM_RANGE(0x400000, 0x41ffff) AM_RAM AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_SHARE("tms32031_ctl") AM_RANGE(0x880000, 0x8803ff) AM_READWRITE(zeus_r, zeus_w) AM_SHARE("zeusbase") - AM_RANGE(0x8d0000, 0x8d0004) AM_READWRITE(bitlatches_r, bitlatches_w) + AM_RANGE(0x8d0000, 0x8d0009) AM_READWRITE(disk_asic_jr_r, disk_asic_jr_w) AM_RANGE(0x990000, 0x99000f) AM_DEVREADWRITE("ioasic", midway_ioasic_device, read, write) AM_RANGE(0x9e0000, 0x9e0000) AM_WRITENOP // watchdog? AM_RANGE(0x9f0000, 0x9f7fff) AM_READWRITE(cmos_r, cmos_w) AM_SHARE("nvram") @@ -602,11 +749,12 @@ static ADDRESS_MAP_START( zeus2_map, AS_PROGRAM, 32, midzeus2_state ) AM_RANGE(0x400000, 0x43ffff) AM_RAM AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_SHARE("tms32031_ctl") AM_RANGE(0x880000, 0x88007f) AM_DEVREADWRITE("zeus2", zeus2_device, zeus2_r, zeus2_w) - AM_RANGE(0x8a0000, 0x8a003f) AM_READWRITE(linkram_r, linkram_w) AM_SHARE("linkram") - AM_RANGE(0x8d0000, 0x8d000a) AM_READWRITE(bitlatches_r, bitlatches_w) + AM_RANGE(0x8a0000, 0x8a00cf) AM_READWRITE(firewire_r, firewire_w) AM_SHARE("firewire") + AM_RANGE(0x8d0000, 0x8d0009) AM_READWRITE(disk_asic_jr_r, disk_asic_jr_w) AM_RANGE(0x900000, 0x91ffff) AM_READWRITE(zpram_r, zpram_w) AM_SHARE("nvram") AM_MIRROR(0x020000) AM_RANGE(0x990000, 0x99000f) AM_DEVREADWRITE("ioasic", midway_ioasic_device, read, write) AM_RANGE(0x9c0000, 0x9c000f) AM_READWRITE(analog_r, analog_w) + AM_RANGE(0x9d0000, 0x9d000f) AM_READWRITE(disk_asic_r, disk_asic_w) AM_RANGE(0x9e0000, 0x9e0000) AM_WRITENOP // watchdog? AM_RANGE(0x9f0000, 0x9f7fff) AM_READWRITE(zeus2_timekeeper_r, zeus2_timekeeper_w) AM_RANGE(0x9f8000, 0x9f8000) AM_WRITE(cmos_protect_w) @@ -1092,10 +1240,31 @@ static INPUT_PORTS_START( thegrid ) PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_START("49WAYX") - PORT_BIT( 0xff, 0x38, IPT_AD_STICK_X ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) + PORT_BIT( 0xff, 0x38, IPT_AD_STICK_X ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE PORT_START("49WAYY") - PORT_BIT( 0xff, 0x38, IPT_AD_STICK_Y ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) + PORT_BIT( 0xff, 0x38, IPT_AD_STICK_Y ) PORT_MINMAX(0x00,0x6f) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE + + PORT_START("KEYPAD") + PORT_BIT(0x001, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 1") PORT_CODE(KEYCODE_1_PAD) /* keypad 1 */ + PORT_BIT(0x002, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 4") PORT_CODE(KEYCODE_4_PAD) /* keypad 4 */ + PORT_BIT(0x004, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 7") PORT_CODE(KEYCODE_7_PAD) /* keypad 7 */ + PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad *") PORT_CODE(KEYCODE_MINUS_PAD) /* keypad * */ + PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 2") PORT_CODE(KEYCODE_2_PAD) /* keypad 2 */ + PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 5") PORT_CODE(KEYCODE_5_PAD) /* keypad 5 */ + PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 8") PORT_CODE(KEYCODE_8_PAD) /* keypad 8 */ + PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 0") PORT_CODE(KEYCODE_0_PAD) /* keypad 0 */ + PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 3") PORT_CODE(KEYCODE_3_PAD) /* keypad 3 */ + PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 6") PORT_CODE(KEYCODE_6_PAD) /* keypad 6 */ + PORT_BIT(0x400, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad 9") PORT_CODE(KEYCODE_9_PAD) /* keypad 9 */ + PORT_BIT(0x800, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_NAME("Keypad #") PORT_CODE(KEYCODE_PLUS_PAD) /* keypad # */ + + PORT_START("TRACKX1") + PORT_BIT(0xff, 0x00, IPT_TRACKBALL_X) PORT_SENSITIVITY(1) PORT_KEYDELTA(1) PORT_PLAYER(1) + + PORT_START("TRACKY1") + PORT_BIT(0xff, 0x00, IPT_TRACKBALL_Y) PORT_SENSITIVITY(1) PORT_KEYDELTA(1) PORT_REVERSE PORT_PLAYER(1) + INPUT_PORTS_END @@ -1531,6 +1700,8 @@ DRIVER_INIT_MEMBER(midzeus_state,crusnexo) DRIVER_INIT_MEMBER(midzeus_state,thegrid) { membank("bank1")->configure_entries(0, 3, memregion("user2")->base(), 0x400000*4); + m_maincpu->space(AS_PROGRAM).install_read_handler(0x8c0000, 0x8c0001, read32_delegate(FUNC(midzeus_state::trackball_r), this)); + m_maincpu->space(AS_PROGRAM).install_read_handler(0x9b0000, 0x9b0004, read32_delegate(FUNC(midzeus_state::grid_keypad_r), this)); } diff --git a/src/mame/includes/midzeus.h b/src/mame/includes/midzeus.h index 8f1880b4870..340286ff7c8 100644 --- a/src/mame/includes/midzeus.h +++ b/src/mame/includes/midzeus.h @@ -18,7 +18,7 @@ public: : driver_device(mconfig, type, tag), m_nvram(*this, "nvram"), m_ram_base(*this, "ram_base"), - m_linkram(*this, "linkram"), + m_firewire(*this, "firewire"), m_tms32031_control(*this, "tms32031_ctl"), m_zeusbase(*this, "zeusbase") , m_m48t35(*this, "m48t35"), @@ -28,7 +28,7 @@ public: required_shared_ptr m_nvram; required_shared_ptr m_ram_base; - optional_shared_ptr m_linkram; + optional_shared_ptr m_firewire; required_shared_ptr m_tms32031_control; optional_shared_ptr m_zeusbase; optional_device m_m48t35; @@ -43,12 +43,14 @@ public: DECLARE_WRITE32_MEMBER(cmos_protect_w); DECLARE_READ32_MEMBER(zpram_r); DECLARE_WRITE32_MEMBER(zpram_w); - DECLARE_READ32_MEMBER(bitlatches_r); - DECLARE_WRITE32_MEMBER(bitlatches_w); + DECLARE_READ32_MEMBER(disk_asic_r); + DECLARE_WRITE32_MEMBER(disk_asic_w); + DECLARE_READ32_MEMBER(disk_asic_jr_r); + DECLARE_WRITE32_MEMBER(disk_asic_jr_w); DECLARE_READ32_MEMBER(crusnexo_leds_r); DECLARE_WRITE32_MEMBER(crusnexo_leds_w); - DECLARE_READ32_MEMBER(linkram_r); - DECLARE_WRITE32_MEMBER(linkram_w); + DECLARE_READ32_MEMBER(firewire_r); + DECLARE_WRITE32_MEMBER(firewire_w); DECLARE_READ32_MEMBER(tms32031_control_r); DECLARE_WRITE32_MEMBER(tms32031_control_w); DECLARE_WRITE32_MEMBER(keypad_select_w); @@ -60,8 +62,8 @@ public: DECLARE_WRITE32_MEMBER(zeus_w); DECLARE_CUSTOM_INPUT_MEMBER(custom_49way_r); DECLARE_CUSTOM_INPUT_MEMBER(keypad_r); - DECLARE_READ32_MEMBER(zeus2_timekeeper_r); - DECLARE_WRITE32_MEMBER(zeus2_timekeeper_w); + DECLARE_READ32_MEMBER(grid_keypad_r); + DECLARE_READ32_MEMBER(trackball_r); DECLARE_DRIVER_INIT(invasn); DECLARE_DRIVER_INIT(mk4); DECLARE_DRIVER_INIT(thegrid); -- cgit v1.2.3