From 25f69579bfce78c8e27ad72ea664c3e85c5302a7 Mon Sep 17 00:00:00 2001 From: hap Date: Sun, 5 Dec 2021 19:01:43 +0100 Subject: sparclite: NWINDOWS=8 --- src/devices/cpu/sparc/sparc.cpp | 27 ++++++++++++++++++++++----- src/devices/cpu/sparc/sparc.h | 14 ++++++-------- src/devices/cpu/sparc/sparcdefs.h | 2 ++ 3 files changed, 30 insertions(+), 13 deletions(-) diff --git a/src/devices/cpu/sparc/sparc.cpp b/src/devices/cpu/sparc/sparc.cpp index 7a23dfffe48..2c594a74bb3 100644 --- a/src/devices/cpu/sparc/sparc.cpp +++ b/src/devices/cpu/sparc/sparc.cpp @@ -57,8 +57,6 @@ DEFINE_DEVICE_TYPE(SPARCV7, sparcv7_device, "sparcv7", "Sun SPARC v7") DEFINE_DEVICE_TYPE(SPARCV8, sparcv8_device, "sparcv8", "Sun SPARC v8") DEFINE_DEVICE_TYPE(MB86930, mb86930_device, "mb86930", "Fujitsu MB86930 'SPARClite'") -const int sparc_base_device::NWINDOWS = 7; - #if LOG_FCODES #include "ss1fcode.ipp" #endif @@ -264,6 +262,11 @@ void sparc_base_device::device_start() m_log_fcodes = false; #endif + NWINDOWS = 7; + PSR = 0; + m_ver = 0; + m_impl = 0; + m_bp_reset_in = false; m_bp_fpu_present = true; m_bp_cp_present = false; @@ -481,12 +484,12 @@ void sparc_base_device::device_start() save_item(NAME(m_alu_op3_assigned)); save_item(NAME(m_ldst_op3_assigned)); save_item(NAME(m_alu_setcc)); + save_item(NAME(m_nwindows)); save_item(NAME(m_privileged_asr)); save_item(NAME(m_illegal_instruction_asr)); save_item(NAME(m_mae)); save_item(NAME(m_no_annul)); save_item(NAME(m_hold_bus)); - save_item(NAME(m_icount)); save_item(NAME(m_stashed_icount)); save_item(NAME(m_insn_space)); save_item(NAME(m_data_space)); @@ -558,9 +561,16 @@ void sparc_base_device::device_reset() TBR = 0; Y = 0; - PSR = PSR_S_MASK | PSR_PS_MASK; + PSR = (PSR & PSR_ZERO_MASK) | (PSR_S_MASK | PSR_PS_MASK); m_s = true; + m_ps = true; m_data_space = 11; + m_pil = 0; + m_et = false; + m_icc = 0; + m_ec = false; + m_ef = false; + m_cwp = 0; for (int i = 0; i < 8; i++) { @@ -634,6 +644,13 @@ void mb86930_device::device_start() { sparcv8_device::device_start(); + NWINDOWS = 8; + PSR |= 2 << PSR_VER_SHIFT; + m_ver = 2; + + m_bp_cp_present = false; + m_bp_fpu_present = false; + m_alu_setcc[OP3_DIVSCC] = true; m_alu_op3_assigned[OP3_DIVSCC] = true; @@ -1716,7 +1733,7 @@ void sparc_base_device::execute_wrsr(uint32_t op) return; } - PSR = result &~ PSR_ZERO_MASK; + PSR = (PSR & PSR_ZERO_MASK) | (result & ~PSR_ZERO_MASK); update_gpr_pointers(); m_et = PSR & PSR_ET_MASK; diff --git a/src/devices/cpu/sparc/sparc.h b/src/devices/cpu/sparc/sparc.h index a850f2a6a82..f27d1fe33b1 100644 --- a/src/devices/cpu/sparc/sparc.h +++ b/src/devices/cpu/sparc/sparc.h @@ -225,16 +225,16 @@ protected: uint8_t m_cp_sequence_err; // fields separated out from PSR (Processor State Register) - uint8_t m_impl; // implementation (always 0 in SPARCv7) - uint8_t m_ver; // version (always 0 in SPARCv7) - uint8_t m_icc; // integer condition codes + uint8_t m_impl; // implementation (always 0 in SPARCv7) + uint8_t m_ver; // version (always 0 in SPARCv7) + uint8_t m_icc; // integer condition codes bool m_ec; // enable coprocessor bool m_ef; // enable FPU - uint8_t m_pil; // processor interrupt level + uint8_t m_pil; // processor interrupt level bool m_s; // supervisor mode bool m_ps; // prior S state bool m_et; // enable traps - uint8_t m_cwp; // current window pointer + uint8_t m_cwp; // current window pointer bool m_alu_op3_assigned[64]; bool m_ldst_op3_assigned[64]; @@ -242,6 +242,7 @@ protected: // register windowing helpers uint32_t* m_regs[32]; + int m_nwindows; // other internal states bool m_privileged_asr[32]; @@ -267,9 +268,6 @@ protected: bool m_log_fcodes; #endif - // processor configuration - static const int NWINDOWS; - std::function m_asi_desc_adder; }; diff --git a/src/devices/cpu/sparc/sparcdefs.h b/src/devices/cpu/sparc/sparcdefs.h index 20a90b6a1d7..6b31cfe796b 100644 --- a/src/devices/cpu/sparc/sparcdefs.h +++ b/src/devices/cpu/sparc/sparcdefs.h @@ -85,6 +85,8 @@ #define WIM m_wim #define TBR m_tbr +#define NWINDOWS m_nwindows + #define OP_NS (op & 0xc0000000) #define OP (op >> 30) -- cgit v1.2.3