From 24d2b7a51d435c2be7f8e57886ccc4198392fc20 Mon Sep 17 00:00:00 2001 From: Osso13 Date: Sat, 14 Dec 2019 16:15:56 +0100 Subject: cpu/mips/mips1: initialize some stuff (nw) --- src/devices/cpu/mips/mips1.cpp | 5 +++++ src/devices/cpu/mips/mips1.h | 30 +++++++++++++++--------------- 2 files changed, 20 insertions(+), 15 deletions(-) diff --git a/src/devices/cpu/mips/mips1.cpp b/src/devices/cpu/mips/mips1.cpp index 6c491cb04ca..ca3363fcd32 100644 --- a/src/devices/cpu/mips/mips1.cpp +++ b/src/devices/cpu/mips/mips1.cpp @@ -183,6 +183,9 @@ void mips1core_device_base::device_start() // initialise cpu id register m_cop0[COP0_PRId] = m_cpurev; + + std::fill(std::begin(m_cop0), std::end(m_cop0), 0); + std::fill(std::begin(m_r), std::end(m_r), 0); } void r3041_device::device_start() @@ -1195,6 +1198,8 @@ void mips1_device_base::device_start() state_add(MIPS1_F0 + i, util::string_format("F%d", i * 2).c_str(), m_f[i]); } + std::fill(std::begin(m_f), std::end(m_f), 0); + save_item(NAME(m_reset_time)); save_item(NAME(m_tlb)); diff --git a/src/devices/cpu/mips/mips1.h b/src/devices/cpu/mips/mips1.h index 3a3444607fc..b84f69aeb26 100644 --- a/src/devices/cpu/mips/mips1.h +++ b/src/devices/cpu/mips/mips1.h @@ -206,23 +206,23 @@ protected: const address_space_config m_icache_config; const address_space_config m_dcache_config; - int m_data_spacenum; + int m_data_spacenum= 0; // configuration - u32 m_cpurev; - endianness_t m_endianness; + u32 m_cpurev= 0; + endianness_t m_endianness= ENDIANNESS_BIG; // core registers - u32 m_pc; + u32 m_pc= 0; u32 m_r[32]; - u32 m_hi; - u32 m_lo; + u32 m_hi= 0; + u32 m_lo = 0; // cop0 registers u32 m_cop0[32]; // internal stuff - int m_icount; + int m_icount = 0; enum branch_state_t : unsigned { NONE = 0, @@ -230,8 +230,8 @@ protected: BRANCH = 2, // branch instruction active EXCEPTION = 3, // exception triggered } - m_branch_state; - u32 m_branch_target; + m_branch_state = NONE; + u32 m_branch_target = 0; // cache memory size_t const m_icache_size; @@ -239,7 +239,7 @@ protected: // I/O devcb_read_line m_in_brcond[4]; - bool m_bus_error; + bool m_bus_error = false; }; class mips1_device_base : public mips1core_device_base @@ -307,17 +307,17 @@ protected: template void set_cop1_reg(unsigned const reg, T const data); private: - u64 m_reset_time; + u64 m_reset_time = 0; u32 m_tlb[64][2]; // 0 is hi, 1 is lo unsigned m_tlb_mru[3][64]; // cop1 registers u64 m_f[16]; - u32 m_fcr0; - u32 m_fcr30; - u32 m_fcr31; + u32 m_fcr0 = 0; + u32 m_fcr30 = 0; + u32 m_fcr31 = 0; - unsigned m_fpu_irq; + unsigned m_fpu_irq = 0; }; class r2000_device : public mips1_device_base -- cgit v1.2.3