From 1d143e00525baa1847dfd1fdb6f166eb6094df54 Mon Sep 17 00:00:00 2001 From: AJR Date: Mon, 13 Jan 2020 22:57:27 -0500 Subject: pace: Hack one cycle off shift/rotate instructions when count is nonzero; update notes (nw) --- src/devices/cpu/pace/pace.cpp | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/src/devices/cpu/pace/pace.cpp b/src/devices/cpu/pace/pace.cpp index 85e75b72163..91e105548f0 100644 --- a/src/devices/cpu/pace/pace.cpp +++ b/src/devices/cpu/pace/pace.cpp @@ -9,27 +9,29 @@ successor to the multiple-chip IMP-16 processor contained in a single PMOS LSI package with internal microcode (though the emulation currently uses a state machine instead, loosely based on the published - IMP-16 microcode). The two clock inputs with non-overlapping low + IMP-16 microcode; IMP-16's opcodes and instruction timings differ from + PACE's in various ways). The two clock inputs with non-overlapping low phases required by PACE may be generated by the DP8302 STE (System Timing Element), which divides its oscillator input by 2. - Like the Data General Nova, PACE and IMP-16 have four 16-bit + Much like the Data General Nova, PACE and IMP-16 have four 16-bit accumulators, two of which can be used as index registers. The program - counter can also be used as a base for indexing, and instructions may - also directly access 256 words of memory. The upper 128 words of the - direct region may be mapped to either 0080–00FF or FF80–FFFF, - depending on the state of the BPS input (which National suggests - connecting to one of the flag outputs). The on-chip 10-level LIFO - stack (IMP-16 had a 16-level stack) may hold both return addresses - and register data. The flag register may be transferred to or from - the stack or one of the accumulators. + counter can also be used as a base for relative addressing, and 256 + consecutive words including address 0 may be addressed absolutely. The + upper 128 words of this base page may be mapped to either 0080–00FF + or FF80–FFFF, depending on the state of the BPS input (which National + suggests connecting to one of the flag outputs). The on-chip 10-level + LIFO stack (IMP-16 has a 16-level stack) may hold both return addresses + and register data. The flag register, which includes four general- + purpose outputs, may be transferred to or from the stack or one of the + accumulators. The standard machine cycle takes 4 clock periods (and the shortest instructions take 4 cycles each), though cycles can be stretched by asserting the EXTEND pin (the emulation does not currently support - this). Six interrupts are available, one triggered only by internal - stack full/empty conditions; the nonmaskable level 0 interrupt is - intended primarily for debugging. Each instruction is one word. + this). Six prioritized interrupts are available, one triggered only by + internal stack full/empty conditions; the nonmaskable level 0 interrupt + is intended primarily for debugging use. Each instruction is one word. INS8900 was a NMOS reimplementation of PACE which takes a single-phase clock and allows up to 2 MHz operation. It has different power supply @@ -874,7 +876,7 @@ pace_device::cycle pace_device::execute_one() case cycle::SHL_M8: m_mdr -= 1; - return cycle::SHL_M6; + return m_mdr == 0 ? cycle::IFETCH_M1 : cycle::SHL_M6; case cycle::SHR_M4: prepare_shift(); @@ -894,7 +896,7 @@ pace_device::cycle pace_device::execute_one() case cycle::SHR_M8: m_mdr -= 1; - return cycle::SHR_M6; + return m_mdr == 0 ? cycle::IFETCH_M1 : cycle::SHR_M6; case cycle::ROL_M4: prepare_shift(); @@ -914,7 +916,7 @@ pace_device::cycle pace_device::execute_one() case cycle::ROL_M8: m_mdr -= 1; - return cycle::ROL_M5; + return m_mdr == 0 ? cycle::IFETCH_M1 : cycle::ROL_M5; case cycle::ROR_M4: prepare_shift(); @@ -934,7 +936,7 @@ pace_device::cycle pace_device::execute_one() case cycle::ROR_M8: m_mdr -= 1; - return cycle::ROR_M6; + return m_mdr == 0 ? cycle::IFETCH_M1 : cycle::ROR_M6; case cycle::HALT_M4: // TODO logerror("%04X: HALT opcode encountered\n", m_ppc); -- cgit v1.2.3