From 1ac37fdefec62187ca27c04221841cf08c4e2a16 Mon Sep 17 00:00:00 2001 From: hap Date: Sun, 28 Nov 2021 15:27:14 +0100 Subject: sparc: remove pseudocode comments copy pasted from manual --- src/devices/cpu/sparc/sparc.cpp | 938 ++-------------------------------------- 1 file changed, 29 insertions(+), 909 deletions(-) diff --git a/src/devices/cpu/sparc/sparc.cpp b/src/devices/cpu/sparc/sparc.cpp index bb3516b72d8..14ced724b5d 100644 --- a/src/devices/cpu/sparc/sparc.cpp +++ b/src/devices/cpu/sparc/sparc.cpp @@ -1264,28 +1264,8 @@ void sparc_base_device::execute_set_input(int inputnum, int state) void sparc_base_device::execute_add(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 173, "Appendix C - ISP Descriptions - Add Instructions" (SPARCv8.pdf, pg. 170) - - operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); - - if (ADD or ADDcc) then - result <- r[rs1] + operand2; - else if (ADDX or ADDXcc) then - result <= r[rs1] + operand2 + C; - next; - - if (rd != 0) then - r[rd] <- result; - - if (ADDcc or ADDXcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or - ((not r[rs1]<31>) and (not operand2<31>) and result<31>); - C <- (r[rs1]<31> and operand2<31>) or - ((not result<31>) and (r[rs1]<31> or operand2<31>)) - ); - */ + // The SPARC Instruction Manual: Version 8, page 173, "Appendix C - ISP Descriptions - Add Instructions" (SPARCv8.pdf, pg. 170) + uint32_t rs1 = RS1REG; uint32_t operand2 = USEIMM ? SIMM13 : RS2REG; @@ -1321,31 +1301,8 @@ void sparc_base_device::execute_add(uint32_t op) void sparc_base_device::execute_taddcc(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 173, "Appendix C - ISP Descriptions - Tagged Add Instructions" (SPARCv8.pdf, pg. 170) - - operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); - - result <- r[rs1] + operand2; - next; - - temp_V <- (r[rs1]<31> and operand2<31> and (not result<31>)) or - ((not r[rs1]<31>) and (not operand2<31>) and result<31>) or - (r[rs1]<1:0> != 0 or operand2<1:0> != 0); - next; - - if (TADDccTV and (temp_V = 1)) then ( - trap <- 1; - tag_overflow <- 1 - ) else ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- temp_V; - C <- (r[rs1]<31> and operand2<31>) or - ((not result<31>) and (r[rs1]<31> or operand2<31>)); - if (rd != 0) then - r[rd] <- result; - ); - */ + // The SPARC Instruction Manual: Version 8, page 173, "Appendix C - ISP Descriptions - Tagged Add Instructions" (SPARCv8.pdf, pg. 170) + uint32_t rs1 = RS1REG; uint32_t operand2 = USEIMM ? SIMM13 : RS2REG; @@ -1386,28 +1343,8 @@ void sparc_base_device::execute_taddcc(uint32_t op) void sparc_base_device::execute_sub(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 174, "Appendix C - ISP Descriptions - Subtract Instructions" (SPARCv8.pdf, pg. 171) - - operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); + // The SPARC Instruction Manual: Version 8, page 174, "Appendix C - ISP Descriptions - Subtract Instructions" (SPARCv8.pdf, pg. 171) - if (SUB or SUBcc) then - result <- r[rs1] - operand2; - else if (SUBX or SUBXcc) then - result <= r[rs1] - operand2 - C; - next; - - if (rd != 0) then - r[rd] <- result; - - if (SUBcc or SUBXcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or - ((not r[rs1]<31>) and operand2<31> and result<31>); - C <- ((not r[rs1]<31>) and operand2<31>) or - (result<31> and ((not r[rs1]<31>) or operand2<31>)) - ); - */ uint32_t rs1 = RS1REG; uint32_t operand2 = USEIMM ? SIMM13 : RS2REG; @@ -1443,31 +1380,7 @@ void sparc_base_device::execute_sub(uint32_t op) void sparc_base_device::execute_tsubcc(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 174, "Appendix C - ISP Descriptions - Tagged Subtract Instructions" (SPARCv8.pdf, pg. 171) - - operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); - - result <- r[rs1] - operand2; - next; - - temp_V <- (r[rs1]<31> and (not operand2<31>) and (not result<31>)) or - ((not r[rs1]<31>) and operand2<31> and result<31>) or - (r[rs1]<1:0> != 0 or operand2<1:0> != 0); - next; - - if (TSUBccTV and (temp_V = 1)) then ( - trap <- 1; - tag_overflow <- 1 - ) else ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- temp_V; - C <- ((not r[rs1]<31>) and operand2<31>) or - (result<31> and ((not r[rs1]<31>) or operand2<31>)); - if (rd != 0) then - r[rd] <- result; - ); - */ + // The SPARC Instruction Manual: Version 8, page 174, "Appendix C - ISP Descriptions - Tagged Subtract Instructions" (SPARCv8.pdf, pg. 171) uint32_t rs1 = RS1REG; uint32_t operand2 = USEIMM ? SIMM13 : RS2REG; @@ -1502,27 +1415,7 @@ void sparc_base_device::execute_tsubcc(uint32_t op) } -/* The SPARC Instruction Manual: Version 8, page 172, "Appendix C - ISP Descriptions - Logical Instructions" (SPARCv8.pdf, pg. 169) - -operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); - -if ( AND or ANDcc) then result <- r[rs1] and operand2 -if (ANDN or ANDNcc) then result <- r[rs1] and not operand2 -if ( OR or ORcc) then result <- r[rs1] or operand2 -if ( ORN or ORNcc) then result <- r[rs1] or not operand2 -if ( XOR or XORcc) then result <- r[rs1] xor operand2 -if (XNOR or XNORcc) then result <- r[rs1] xor not operand2; -next; - -if (rd != 0) then r[rd] <- result; - -if (ANDcccc or ANDNcc or ORcc or ORNcc or XORcc or XNORcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- 0 - C <- 0 -); -*/ +// The SPARC Instruction Manual: Version 8, page 172, "Appendix C - ISP Descriptions - Logical Instructions" (SPARCv8.pdf, pg. 169) template void sparc_base_device::execute_and(const uint32_t op) @@ -1639,17 +1532,8 @@ void sparc_base_device::execute_xnor(const uint32_t op) void sparc_base_device::execute_shift(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 172, "Appendix C - ISP Descriptions - Shift Instructions" (SPARCv8.pdf, pg. 169) - - shift_count := if (i = 0) then r[rs2]<4:0> else shcnt; + // The SPARC Instruction Manual: Version 8, page 172, "Appendix C - ISP Descriptions - Shift Instructions" (SPARCv8.pdf, pg. 169) - if (SLL and (rd != 0) ) then - r[rd] <- shift_left_logical(r[rs1], shift_count) - else if (SRL and (rd != 0) ) then - r[rd] <- shift_right_logical(r[rs1], shift_count) - else if (SRA and (rd != 0) ) then - r[rd] <- shift_right_arithmetic(r[rs1], shift_count) - */ uint32_t shift_count = USEIMM ? (SIMM13 & 31) : (RS2REG & 31); if (RDBITS) @@ -1673,29 +1557,8 @@ void sparc_base_device::execute_shift(uint32_t op) void sparc_base_device::execute_mulscc(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 175, "Appendix C - ISP Descriptions - Multiply Step Instruction" (SPARCv8.pdf, pg. 172) - - operand1 := (N xor V) [] (r[rs1]<31:1>); - - operand2 := ( - if (Y<0> = 0) then 0 - else if (i = 0) then r[rs2] else sign_extend(simm13) - ); - - result <- operand1 + operand2; - Y <- r[rs1]<0> [] Y<31:1>; - next; - - if (rd != 0) then ( - r[rd] <- result; - ) - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- (operand1<31> and operand2<31> and (not result<31>)) or - ((not operand1<31>) and (not operand2<31>) and result<31>); - C <- (operand1<31> and operand2<31>) or - ((not result<31>) and (operand1<31> or operand2<31>)) - */ + // The SPARC Instruction Manual: Version 8, page 175, "Appendix C - ISP Descriptions - Multiply Step Instruction" (SPARCv8.pdf, pg. 172) + uint32_t operand1 = ((ICC_N != ICC_V) ? 0x80000000 : 0) | (RS1REG >> 1); uint32_t operand2 = (Y & 1) ? (USEIMM ? SIMM13 : RS2REG) : 0; @@ -1726,23 +1589,7 @@ void sparc_base_device::execute_mulscc(uint32_t op) void sparc_base_device::execute_rdsr(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 182, "Appendix C - ISP Descriptions - Read State Register Instructions" (SPARCv8.pdf, pg. 179) - - if ((RDPSR or RDWIM or RDTBR - or (RDASR and (privileged_ASR(rs1) = 1))) and (S = 0)) then ( - trap <- 1; - privileged_instruction <- 1; - else if (illegal_instruction_ASR(rs1) = 1) then ( - trap <- 1; - illegal_instruction <- 1 - else if (rd != 0) then ( - if (RDY) then r[rd] <- Y - else if (RDASR) then r[rd] <- ASR[rs1] - else if (RDPSR) then r[rd] <- PSR - else if (RDWIM) then r[rd] <- WIM - else if (RDTBR) then r[rd] <- TBR; - ); - */ + // The SPARC Instruction Manual: Version 8, page 182, "Appendix C - ISP Descriptions - Read State Register Instructions" (SPARCv8.pdf, pg. 179) if (((RDPSR || RDWIM || RDTBR) || (RDASR && m_privileged_asr[RS1])) && IS_USER) { @@ -1792,49 +1639,8 @@ void sparc_base_device::execute_rdsr(uint32_t op) void sparc_base_device::execute_wrsr(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 183, "Appendix C - ISP Descriptions - Write State Register Instructions" (SPARCv8.pdf, pg. 180) - - operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); - result := r[rs1] xor operand2; - - if (WRY) then ( - Y'''' <- result - ) else if (WRASR) then ( - if ( (privileged_ASR(rd) = 1) and (S = 0) ) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (illegal_instruction_ASR(rd) = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - ASR[rd]'''' <- result - ) - ) else if (WRPSR) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (result<4:0> >= NWINDOWS) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - PSR'''' <- result - ) - ) else if (WRWIM) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else ( - WIM'''' <- result - ) - ) else if (WRTBR) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else ( - TBR'''' <- result - ) - ); - */ + // The SPARC Instruction Manual: Version 8, page 183, "Appendix C - ISP Descriptions - Write State Register Instructions" (SPARCv8.pdf, pg. 180) + uint32_t operand2 = USEIMM ? SIMM13 : RS2REG; uint32_t result = RS1REG ^ operand2; @@ -1953,41 +1759,7 @@ void sparc_base_device::execute_wrsr(uint32_t op) void sparc_base_device::execute_rett(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 181, "Appendix C - ISP Descriptions - Return from Trap Instructions" (SPARCv8.pdf, pg. 178) - - new_cwp <- (CWP + 1) modulo NWINDOWS; - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - next; - if (ET = 1) then ( - trap <- 1; - if (S = 0) then privileged_instruction <- 1 - else if (S != 0) then illegal_instruction <- 1 - ) else if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - tt <- 00000011; { trap type for privileged_instruction } - execute_mode <- 0; - error_mode = 1 - ) else if ((WIM and (1 << new_cwp)) != 0) then ( - trap <- 1; - window_underflow <- 1; - tt <- 00000110; { trap type for window_underflow } - execute_mode = 0; - error_mode = 1 - ) else if (address<1:0> != 0) then ( - trap = 1; - mem_address_not_aligned = 1; - tt = 7; { trap type for mem_address_not_aligned } - execute_mode = 0; - error_mode = 1 - ) else ( - ET <- 1; - PC <- nPC; - nPC <- address; - CWP <- new_cwp; - S <- PS - ) - */ + // The SPARC Instruction Manual: Version 8, page 181, "Appendix C - ISP Descriptions - Return from Trap Instructions" (SPARCv8.pdf, pg. 178) uint8_t new_cwp = ((PSR & PSR_CWP_MASK) + 1) % NWINDOWS; uint32_t address = RS1REG + (USEIMM ? SIMM13 : RS2REG); @@ -2073,35 +1845,7 @@ void sparc_base_device::execute_rett(uint32_t op) void sparc_base_device::execute_saverestore(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 177, "Appendix C - ISP Descriptions - SAVE and RESTORE Instructions" (SPARCv8.pdf, pg. 174) - - operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); - - if (SAVE) then ( - new_cwp <- (CWP - 1) modulo NWINDOWS; - next; - if ((WIM and (1 << new_cwp)) != 0) then ( - trap <- 1; - window_overflow <- 1 - ) else ( - result <- r[rs1] + operand2; { operands from old window } - CWP <- new_cwp - ) - ) else if (RESTORE) then ( - new_cwp <- (CWP + 1) modulo NWINDOWS; - next; - if ((WIM and (1 << new_cwp)) != 0) then ( - trap <- 1; - window_overflow <- 1 - ) else ( - result <- r[rs1] + operand2; { operands from old window } - CWP <- new_cwp - ) - ); - next; - if ((trap = 0) and (rd != 0)) then - r[rd] <- result { destination in new window } - */ + // The SPARC Instruction Manual: Version 8, page 177, "Appendix C - ISP Descriptions - SAVE and RESTORE Instructions" (SPARCv8.pdf, pg. 174) uint32_t rs1 = RS1REG; uint32_t operand2 = USEIMM ? SIMM13 : RS2REG; @@ -2156,19 +1900,7 @@ void sparc_base_device::execute_saverestore(uint32_t op) void sparc_base_device::execute_jmpl(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 180, "Appendix C - ISP Descriptions - SAVE and RESTORE Instructions" (SPARCv8.pdf, pg. 177) - - jump_address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - next; - if (jump_address<1:0> != 0) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else ( - if (rd != 0) then r[rd] <- PC; - PC <- nPC; - nPC <- jump_address - ) - */ + // The SPARC Instruction Manual: Version 8, page 180, "Appendix C - ISP Descriptions - SAVE and RESTORE Instructions" (SPARCv8.pdf, pg. 177) uint32_t jump_address = RS1REG + (USEIMM ? SIMM13 : RS2REG); @@ -2443,124 +2175,7 @@ void sparc_base_device::update_gpr_pointers() void sparc_base_device::execute_store(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 165, "Appendix C - ISP Descriptions - Store Instructions" (SPARCv8.pdf, pg. 162) - - if ( (S = 0) and (STDA or STA or STHA or STBA or STDFQ or STDCQ) ) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if ((i = 1) and (STDA or STA or STHA or STBA)) then ( - trap <- 1; - illegal_instruction <- 1 - ); - next; - if (trap = 0) then ( - if (STD or ST or STH or STB or STF or STDF or STFSR or STDFQ or STCSR or STC or STDC or STDCQ) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) - ) else if (STDA or STA or STHA or STBA) then ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ); - if ((STF or STDF or STFSR or STDFQ) and - ((EF = 0) or (bp_FPU_present = 0)) ) then ( - trap <- 1; - fp_disabled <- 1; - ); - if ((STC or STDC or STCSR or STDCQ) and - ((EC = 0) or (bp_CP_present = 0)) ) then ( - trap <- 1; - cp_disabled <- 1; - ) - ); - next; - if (trap = 0) then ( - if ((STH or STHA) and (address<0> != 0)) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else if ((ST or STA or STF or STFSR or STC or STCSR) and (address<1:0> != 0)) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else if ((STD or STDA or STDF or STDFQ or STDC or STDCQ) and (address<2:0> != 0)) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else ( - if (STDFQ and ((implementation has no floating-point queue) or (FSR.qne = 0))) then ( - trap <- 1; - fp_exception <- 1; - ftt <- sequence_error; - ); - if (STDCQ and ((implementation has no coprocessor queue)) then ( - trap <- 1; - cp_exception <- 1; - { possibly additional implementation-dependent actions } - ); - if (STDF and (rd<0> != 0)) then ( - trap <- 1; - fp_exception <- 1; - ftt <- invalid_fp_register; - ) - ) - ); - next; - if (trap = 0) then ( - if (STF) then ( byte_mask <- 1111; data0 <- f[rd] ) - else if (STC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STDF) then ( byte_mask <- 1111; data0 <- f[rd & 0x1e] ) - else if (STDC) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STD or STDA) then ( byte_mask <- 1111; data0 <- r[rd & 0x1e] ) - else if (STDFQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STDCQ) then ( byte_mask <- 1111; data0 <- implementation_dependent_value ) - else if (STFSR) then ( - while ((FSR.qne = 1) and (trap = 0)) ( - // wait for pending floating-point instructions to complete - ) - next; - byte_mask <- 1111; data0 <- FSR - ) else if (STCSR) then ( - { implementation-dependent actions } - byte_mask <- 1111; data0 <- CSR - ) else if (ST or STA) then ( byte_mask <- 1111; data0 = r[rd] ) - else if (STH or STHA) then ( - if (address<1:0> = 0) then ( - byte_mask <- 1100; data0 <- shift_left_logical(r[rd], 16) ) - else if (address<1:0> = 2) then ( - byte_mask <- 0011; data0 <- r[rd] ) - ) else if (STB or STBA) then ( - if (address<1:0> = 0) then ( - byte_mask <- 1000; data0 <- shift_left_logical(r[rd], 24) ) - ) else if (address<1:0> = 1) then ( - byte_mask <- 0100; data0 <- shift_left_logical(r[rd], 16) ) - ) else if (address<1:0> = 2) then ( - byte_mask <- 0010; data0 <- shift_left_logical(r[rd], 8) ) - ) else if (address<1:0> = 3) then ( - byte_mask <- 0001; data0 <- r[rd] ) - ) - ); - ); - next; - if (trap = 0) then ( - MAE <- memory_write(addr_space, address, byte_mask, data1); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception <- 1 - ) - ); - if ((trap = 0) and (STD or STDA or STDF or STDC or STDFQ or STDCQ)) then ( - if (STD or STDA) then ( data1 <- r[rd or 00001] ) - else if (STDF) then ( data1 <- f[rd or 00001] ) - else if (STDC) then ( data1 <- implementation_dependent_value } - else if (STDFQ) then ( data1 <- implementation_dependent_value } - else if (STDCQ) then ( data1 <- implementation_dependent_value } - next; - MAE <- memory_write(addr_space, address + 4, 1111, data1); - next; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 - ) - ); - */ + // The SPARC Instruction Manual: Version 8, page 165, "Appendix C - ISP Descriptions - Store Instructions" (SPARCv8.pdf, pg. 162) if (IS_USER && (STDA || STA || STHA || STBA || STDFQ || STDCQ)) { @@ -2786,105 +2401,7 @@ void sparc_base_device::execute_store(uint32_t op) nPC = nPC + 4; } -/* The SPARC Instruction Manual: Version 8, page 163, "Appendix C - ISP Descriptions - C.9. Instruction Defintions - Load Instructions" (SPARCv8.pdf, pg. 160) - -if (LDD or LD or LDSH or LDUH or LDSB or LDUB or LDDF or LDF or LDFSR or LDDC or LDC or LDCSR) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) -) else if (LDDA or LDA or LDSHA or LDUHA or LDSBA or LDUBA) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (i = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ) -) -next; -if (trap = 0) then ( - if ( (LDF or LDDF or LDFSR) and ((EF = 0) or (bp_FPU_present = 0)) then ( - trap <- 1; - fp_disabled <- 1 - ) else if ( (LDC or LDDC or LDCSR) and ((EC = 0) or (bp_CP_present = 0)) then ( - trap <- 1; - cp_disabled <- 1 - ) else if ( ( (LDD or LDDA or LDDF or LDDC) and (address<2:0> != 0)) or - ((LD or LDA or LDF or LDFSR or LDC or LDCSR) and (address<1:0> != 0)) or - ((LDSH or LDSHA or LDUH or LDUHA) and address<0> != 0) ) then ( - trap <- 1; - mem_address_not_aligned <- 1 - ) else if (LDDF and (rd<0> != 0)) then ( - trap <- 1; - fp_exception <- 1; - ftt <- invalid_fpr_register - ) else if ((LDF or LDDF or LDFSR) and (an FPU sequence error is detected)) then ( - trap <- 1; - fp_exception <- 1; - ftt <- sequence_error - ) else if ((LDC or LDDC or LDCSR) and (a CP sequence error is detected)) then ( - trap <- 1; - cp_exception <- 1; - { possibly additional implementation-dependent actions } - ) -); -next; -if (trap = 0) then { - (data, MAE) <- memory_read(addr_space, address); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception <- 1; - ) else ( - if (LDSB or LDSBA or LDUB or LDUBA) then ( - if (address<1:0> = 0) then byte <- data<31:24> - else if (address<1:0> = 1) then byte <- data<23:16> - else if (address<1:0> = 2) then byte <- data<15: 8> - else if (address<1:0> = 3) then byte <- data< 7: 0> - next; - if (LDSB or LDSBA) then - word0 <- sign_extend_byte(byte) - else - word0 <- zero_extend_byte(byte) - ) else if (LDSH or LDSHA or LDUH or LDUHA) then ( - if (address<1:0> = 0) then halfword <- data<31:16> - else if (address<1:0> = 2) then halfword <- data<15: 0> - next; - if (LDSH or LDSHA) then - word0 <- sign_extend_halfword(halfword) - else - word0 <- zero_extend_halfword(halfword) - ) else - word0 <- data - ) -); -next; -if (trap = 0) then ( - if ( (rd != 0) and (LD or LDA or LDSH or LDSHA - or LDUHA or LDUH or LDSB or LDSBA or LDUB or LDUBA) ) then - r[rd] <- word0 - else if (LDF) then f[rd] <- word0 - else if (LDC) then { implementation-dependent actions } - else if (LDFSR) then FSR <- word0 - else if (LDCSR) then CSR <- word0 - else if (LDD or LDDA) then r[rd and 11110] <- word0 - else if (LDDF) then f[rd and 11110] <- word0 - else if (LDDC) then { implementation-dependent actions } -); -next; -if (((trap = 0) and (LDD or LDDA or LDDF or LDDC)) then ( - (word1, MAE) <- memory_read(addr_space, address + 4); - next; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 ) - else if (LDD or LDDA) then r[rd or 1] <- word1 - else if (LDDF) then f[rd or 1] <- word1 - else if (LDDC) then { implementation-dependent actions } -); -*/ +// The SPARC Instruction Manual: Version 8, page 163, "Appendix C - ISP Descriptions - C.9. Instruction Defintions - Load Instructions" (SPARCv8.pdf, pg. 160) inline void sparc_base_device::execute_ldd(uint32_t op) { @@ -3710,64 +3227,7 @@ inline void sparc_base_device::execute_lduba(uint32_t op) void sparc_base_device::execute_ldstub(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 169, "Appendix C - ISP Descriptions - Atomic Load-Store Unsigned Byte Instructions" (SPARCv8.pdf, pg. 166) - - if (LDSTUB) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) - } else if (LDSTUBA) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (i = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ) - ); - next; - if (trap = 0) then ( - while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) then ( - { wait for lock(s) to be lifted } - { an implementation actually need only block when another LDSTUB or SWAP - is pending on the same byte in memory as the one addressed by this LDSTUB } - }; - next; - pb_block_ldst_byte <- 1; - next; - (data, MAE) <- memory_read(addr_space, address); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception <- 1 - ) - ) - next; - if (trap = 0) then ( - if (address<1:0> = 0) then ( byte_mask <- 1000 ) - else if (address<1:0> = 1) then ( byte_mask <- 0100 ) - else if (address<1:0> = 2) then ( byte_mask <- 0010 ) - else if (address<1:0> = 3) then ( byte_mask <- 0001 ) - ; - next; - MAE <- memory_write(addr_space, address, byte_mask, FFFFFFFF); - next; - pb_block_ldst_byte <- 0; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 - ) else ( - if (address<1:0> = 0) then word <- zero_extend_byte(data<31:24>) - else if (address<1:0> = 1) then word <- zero_extend_byte(data<23:24>) - else if (address<1:0> = 2) then word <- zero_extend_byte(data<15: 8>) - else if (address<1:0> = 3) then word <- zero_extend_byte(data< 7: 0>) - next; - if (rd != 0) then r[rd] <- word - ) - ); - */ + // The SPARC Instruction Manual: Version 8, page 169, "Appendix C - ISP Descriptions - Atomic Load-Store Unsigned Byte Instructions" (SPARCv8.pdf, pg. 166) uint32_t address = 0; uint8_t addr_space = 0; @@ -4128,37 +3588,7 @@ bool sparc_base_device::evaluate_condition(uint32_t op) void sparc_base_device::execute_bicc(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 178, "Appendix C - ISP Descriptions - Branch on Integer Condition Instructions" (SPARCv8.pdf, pg. 175) - - eval_icc := ( - if (BNE) then (if (Z = 0) then 1 else 0); - if (BE) then (if (Z = 1) then 1 else 0); - if (BG) then (if ((Z or (N xor V)) = 0) then 1 else 0); - if (BLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); - if (BGE) then (if ((N xor V) = 0) then 1 else 0); - if (BL) then (if ((N xor V) = 1) then 1 else 0); - if (BGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); - if (BLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); - if (BCC) then (if (C = 0) then 1 else 0); - if (BCS) then (if (C = 1) then 1 else 0); - if (BPOS) then (if (N = 0) then 1 else 0); - if (BNEG) then (if (N = 1) then 1 else 0); - if (BVC) then (if (V = 0) then 1 else 0); - if (BVS) then (if (V = 1) then 1 else 0); - if (BA) then 1; - if (BN) then 0; - ) - PC <- nPC; - if (eval_icc = 1) then ( - nPC <- PC + sign_extend(disp22[]00); - if (BA and (a = 1)) then - annul <- 1 { only for annulling Branch-Always } - ) else ( - nPC <- nPC + 4; - if (a = 1) then - annul <- 1 { only for annulling branches other than BA } - ) - */ + // The SPARC Instruction Manual: Version 8, page 178, "Appendix C - ISP Descriptions - Branch on Integer Condition Instructions" (SPARCv8.pdf, pg. 175) bool branch_taken = evaluate_condition(op); uint32_t pc = PC; @@ -4184,40 +3614,7 @@ void sparc_base_device::execute_bicc(uint32_t op) void sparc_base_device::execute_ticc(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 182, "Appendix C - ISP Descriptions - Trap on Integer Condition Instructions" (SPARCv8.pdf, pg. 179) - - trap_eval_icc := ( - if (TNE) then (if (Z = 0) then 1 else 0); - if (TE) then (if (Z = 1) then 1 else 0); - if (TG) then (if ((Z or (N xor V)) = 0) then 1 else 0); - if (TLE) then (if ((Z or (N xor V)) = 1) then 1 else 0); - if (TGE) then (if ((N xor V) = 0) then 1 else 0); - if (TL) then (if ((N xor V) = 1) then 1 else 0); - if (TGU) then (if ((C = 0) and (Z = 0)) then 1 else 0); - if (TLEU) then (if ((C = 1) or (Z = 1)) then 1 else 0); - if (TCC) then (if (C = 0) then 1 else 0); - if (TCS) then (if (C = 1) then 1 else 0); - if (TPOS) then (if (N = 0) then 1 else 0); - if (TNEG) then (if (N = 1) then 1 else 0); - if (TVC) then (if (V = 0) then 1 else 0); - if (TVS) then (if (V = 1) then 1 else 0); - if (TA) then 1; - if (TN) then 0; - ) - - trap_number := r[rs1] + (if (i = 0) then r[rs2] else sign_extend(software_trap#)); - - if (Ticc) then ( - if (trap_eval_icc = 1) then ( - trap <- 1; - trap_instruction <- 1; - ticc_trap_type <- trap_number<6:0> - ) else ( - PC <- nPC; - nPC <- nPC + 4; - ) - ); - */ + // The SPARC Instruction Manual: Version 8, page 182, "Appendix C - ISP Descriptions - Trap on Integer Condition Instructions" (SPARCv8.pdf, pg. 179) bool trap_eval_icc = evaluate_condition(op); @@ -4388,84 +3785,7 @@ void sparcv8_device::update_tt() void sparc_base_device::execute_trap() { - /* The SPARC Instruction Manual: Version 8, page 161, "Appendix C - C.8. Traps" (SPARCv8.pdf, pg. 158) - - select_trap; { see below } - next; - - if (error_mode = 0) then ( - ET <- 0; - PS <- S; - CWP <- (CWP - 1) modulo NWINDOWS; - - next; - if (annul = 0) then ( - r[17] <- PC; - r[18] <- nPC; - ) else { annul != 0) } ( - r[17] <- nPC; - r[18] <- nPC + 4; - annul <- 0; - ) - - next; - S <- 1; - if (reset_trap = 0) then ( - PC <- TBR; - nPC <- TBR + 4; - ) else { reset_trap = 1 } ( - PC <- 0; - nPC <- 4; - reset_trap <- 0; - ) - ); - - select_trap := ( - if (reset_trap = 1) then { ignore ET, and leave tt unchanged } - else if (ET = 0) then ( - execute_mode <- 0; - error_mode <- 1 ) - else if (data_store_error = 1) then tt <- 00101011 - else if (instruction_access_error = 1) then tt <- 00100001 - else if (r_register_access_error = 1) then tt <- 00100000 - else if (instruction_access_exception = 1) then tt <- 00000001 - else if (privileged_instruction = 1) then tt <- 00000011 - else if (illegal_instruction = 1) then tt <- 00000010 - else if (fp_disabled = 1) then tt <- 00000100 - else if (cp_disabled = 1) then tt <- 00100100 - else if (unimplemented_FLUSH = 1) then tt <- 00100101 - else if (window_overflow = 1) then tt <- 00000101 - else if (window_underflow = 1) then tt <- 00000110 - else if (mem_address_not_aligned = 1) then tt <- 00000111 - else if (fp_exception = 1) then tt <- 00001000 - else if (cp_exception = 1) then tt <- 00101000 - else if (data_access_error = 1) then tt <- 00101001 - else if (data_access_exception = 1) then tt <- 00001001 - else if (tag_overflow = 1) then tt <- 00001010 - else if (division_by_zero = 1) then tt <- 00101010 - else if (trap_instruction = 1) then tt <- 1[]ticc_trap_type - else if (interrupt_level > 0) then tt <- 0001[]interrupt_level; - - next; - - trap <- 0; - instruction_access_exception <- 0; - illegal_instruction <- 0; - privileged_instruction <- 0; - fp_disabled <- 0; - cp_disabled <- 0; - window_overflow <- 0; - window_underflow <- 0; - mem_address_not_aligned <- 0; - fp_exception <- 0; - cp_exception <- 0; - data_access_exception <- 0; - tag_overflow <- 0; - division_by_zero <- 0; - trap_instruction <- 0; - interrupt_level <- 0; - ); - */ + // The SPARC Instruction Manual: Version 8, page 161, "Appendix C - C.8. Traps" (SPARCv8.pdf, pg. 158) if (!m_trap) { @@ -4528,31 +3848,7 @@ void sparc_base_device::execute_trap() // single fetched instruction. //------------------------------------------------- -/* The SPARC Instruction Manual: Version 8, page 159, "Appendix C - ISP Descriptions - C.6. Instruction Dispatch" (SPARCv8.pdf, pg. 156) - -illegal_IU_instr :- ( - if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction } - or - ( ((op=11) or (op=10)) and (op3=unassigned) ) - then 1 else 0 - -if (illegal_IU_instr = 1) then ( - trap <- 1 - illegal_instruction <- 1 -); -if ((FPop1 or FPop2 or FBfcc) and ((EF = 0) or (bp_FPU_present = 0))) then ( - trap <- 1; - fp_disabled <- 1 -); -if (CPop1 or CPop2 or CBccc) and ((EC = 0) or (bp_CP_present = 0))) then ( - trap <- 1; - cp_disabled <- 1 -); -next; -if (trap = 0) then ( - { code for specific instruction, defined below } -); -*/ +// The SPARC Instruction Manual: Version 8, page 159, "Appendix C - ISP Descriptions - C.6. Instruction Dispatch" (SPARCv8.pdf, pg. 156) inline void sparc_base_device::dispatch_instruction(uint32_t op) { @@ -5068,54 +4364,7 @@ void sparc_base_device::complete_fp_execution(uint32_t op) void sparcv8_device::execute_swap(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 169, "Appendix C - ISP Descriptions - Atomic Load-Store Unsigned Byte Instructions" (SPARCv8.pdf, pg. 166) - - if (SWAP) then ( - address <- r[rs1] + (if (i = 0) then r[rs2] else sign_extend(simm13)); - addr_space <- (if (S = 0) then 10 else 11) - ) else if (SWAPA) then ( - if (S = 0) then ( - trap <- 1; - privileged_instruction <- 1 - ) else if (i = 1) then ( - trap <- 1; - illegal_instruction <- 1 - ) else ( - address <- r[rs1] + r[rs2]; - addr_space <- asi - ) - ); - next; - if (trap = 0) then ( - temp <- r[rd]; - while ( (pb_block_ldst_byte = 1) or (pb_block_ldst_word = 1) ) ( - { wait for lock(s) to be lifted } - { an implementation actually need only block when another SWAP is pending on - the same word in memory as the one addressed by this SWAP, or a LDSTUB is - pending on any byte of the word in memory addressed by this SWAP } - ); - next; - pb_block_ldst_word <- 1; - next; - (word, MAE) <- memory_read(addr_space, address); - next; - if (MAE = 1) then ( - trap <- 1; - data_access_exception = 1 - ) - next; - if (trap = 0) then ( - MAE <- memory_write(addr_space, address, 1111, temp); - next; - pb_block_ldst_word <- 0; - if (MAE = 1) then ( { MAE = 1 only due to a "non-resumable machine-check error" } - trap <- 1; - data_access_exception <- 1 - ) else ( - if (rd != 0) then r[rd] <- word - ) - ); - */ + // The SPARC Instruction Manual: Version 8, page 169, "Appendix C - ISP Descriptions - Atomic Load-Store Unsigned Byte Instructions" (SPARCv8.pdf, pg. 166) uint32_t address = 0; uint8_t addr_space = 0; @@ -5206,23 +4455,7 @@ void sparcv8_device::execute_swap(uint32_t op) void sparcv8_device::execute_mul(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 175, "Appendix C - ISP Descriptions - Multiply Instructions" (SPARCv8.pdf, pg. 172) - - operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); - - if (UMUL or UMULScc) then (Y, result) <- multiply_unsigned(r[rs1], operand2) - else if (SMUL or SMULcc) then (Y, result) <- multiply_signed(r[rs1], operand2) - next; - if (rd != 0) then ( - r[rd] <- result; - ) - if (UMULcc or SMULcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- 0 - C <- 0 - ); - */ + // The SPARC Instruction Manual: Version 8, page 175, "Appendix C - ISP Descriptions - Multiply Instructions" (SPARCv8.pdf, pg. 172) uint32_t operand2 = (USEIMM ? SIMM13 : RS2REG); @@ -5262,50 +4495,7 @@ void sparcv8_device::execute_mul(uint32_t op) void sparcv8_device::execute_div(uint32_t op) { - /* The SPARC Instruction Manual: Version 8, page 176, "Appendix C - ISP Descriptions - Multiply Instructions" (SPARCv8.pdf, pg. 173) - - operand2 := if (i = 0) then r[rs2] else sign_extend(simm13); - - next; - if (operand2 = 0) then ( - trap <- 1; - division_by_zero <- 1 - ) else ( - if (UDIV or UDIVcc) then ( - temp_64bit <- divide_unsigned(Y[]r[rs1], operand2); - next; - result <- temp_64bit<31:0>; - temp_V <- if (temp_64bit<63:32> = 0) then 0 else 1; - ) else if (SDIV or SDIVcc) then ( - temp_64bit <- divide_signed(Y[]r[rs1], operand2); - next; - result <- temp_64bit<31:0>; - temp_V <- if (temp_64bit<63:31> = 0) or - (temp_64bit<63:31> = (2^33 - 1)) ) then 0 else 1; - ) ; - next; - - if (temp_V) then ( - { result overflowed 32 bits; return largest appropriate integer } - if (UDIV or UDIVcc) then result <- 2^32 - 1; - else if (SDIV or SDIVcc) then ( - if (temp_64bit > 0) then result <- 2^31 - 1; - else result <- -2^31 - ) - ); - next; - - if (rd != 0) then ( - r[rd] <- result - ) ; - if (UDIVcc or SDIVcc) then ( - N <- result<31>; - Z <- if (result = 0) then 1 else 0; - V <- temp_V; - C <- 0 - ) - ); - */ + // The SPARC Instruction Manual: Version 8, page 176, "Appendix C - ISP Descriptions - Multiply Instructions" (SPARCv8.pdf, pg. 173) uint32_t operand2 = (USEIMM ? SIMM13 : RS2REG); @@ -5379,58 +4569,7 @@ void sparcv8_device::execute_div(uint32_t op) inline void sparc_base_device::execute_step() { - /* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153) - - if (bp_reset_in = 1) then ( - execute_mode <- 0; - reset_mode <- 1; - break { out of while (execute_mode = 1) loop } - ) else if ((ET = 1) and ((bp_IRL = 15) or (bp_IRL > PIL))) then ( - trap <- 1; - interrupt_level <- bp_IRL - ); - next; - - if (trap = 1) then execute_trap; { See Section C.8 } - - if (execute_mode = 1) then ( { execute_trap may have set execute_mode to 0 } - - { the following code emulates the delayed nature of the write-state-register instructions. - PSR <- PSR'; PSR' <- PSR''; PSR'' <- PSR'''; PSR''' <- PSR''''; - ASR <- ASR'; ASR' <- ASR''; ASR'' <- ASR'''; ASR''' <- ASR''''; - TBR <- TBR'; TBR' <- TBR''; TBR'' <- TBR'''; TBR''' <- TBR''''; - WIM <- WIM'; WIM' <- WIM''; WIM'' <- WIM'''; WIM''' <- WIM''''; - Y <- Y'; Y' <- Y''; Y'' <- Y'''; Y''' <- Y''''; - next; - - addr_space := (if (S = 0) then 8 else 9); - (instruction, MAE) <- memory_read(addr_space, PC); - next; - - if ( (MAE = 1) and (annul = 0) ) then ( - trap <- 1; - instruction_access_exception <- 1 - ) else ( - if (annul = 0) then ( - dispatch_instruction ; { See Section C.6 } - next; - if (FPop1 or FPop2) then ( - complete_fp_execution { See Section C.7 } - ) - next; - if ( (trap = 0) and - not (CALL or RETT or JMPL or Bicc or FBfcc or CBccc or Ticc) ) then ( - PC <- nPC; - nPC <- nPC + 4 - ) - ) else { annul != 0 } ( - annul <- 0; - PC <- nPC; - nPC <- nPC + 4 - ) - ) - ) - */ + // The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153) // write-state-register delay not yet implemented @@ -5488,17 +4627,7 @@ inline void sparc_base_device::execute_step() void sparc_base_device::reset_step() { - /* The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153) - - while (reset_mode = 1) ( - if (bp_reset_in = 0) then ( - reset_mode <- 0; - execute_mode <- 1; - trap <- 1; - reset_trap <- 1; - ) - ); - */ + // The SPARC Instruction Manual: Version 8, page 156, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 153) if (!m_bp_reset_in) { @@ -5518,16 +4647,7 @@ void sparc_base_device::reset_step() void sparc_base_device::error_step() { - /* The SPARC Instruction Manual: Version 8, page 157, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 154) - - while (error_mode = 1) ( - if (bp_reset_in = 1) then ( - error_mode <- 0; - reset_mode <- 1; - pb_error <- 0 - ) - ); - */ + // The SPARC Instruction Manual: Version 8, page 157, "Appendix C - ISP Descriptions - C.5. Processor States and Instruction Dispatch" (SPARCv8.pdf, pg. 154) if (m_bp_reset_in) { -- cgit v1.2.3