From 0810a75c23972b4d87f840b6eb75d29e661a0f46 Mon Sep 17 00:00:00 2001 From: Quench0 Date: Sun, 24 Sep 2017 21:35:51 +1000 Subject: CPU M6800: CPX (compare X) instruction, fix behaviour of V flag #2. (nw) Previous fix for CPX I posted a year ago was flawed and didn't handle overflow properly. --- src/devices/cpu/m6800/6800ops.hxx | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/devices/cpu/m6800/6800ops.hxx b/src/devices/cpu/m6800/6800ops.hxx index db6429c0ba9..83bc10827c5 100644 --- a/src/devices/cpu/m6800/6800ops.hxx +++ b/src/devices/cpu/m6800/6800ops.hxx @@ -1085,11 +1085,12 @@ OP_HANDLER( cmpx_im ) PAIR r,d,b; IMMWORD(b); d.d = X; - r.d = d.d - b.d; + r.w.l = d.b.h - b.b.h; CLR_NZV; + SET_N8(r.b.l); + SET_V8(d.b.h, b.b.h, r.w.l); + r.d = d.d - b.d; SET_Z16(r.d); - SET_N8(r.b.h); - SET_V8(d.b.h, b.b.h, r.b.h); } /* $8c CPX immediate -**** (6803) */ @@ -1252,11 +1253,12 @@ OP_HANDLER( cmpx_di ) PAIR r,d,b; DIRWORD(b); d.d = X; - r.d = d.d - b.d; + r.w.l = d.b.h - b.b.h; CLR_NZV; + SET_N8(r.b.l); + SET_V8(d.b.h, b.b.h, r.w.l); + r.d = d.d - b.d; SET_Z16(r.d); - SET_N8(r.b.h); - SET_V8(d.b.h, b.b.h, r.b.h); } /* $9c CPX direct -**** (6803) */ @@ -1426,11 +1428,12 @@ OP_HANDLER( cmpx_ix ) PAIR r,d,b; IDXWORD(b); d.d = X; - r.d = d.d - b.d; + r.w.l = d.b.h - b.b.h; CLR_NZV; + SET_N8(r.b.l); + SET_V8(d.b.h, b.b.h, r.w.l); + r.d = d.d - b.d; SET_Z16(r.d); - SET_N8(r.b.h); - SET_V8(d.b.h, b.b.h, r.b.h); } /* $ac CPX indexed -**** (6803)*/ @@ -1602,11 +1605,12 @@ OP_HANDLER( cmpx_ex ) PAIR r,d,b; EXTWORD(b); d.d = X; - r.d = d.d - b.d; + r.w.l = d.b.h - b.b.h; CLR_NZV; + SET_N8(r.b.l); + SET_V8(d.b.h, b.b.h, r.w.l); + r.d = d.d - b.d; SET_Z16(r.d); - SET_N8(r.b.h); - SET_V8(d.b.h, b.b.h, r.b.h); } /* $bc CPX extended -**** (6803) */ -- cgit v1.2.3