From 02198d069bdafdf11731e1363df6c51ba057449e Mon Sep 17 00:00:00 2001 From: Patrick Mackinlay Date: Mon, 1 Feb 2021 16:36:24 +0700 Subject: z80scc: tidy logging a little bit --- src/devices/machine/z80scc.cpp | 270 +++++++++++++++++++---------------------- 1 file changed, 125 insertions(+), 145 deletions(-) diff --git a/src/devices/machine/z80scc.cpp b/src/devices/machine/z80scc.cpp index e3a7c8a1d00..a7af4fdc253 100644 --- a/src/devices/machine/z80scc.cpp +++ b/src/devices/machine/z80scc.cpp @@ -508,7 +508,7 @@ void z80scc_device::device_resolve_objects() //------------------------------------------------- void z80scc_device::device_start() { - LOG("%s", FUNCNAME); + LOG("%s\n", FUNCNAME); // state saving save_item(NAME(m_out_int_state)); @@ -525,7 +525,7 @@ void z80scc_device::device_start() //------------------------------------------------- void z80scc_device::device_reset_after_children() { - LOG("%s %s \n",tag(), FUNCNAME); + LOG("%s\n", FUNCNAME); // Hardware reset values for registers where it differs from channel reset values m_wr9 &= 0x3c; @@ -585,7 +585,7 @@ int z80scc_device::z80daisy_irq_state() { int state = 0; - LOGINT("%s %s A:%d%d%d B:%d%d%d ", tag(), FUNCNAME, + LOGINT("%s: A:%d%d%d B:%d%d%d\n", FUNCNAME, m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3], m_int_state[4], m_int_state[5]); @@ -604,7 +604,7 @@ int z80scc_device::z80daisy_irq_state() // Last chance to keep the control of the interrupt line state |= (m_wr9 & WR9_BIT_DLC) ? Z80_DAISY_IEO : 0; - LOGINT("- Interrupt State %u\n", state); + LOGINT("- Interrupt State %d\n", state); return state; } @@ -617,7 +617,7 @@ int z80scc_device::z80daisy_irq_ack() { int ret = -1; // Indicate default vector - LOGINT("%s %s \n",tag(), FUNCNAME); + LOGINT("%s\n", FUNCNAME); // loop over all interrupt sources for (auto & elem : m_int_state) { @@ -646,8 +646,7 @@ int z80scc_device::z80daisy_irq_ack() { // default irq vector is -1 for 68000 but 0 for z80 for example... ret = owner()->subdevice(m_cputag)->default_irq_vector(INPUT_LINE_IRQ0); - LOGINT(" - failed to find an interrupt to ack, returning default IRQ vector: %02x\n", ret ); - logerror("z80sio_irq_ack: failed to find an interrupt to ack!\n"); + logerror("%s: failed to find an interrupt to ack, returning default IRQ vector: %02x\n", FUNCNAME, ret); } return ret; @@ -666,7 +665,7 @@ daisy chain, the SCC has a Disable Lower Chain (DLC) software command (WR9 bit 2 */ void z80scc_device::z80daisy_irq_reti() { - LOGINT("%s %s - No RETI detection needed on SCC\n",tag(), FUNCNAME); + LOGINT("%s: No RETI detection needed on SCC\n", FUNCNAME); } @@ -690,7 +689,7 @@ void z80scc_device::check_interrupts() //------------------------------------------------- void z80scc_device::reset_interrupts() { - LOGINT("%s %s \n",tag(), FUNCNAME); + LOGINT("%s\n", FUNCNAME); // reset internal interrupt sources for (auto & elem : m_int_state) { @@ -747,6 +746,7 @@ int z80scc_device::get_extint_priority(int type) case z80scc_channel::INT_TRANSMIT: prio = z80scc_channel::INT_TRANSMIT_PRIO; break; case z80scc_channel::INT_SPECIAL: prio = z80scc_channel::INT_SPECIAL_PRIO; break; default: logerror("Bad interrupt source being prioritized!"); + break; } return prio; } @@ -762,7 +762,7 @@ void z80scc_device::trigger_interrupt(int index, int type) int prio_level = 0; - LOGINT("%s %s:%c %02x \n",FUNCNAME, tag(), 'A' + index, type); + LOGINT("%s: %02x\n", FUNCNAME, type); /* The Master Interrupt Enable (MIE) bit, WR9 D3, must be set to enable the SCC to generate interrupts.*/ if (!(m_wr9 & WR9_BIT_MIE)) @@ -775,7 +775,7 @@ void z80scc_device::trigger_interrupt(int index, int type) prio_level = get_extint_priority(type); if (source < z80scc_channel::INT_TRANSMIT || source > z80scc_channel::INT_SPECIAL || prio_level < 0 || prio_level > 2) { - logerror("Attempt to trigger interrupt of unknown origin blocked: %02x/%02x on channel %c\n", source, prio_level, 'A' + index); + logerror("Attempt to trigger interrupt of unknown origin blocked: %02x/%02x\n", source, prio_level); return; } // Vector modification requested? @@ -784,7 +784,7 @@ void z80scc_device::trigger_interrupt(int index, int type) vector = modify_vector(vector, index, source); } - LOGINT(" Interrupt Request fired of type %u and vector %02x\n", type, vector); + LOGINT(" Interrupt Request fired of type %d and vector %02x\n", type, vector); // update vector register m_chanB->m_rr2 = vector; @@ -915,6 +915,7 @@ void z80scc_device::zbus_w(offs_t offset, uint8_t data) m_chanA->scc_register_write(reg, data); else m_chanB->scc_register_write(reg, data); + break; } return; @@ -1212,6 +1213,7 @@ void z80scc_channel::device_timer(emu_timer &timer, device_timer_id id, int para break; default: logerror("Spurious timer %d event\n", id); + break; } #endif } @@ -1224,13 +1226,13 @@ void z80scc_channel::tra_callback() { if (!(m_wr5 & WR5_TX_ENABLE)) { - LOGTX("%s \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5); + LOGTX("%s: transmit mark 1 m_wr5:%02x\n", FUNCNAME, m_wr5); // transmit mark out_txd_cb(1); } else if (m_wr5 & WR5_SEND_BREAK) { - LOGTX("%s \"%s \"Channel %c send break 1 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5); + LOGTX("%s: send break 1 m_wr5:%02x\n", FUNCNAME, m_wr5); // transmit break out_txd_cb(0); } @@ -1238,14 +1240,13 @@ void z80scc_channel::tra_callback() { int db = transmit_register_get_data_bit(); - LOGTX("%s \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, db, m_wr5); + LOGTX("%s: transmit data bit %d m_wr5:%02x\n", FUNCNAME, db, m_wr5); // transmit data out_txd_cb(db); } else { - LOGTX("%s \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5); - logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, owner()->tag(), 'A' + m_index); + logerror("%s: Failed to transmit m_wr5:%02x\n", FUNCNAME, m_wr5); } } @@ -1267,7 +1268,7 @@ void z80scc_channel::tra_complete() if ( (m_rr0 & RR0_TX_BUFFER_EMPTY) == 0 || // Takes care of the NMOS/CMOS 1 slot TX FIFO m_tx_fifo_rp != m_tx_fifo_wp) // or there are more characters to send in a longer FIFO. { - LOGTX("%s %s %c done sending, loading data from fifo:%02x '%c'\n", FUNCNAME, owner()->tag(), 'A' + m_index, + LOGTX("%s: done sending, loading data from fifo:%02x '%c'\n", FUNCNAME, m_tx_data_fifo[m_tx_fifo_rp], isascii(m_tx_data_fifo[m_tx_fifo_rp]) ? m_tx_data_fifo[m_tx_fifo_rp] : ' '); transmit_register_setup(m_tx_data_fifo[m_tx_fifo_rp]); // Reload the shift register m_tx_fifo_rp_step(); @@ -1275,7 +1276,7 @@ void z80scc_channel::tra_complete() } else { - LOGTX("%s %s %c done sending, setting all sent bit\n", FUNCNAME, owner()->tag(), 'A' + m_index); + LOGTX("%s: done sending, setting all sent bit\n", FUNCNAME); m_rr1 |= RR1_ALL_SENT; // when the RTS bit is reset, the _RTS output goes high after the transmitter empties @@ -1304,13 +1305,13 @@ void z80scc_channel::tra_complete() } else if (m_wr5 & WR5_SEND_BREAK) { - LOG("%s \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5); + LOG("%s: Transmit Break 0 m_wr5:%02x\n", FUNCNAME, m_wr5); // transmit break out_txd_cb(0); } else { - LOG("%s \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5); + LOG("%s: Transmit Mark 1 m_wr5:%02x\n", FUNCNAME, m_wr5); // transmit mark out_txd_cb(1); } @@ -1324,16 +1325,13 @@ void z80scc_channel::rcv_callback() { if (m_wr3 & WR3_RX_ENABLE) { - LOG("%s \"%s \"Channel %c receive data bit %d m_wr3:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_rxd, m_wr3); + LOG("%s: receive data bit %d m_wr3:%02x\n", FUNCNAME, m_rxd, m_wr3); receive_register_update_bit(m_rxd); } -#if 1 else { - LOG("%s \"%s \"Channel %c Received Data Bit but receiver is disabled\n", FUNCNAME, owner()->tag(), 'A' + m_index); - logerror("%s \"%s \"Channel %c Received data dit but receiver is disabled\n", FUNCNAME, owner()->tag(), 'A' + m_index); + logerror("%s: Received data dit but receiver is disabled\n", FUNCNAME); } -#endif } @@ -1346,7 +1344,7 @@ void z80scc_channel::rcv_complete() receive_register_extract(); data = get_received_char(); - LOG("%s \"%s \"Channel %c Received Data %c\n", FUNCNAME, owner()->tag(), 'A' + m_index, data); + LOG("%s: Received Data %c\n", FUNCNAME, data); receive_data(data); #if START_BIT_HUNT m_rcv_mode = RCV_SEEKING; @@ -1385,13 +1383,13 @@ TODO: */ void z80scc_channel::set_rts(int state) { - LOG("%s(%d) \"%s\": %c \n", FUNCNAME, state, owner()->tag(), 'A' + m_index); + LOG("%s(%d)\n", FUNCNAME, state); out_rts_cb(state); } void z80scc_channel::update_rts() { -// LOG("%s(%d) \"%s\": %c \n", FUNCNAME, state, owner()->tag(), 'A' + m_index); +// LOG("%s(%d)\n", FUNCNAME, state); if (m_wr5 & WR5_RTS) { // when the RTS bit is set, the _RTS output goes low @@ -1471,16 +1469,16 @@ uint8_t z80scc_channel::do_sccreg_rr0() { uint8_t rr0 = m_rr0; - LOG("%s %c %s <- %02x\n",tag(), 'A' + m_index, FUNCNAME, m_rr0); + LOG("%s <- %02x\n", FUNCNAME, m_rr0); if (m_extint_latch == 1) { rr0 &= ((~m_wr15) | WR15_WR7PRIME | WR15_STATUS_FIFO); // clear enabled bits, saving 2 unrelated bits rr0 |= (m_extint_states & ~((~m_wr15) | WR15_WR7PRIME | WR15_STATUS_FIFO)); // set enabled bits to latched states - LOGINT("- %c returning latched value RR0:%02x WR15:%02x => %02x\n", 'A' + m_index, m_rr0, m_wr15, rr0); + LOGINT("- returning latched value RR0:%02x WR15:%02x => %02x\n", m_rr0, m_wr15, rr0); } else { - LOG("- %c returning unlatched value: %02x\n", 'A' + m_index, rr0); + LOG("- returning unlatched value: %02x\n", rr0); } return rr0; @@ -1491,7 +1489,7 @@ uint8_t z80scc_channel::do_sccreg_rr0() * codes for the I-Field in the SDLC Receive Mode. */ uint8_t z80scc_channel::do_sccreg_rr1() { - LOGR("%s %s <- %02x\n",tag(), FUNCNAME, m_rr1); + LOGR("%s <- %02x\n", FUNCNAME, m_rr1); return m_rr1; } @@ -1590,7 +1588,6 @@ uint8_t z80scc_channel::do_sccreg_rr6() LOGR("%s\n", FUNCNAME); if (m_wr15 & WR15_STATUS_FIFO) { - LOGSYNC(" - Status FIFO for synchronous mode - not implemented\n"); logerror(" - Status FIFO for synchronous mode - not implemented\n"); return 0; } @@ -1610,7 +1607,7 @@ uint8_t z80scc_channel::do_sccreg_rr7() LOGR("%s\n", FUNCNAME); if (!(m_uart->m_variant & (z80scc_device::SET_NMOS))) { - logerror("%s not implemented feature\n", FUNCNAME); + logerror("%s: feature not implemented\n", FUNCNAME); return 0; } return m_rr3; @@ -1640,8 +1637,7 @@ uint8_t z80scc_channel::do_sccreg_rr9() /* RR10 contains some SDLC related miscellaneous status bits. Unused bits are always 0. */ uint8_t z80scc_channel::do_sccreg_rr10() { - LOGR("%s\n", FUNCNAME); - logerror("%s not implemented feature\n", FUNCNAME); + logerror("%s: feature not implemented\n", FUNCNAME); return m_rr10; } @@ -1703,7 +1699,7 @@ uint8_t z80scc_channel::do_sccreg_rr15() uint8_t z80scc_channel::scc_register_read( uint8_t reg) { if (reg > 1) - LOG("%s %02x\n", FUNCNAME, reg); + LOG("%s: %02x\n", FUNCNAME, reg); uint8_t data = 0; uint8_t wreg = 0; @@ -1751,7 +1747,8 @@ uint8_t z80scc_channel::scc_register_read( uint8_t reg) case REG_RR14_WR7_OR_R10: data = do_sccreg_rr14(); break; case REG_RR15_WR15_EXT_STAT: data = do_sccreg_rr15(); break; default: - logerror(" \"%s\"%s: %c : Unsupported RRx register:%02x\n", owner()->tag(), FUNCNAME, 'A' + m_index, reg); + logerror("%s: Unsupported RRx register:%02x\n", FUNCNAME, reg); + break; } return data; } @@ -1765,19 +1762,19 @@ uint8_t z80scc_channel::control_read() int reg = m_uart->m_wr0_ptrbits; int regmask = (WR0_REGISTER_MASK | (m_uart->m_wr0_ptrbits & WR0_POINT_HIGH)); - LOGR("%s(%02x) reg %02x, regmask %02x, WR0 %02x\n", FUNCNAME, data, reg, regmask, m_wr0); + LOGR("%s(%02x): reg %02x, regmask %02x, WR0 %02x\n", FUNCNAME, data, reg, regmask, m_wr0); m_uart->m_wr0_ptrbits = 0; reg &= regmask; if (reg != 0) { - LOG("%s(%02x) reg %02x, regmask %02x, WR0 %02x\n", FUNCNAME, data, reg, regmask, m_wr0); + LOG("%s(%02x): reg %02x, regmask %02x, WR0 %02x\n", FUNCNAME, data, reg, regmask, m_wr0); m_wr0 &= ~regmask; // mask out register index } data = scc_register_read(reg); - //LOG("%s \"%s\": %c : Register R%d read '%02x'\n", FUNCNAME, owner()->tag(), 'A' + m_index, reg, data); + //LOG("%s: Register R%d read '%02x'\n", FUNCNAME, reg, data); return data; } @@ -1800,11 +1797,11 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data) addressing*/ if (m_uart->m_variant & z80scc_device::SET_Z85X3X) { - LOG("%s %s: %c : - Point High command\n", FUNCNAME, owner()->tag(), 'A' + m_index); + LOG("%s: Point High command\n", FUNCNAME); m_uart->m_wr0_ptrbits |= 8; } else - LOG("%s %s: %c : - NULL command 2\n", FUNCNAME, owner()->tag(), 'A' + m_index); + LOG("%s: NULL command 2\n", FUNCNAME); break; case WR0_RESET_EXT_STATUS: /*After an External/Status interrupt (a change on a modem line or a break condition, @@ -1819,7 +1816,7 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data) (there are two transitions), another interrupt is not generated. Exceptions to this rule are detailed in the RR0 description.*/ - LOGCMD("%s %c - Reset External/Status Interrupt, latch %s\n", owner()->tag(), 'A' + m_index, + LOGCMD("Reset External/Status Interrupt, latch %s\n", m_extint_latch == 1? "is released" : "was already released"); // Release latch if no other external or status sources are active if ((m_extint_latch = m_uart->update_extint(m_index)) == 0) @@ -1832,19 +1829,18 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data) an interrupt service routine. */ if (m_uart->m_variant & z80scc_device::SET_NMOS) { - logerror("WR0 SWI ack command not supported on NMOS\n"); - LOGCMD("%s: %c : WR0_RESET_HIGHEST_IUS command not available on NMOS!\n", owner()->tag(), 'A' + m_index); + logerror("WR0_RESET_HIGHEST_IUS command not supported on NMOS\n"); } else { - LOGCMD("%s: %c : Reset Highest IUS\n", owner()->tag(), 'A' + m_index); + LOGCMD("Reset Highest IUS\n"); // loop over all interrupt sources for (auto & elem : m_uart->m_int_state) { // find the first interrupt under service if (elem & Z80_DAISY_IEO) { - LOGCMD("- %c found IUS bit to clear\n", 'A' + m_index); + LOGCMD("- found IUS bit to clear\n"); elem = 0; // Clear IUS bit (called IEO in z80 daisy lingo) m_uart->check_interrupts(); break; @@ -1858,18 +1854,18 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data) data with the special condition is held in the Receive FIFO until this command is issued. If either of these modes is selected and this command is issued before the data has been read from the Receive FIFO, the data is lost */ - LOGCMD("%s: %c : WR0_ERROR_RESET - not implemented\n", owner()->tag(), 'A' + m_index); + LOGCMD("WR0_ERROR_RESET - not implemented\n"); if (m_rx_fifo_wp != m_rx_fifo_rp) m_rx_fifo_rp_step(); // Reset error state in fifo and unlock it. unlock == step to next slot in fifo. break; case WR0_SEND_ABORT: // Flush transmitter and Send 8-13 bits of '1's, used with SDLC - LOGCMD("%s: %c : WR0_SEND_ABORT - not implemented\n", owner()->tag(), 'A' + m_index); + LOGCMD("WR0_SEND_ABORT - not implemented\n"); break; case WR0_NULL: // Do nothing - LOGCMD("%s: %c : WR0_NULL\n", owner()->tag(), 'A' + m_index); + LOGCMD("WR0_NULL\n"); break; case WR0_ENABLE_INT_NEXT_RX: // enable interrupt on next receive character - LOGCMD("%s: %c : WR0_ENABLE_INT_NEXT\n", owner()->tag(), 'A' + m_index); + LOGCMD("WR0_ENABLE_INT_NEXT\n"); m_rx_first = 1; break; case WR0_RESET_TX_INT: // reset transmitter interrupt pending @@ -1879,7 +1875,7 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data) been completely sent. This command is necessary to prevent the transmitter from requesting an interrupt when the transmit buffer becomes empty (with Transmit Interrupt Enabled).*/ m_tx_int_disarm = 1; - LOGCMD("%s: %c : WR0_RESET_TX_INT\n", owner()->tag(), 'A' + m_index); + LOGCMD("WR0_RESET_TX_INT\n"); m_uart->m_int_state[INT_TRANSMIT_PRIO + (m_index == z80scc_device::CHANNEL_A ? 0 : 3 )] = 0; // Based on the fact that prio levels are aligned with the bitorder of rr3 we can do this... m_uart->m_chanA->m_rr3 &= ~(1 << (INT_TRANSMIT_PRIO + ((m_index == z80scc_device::CHANNEL_A) ? 3 : 0))); @@ -1905,8 +1901,6 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data) case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the RRO register) */ LOGCMD(" CRC_RESET_TX_UNDERRUN - not implemented\n"); break; - default: /* Will not happen unless someone messes with the mask */ - logerror(" Wrong CRC reset/init command:%02x\n", data & WR0_CRC_RESET_CODE_MASK); } if (m_uart->m_variant & z80scc_device::SET_Z85X3X) @@ -1919,15 +1913,15 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data) /* Write Register 1 is the control register for the various SCC interrupt and Wait/Request modes.*/ void z80scc_channel::do_sccreg_wr1(uint8_t data) { - LOG("%s(%02x) \"%s\": %c : %s - %02x\n", FUNCNAME, data, owner()->tag(), 'A' + m_index, FUNCNAME, data); + LOG("%s(%02x)\n", FUNCNAME, data); /* TODO: Sort out SCC specific behaviours from legacy SIO behaviours inherited from z80dart.cpp: - Channel B only bits vs - Parity Is Special Condition, bit2 */ m_wr1 = data; - LOG("- External Interrupt Enable %u\n", (data & WR1_EXT_INT_ENABLE) ? 1 : 0); - LOG("- Transmit Interrupt Enable %u\n", (data & WR1_TX_INT_ENABLE) ? 1 : 0); - LOG("- Parity is special condition %u\n", (data & WR1_PARITY_IS_SPEC_COND) ? 1 : 0); - LOG("- Wait/DMA Request Enable %u\n", (data & WR1_WREQ_ENABLE) ? 1 : 0); + LOG("- External Interrupt Enable %d\n", (data & WR1_EXT_INT_ENABLE) ? 1 : 0); + LOG("- Transmit Interrupt Enable %d\n", (data & WR1_TX_INT_ENABLE) ? 1 : 0); + LOG("- Parity is special condition %d\n", (data & WR1_PARITY_IS_SPEC_COND) ? 1 : 0); + LOG("- Wait/DMA Request Enable %d\n", (data & WR1_WREQ_ENABLE) ? 1 : 0); LOG("- Wait/DMA Request Function %s\n", (data & WR1_WREQ_FUNCTION) ? "Request" : "Wait"); LOG("- Wait/DMA Request on %s\n", (data & WR1_WREQ_ON_RX_TX) ? "Receive" : "Transmit"); @@ -1961,7 +1955,7 @@ void z80scc_channel::do_sccreg_wr1(uint8_t data) is controlled by the Vector Includes Status (VIS) and the Status High/Status Low bits in WR9.*/ void z80scc_channel::do_sccreg_wr2(uint8_t data) { - LOG("%s(%02x) Setting the interrupt vector\n", FUNCNAME, data); + LOG("%s(%02x): Setting the interrupt vector\n", FUNCNAME, data); m_wr2 = data; m_uart->m_chanA->m_rr2 = data; m_uart->m_chanB->m_rr2 = data; /* TODO: Sort out the setting of ChanB depending on bits in WR9 */ @@ -1978,15 +1972,15 @@ void z80scc_channel::do_sccreg_wr2(uint8_t data) the Sync/Hunt bit is set again is by the Enter Hunt Mode command or by disabling the receiver.*/ void z80scc_channel::do_sccreg_wr3(uint8_t data) { - LOG("%s(%02x) Setting up the receiver\n", FUNCNAME, data); + LOG("%s(%02x): Setting up the receiver\n", FUNCNAME, data); m_wr3 = data; - LOG("- Receiver Enable: %u\n", (data & WR3_RX_ENABLE) ? 1 : 0); - LOG("- Sync Char Load Inhibit %u\n", (data & WR3_SYNC_CHAR_LOAD_INHIBIT) ? 1 : 0); - LOG("- Address Search Mode %u\n", (data & WR3_ADDRESS_SEARCH_MODE) ? 1 : 0); - LOG("- Rx CRC Enable %u\n", (data & WR3_RX_CRC_ENABLE) ? 1 : 0); - LOG("- Enter Hunt Mode %u\n", (data & WR3_ENTER_HUNT_MODE) ? 1 : 0); - LOG("- Auto Enables %u\n", (data & WR3_AUTO_ENABLES) ? 1 : 0); - LOG("- Receiver Bits/Character %u\n", get_rx_word_length()); + LOG("- Receiver Enable: %d\n", (data & WR3_RX_ENABLE) ? 1 : 0); + LOG("- Sync Char Load Inhibit %d\n", (data & WR3_SYNC_CHAR_LOAD_INHIBIT) ? 1 : 0); + LOG("- Address Search Mode %d\n", (data & WR3_ADDRESS_SEARCH_MODE) ? 1 : 0); + LOG("- Rx CRC Enable %d\n", (data & WR3_RX_CRC_ENABLE) ? 1 : 0); + LOG("- Enter Hunt Mode %d\n", (data & WR3_ENTER_HUNT_MODE) ? 1 : 0); + LOG("- Auto Enables %d\n", (data & WR3_AUTO_ENABLES) ? 1 : 0); + LOG("- Receiver Bits/Character %d\n", get_rx_word_length()); if ((m_wr3 & WR3_ENTER_HUNT_MODE) || ((m_wr3 & WR3_RX_ENABLE) == 0)) { @@ -1998,7 +1992,7 @@ void z80scc_channel::do_sccreg_wr3(uint8_t data) void z80scc_channel::do_sccreg_wr4(uint8_t data) { - LOG("%s(%02x) Setting up asynchronous frame format and clock\n", FUNCNAME, data); + LOG("%s(%02x): Setting up asynchronous frame format and clock\n", FUNCNAME, data); if (data == m_wr4) { LOG("- suppressing reinit of Tx as write to wr4 is identical to previous value\n"); @@ -2013,7 +2007,7 @@ void z80scc_channel::do_sccreg_wr4(uint8_t data) (data & WR4_BIT4 ? "External Sync Mode - /SYNC is used as input!" : "SDLC - not implemented") : (data & WR4_BIT4 ? "16 bit" : "8 bit")) : "Disabled"); - LOG("- Clock Mode: %uX\n", get_clock_mode()); + LOG("- Clock Mode: %dX\n", get_clock_mode()); update_serial(); safe_transmit_register_reset(); receive_register_reset(); @@ -2022,19 +2016,15 @@ void z80scc_channel::do_sccreg_wr4(uint8_t data) void z80scc_channel::do_sccreg_wr5(uint8_t data) { - LOG("%s(%02x) Setting up the transmitter\n", FUNCNAME, data); - if (data == m_wr5) - { - LOG("- suppressing reinit of Tx as write to wr5 is identical to previous value\n"); - } - else + if (data != m_wr5) { + LOG("%s(%02x): Setting up the transmitter\n", FUNCNAME, data); m_wr5 = data; - LOG("- Transmitter Enable %u\n", (data & WR5_TX_ENABLE) ? 1 : 0); - LOG("- Transmitter Bits/Character %u\n", get_tx_word_length()); - LOG("- Send Break %u\n", (data & WR5_SEND_BREAK) ? 1 : 0); - LOG("- Request to Send %u\n", (data & WR5_RTS) ? 1 : 0); - LOG("- Data Terminal Ready %u\n", (data & WR5_DTR) ? 1 : 0); + LOG("- Transmitter Enable %d\n", (data & WR5_TX_ENABLE) ? 1 : 0); + LOG("- Transmitter Bits/Character %d\n", get_tx_word_length()); + LOG("- Send Break %d\n", (data & WR5_SEND_BREAK) ? 1 : 0); + LOG("- Request to Send %d\n", (data & WR5_RTS) ? 1 : 0); + LOG("- Data Terminal Ready %d\n", (data & WR5_DTR) ? 1 : 0); update_serial(); safe_transmit_register_reset(); update_rts(); // Will also update DTR accordingly @@ -2045,20 +2035,20 @@ void z80scc_channel::do_sccreg_wr5(uint8_t data) void z80scc_channel::do_sccreg_wr6(uint8_t data) { - LOG("%s(%02x) Transmit sync\n", FUNCNAME, data); + LOG("%s(%02x): Transmit sync\n", FUNCNAME, data); m_sync_pattern = (m_sync_pattern & 0xff00) | data; } void z80scc_channel::do_sccreg_wr7(uint8_t data) { - LOG("%s(%02x) Receive sync\n", FUNCNAME, data); + LOG("%s(%02x): Receive sync\n", FUNCNAME, data); m_sync_pattern = (data << 8) | (m_sync_pattern & 0xff); } /* WR8 is the transmit buffer register */ void z80scc_channel::do_sccreg_wr8(uint8_t data) { - LOGTX("%s(%02x) \"%s\": %c : Transmit Buffer write %02x\n", FUNCNAME, data, owner()->tag(), 'A' + m_index, data); + LOGTX("%s(%02x): Transmit Buffer write\n", FUNCNAME, data); data_write(data); } @@ -2073,18 +2063,18 @@ void z80scc_channel::do_sccreg_wr9(uint8_t data) switch (data & WR9_CMD_MASK) { case WR9_CMD_NORESET: - LOG("\"%s\": %c : Master Interrupt Control - No reset %02x\n", owner()->tag(), 'A' + m_index, data); + LOG("Master Interrupt Control - No reset %02x\n", data); break; case WR9_CMD_CHNB_RESET: - LOGINT("\"%s\": %c : Master Interrupt Control - Channel B reset %02x\n", owner()->tag(), 'A' + m_index, data); + LOGINT("Master Interrupt Control - Channel B reset %02x\n", data); m_uart->m_chanB->reset(); break; case WR9_CMD_CHNA_RESET: - LOGINT("\"%s\": %c : Master Interrupt Control - Channel A reset %02x\n", owner()->tag(), 'A' + m_index, data); + LOGINT("Master Interrupt Control - Channel A reset %02x\n", data); m_uart->m_chanA->reset(); break; case WR9_CMD_HW_RESET: - LOGINT("\"%s\": %c : Master Interrupt Control - Device reset %02x\n", owner()->tag(), 'A' + m_index, data); + LOGINT("Master Interrupt Control - Device reset %02x\n", data); /*"The effects of this command are identical to those of a hardware reset, except that the Shift Right/Shift Left bit is not changed and the MIE, Status High/Status Low and DLC bits take the programmed values that accompany this command." */ @@ -2106,6 +2096,7 @@ void z80scc_channel::do_sccreg_wr9(uint8_t data) break; default: logerror("Code is broken in WR9, please report!\n"); + break; } } @@ -2114,7 +2105,7 @@ void z80scc_channel::do_sccreg_wr9(uint8_t data) void z80scc_channel::do_sccreg_wr10(uint8_t data) { m_wr10 = data; - LOG("\"%s\": %c : %s Misc Tx/Rx Control %02x - not implemented \n", owner()->tag(), 'A' + m_index, FUNCNAME, data); + LOG("%s: Misc Tx/Rx Control %02x - not implemented\n", FUNCNAME, data); LOG("- 6/8 bit sync %d\n", data & WR10_8_6_BIT_SYNC ? 1 : 0); LOG("- Loop Mode %d\n", data & WR10_LOOP_MODE ? 1 : 0); LOG("- Abort/Flag on underrun %d\n", data & WR10_ABORT_FLAG_UNDERRUN ? 1 : 0); @@ -2131,7 +2122,7 @@ receive and transmit clocks, the type of signal on the /SYNC and /RTxC pins, and the /TRxC pin.*/ void z80scc_channel::do_sccreg_wr11(uint8_t data) { - LOG("\"%s\": %c : %s Clock Mode Control %02x\n", owner()->tag(), 'A' + m_index, FUNCNAME, data); + LOG("%s: Clock Mode Control %02x\n", FUNCNAME, data); m_wr11 = data; /*Bit 7: This bit controls the type of input signal the SCC expects to see on the /RTxC pin. If this bit is set to 0, the SCC expects a TTL-compatible signal as an input to this pin. If this bit is set to 1, the SCC @@ -2147,14 +2138,12 @@ void z80scc_channel::do_sccreg_wr11(uint8_t data) interfere with any of the modes of operation in the SCC, but simply control a multiplexer just before the internal receive clock input. A hardware reset forces the receive clock to come from the /RTxC pin.*/ - LOG("- Receive clock source is: "); switch (data & WR11_RCVCLK_SRC_MASK) { - case WR11_RCVCLK_SRC_RTXC: LOG("RTxC - not implemented\n"); break; - case WR11_RCVCLK_SRC_TRXC: LOG("TRxC - not implemented\n"); break; - case WR11_RCVCLK_SRC_BR: LOG("Baudrate Generator\n"); break; - case WR11_RCVCLK_SRC_DPLL: LOG("DPLL - not implemented\n"); break; - default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */ + case WR11_RCVCLK_SRC_RTXC: LOG("Receive clock source is RTxC - not implemented\n"); break; + case WR11_RCVCLK_SRC_TRXC: LOG("Receive clock source is TRxC - not implemented\n"); break; + case WR11_RCVCLK_SRC_BR: LOG("Receive clock source is Baudrate Generator\n"); break; + case WR11_RCVCLK_SRC_DPLL: LOG("Receive clock source is DPLL - not implemented\n"); break; } /*Bits 4 and 3: Transmit Clock select bits 1 and 0. These bits determine the source of the transmit clock as listed in Table . They do not interfere with @@ -2163,14 +2152,12 @@ void z80scc_channel::do_sccreg_wr11(uint8_t data) degrees the output of the DPLL used by the receiver. This makes the received and transmitted bit cells occur simultaneously, neglecting delays. A hardware reset selects the /TRxC pin as the source of the transmit clocks.*/ - LOG("- Transmit clock source is: "); switch (data & WR11_TRACLK_SRC_MASK) { - case WR11_TRACLK_SRC_RTXC: LOG("RTxC - not implemented\n"); break; - case WR11_TRACLK_SRC_TRXC: LOG("TRxC - not implemented\n"); break; - case WR11_TRACLK_SRC_BR: LOG("Baudrate Generator\n"); break; - case WR11_TRACLK_SRC_DPLL: LOG("DPLL - not implemented\n"); break; - default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */ + case WR11_TRACLK_SRC_RTXC: LOG("Transmit clock source is RTxC - not implemented\n"); break; + case WR11_TRACLK_SRC_TRXC: LOG("Transmit clock source is TRxC - not implemented\n"); break; + case WR11_TRACLK_SRC_BR: LOG("Transmit clock source is Baudrate Generator\n"); break; + case WR11_TRACLK_SRC_DPLL: LOG("Transmit clock source is DPLL - not implemented\n"); break; } /* Bit 2: TRxC Pin I/O control bit This bit determines the direction of the /TRxC pin. If this bit is set to 1, the /TRxC pin is an output @@ -2178,7 +2165,6 @@ void z80scc_channel::do_sccreg_wr11(uint8_t data) transmit clock is programmed to come from the /TRxC pin, /TRxC is an input, regardless of the state of this bit. The /TRxC pin is also an input if this bit is set to 0. A hardware reset forces this bit to 0.*/ - LOG("- TRxC pin is %s\n", data & WR11_TRXC_DIRECTION ? "Output" : "Input"); /*Bits 1 and 0: /TRxC Output Source select bits 1 and 0 These bits determine the signal to be echoed out of the SCC via the /TRxC pin as listed in Table on page 167. No signal is produced if /TRxC has been programmed as the source of either the @@ -2188,16 +2174,16 @@ void z80scc_channel::do_sccreg_wr11(uint8_t data) Hardware reset selects the XTAL oscillator as the output source*/ if (data & WR11_TRXC_DIRECTION) { - LOG("- TRxC pin output is: "); switch (data & WR11_TRXSRC_SRC_MASK) { - case WR11_TRXSRC_SRC_XTAL: LOG("the Oscillator - not implemented\n"); break; - case WR11_TRXSRC_SRC_TRA: LOG("Transmit clock - not implemented\n"); break; - case WR11_TRXSRC_SRC_BR: LOG("Baudrate Generator\n"); break; - case WR11_TRXSRC_SRC_DPLL: LOG("DPLL - not implemented\n"); break; - default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */ + case WR11_TRXSRC_SRC_XTAL: LOG("TRxC output is the Oscillator - not implemented\n"); break; + case WR11_TRXSRC_SRC_TRA: LOG("TRxC output is Transmit clock - not implemented\n"); break; + case WR11_TRXSRC_SRC_BR: LOG("TRxC output is Baudrate Generator\n"); break; + case WR11_TRXSRC_SRC_DPLL: LOG("TRxC output is DPLL - not implemented\n"); break; } } + else + LOG("TRxC pin is Input\n"); } /*WR12 contains the lower byte of the time constant for the baud rate generator. The time constant @@ -2219,7 +2205,7 @@ void z80scc_channel::do_sccreg_wr12(uint8_t data) { m_wr12 = data; update_serial(); - LOG("\"%s\": %c : %s %02x Low byte of Time Constant for Baudrate generator\n", owner()->tag(), 'A' + m_index, FUNCNAME, data); + LOG("%s(%02x): Low byte of Time Constant for Baudrate generator\n", FUNCNAME, data); } /* WR13 contains the upper byte of the time constant for the baud rate generator. */ @@ -2227,7 +2213,7 @@ void z80scc_channel::do_sccreg_wr13(uint8_t data) { m_wr13 = data; update_serial(); - LOG("\"%s\": %c : %s %02x High byte of Time Constant for Baudrate generator\n", owner()->tag(), 'A' + m_index, FUNCNAME, data); + LOG("%s(%02x): High byte of Time Constant for Baudrate generator\n", FUNCNAME, data); } /* @@ -2237,7 +2223,7 @@ void z80scc_channel::do_sccreg_wr14(uint8_t data) switch (data & WR14_DPLL_CMD_MASK) { case WR14_CMD_NULL: - LOG("\"%s\": %c : %s Misc Control Bits Null Command %02x\n", owner()->tag(), 'A' + m_index, FUNCNAME, data); + LOG("%s: Misc Control Bits Null Command %02x\n", FUNCNAME, data); break; case WR14_CMD_ESM: /* Issuing this command causes the DPLL to enter the Search mode, where the DPLL searches for a locking edge in the @@ -2259,45 +2245,44 @@ void z80scc_channel::do_sccreg_wr14(uint8_t data) see an edge during the expected window, the one clock missing bit in RR10 is set. If the DPLL does not see an edge after two successive attempts, the two clocks missing bits in RR10 are set and the DPLL automatically enters the Search mode. This command resets both clocks missing latches.*/ - LOG("\"%s\": %c : %s Misc Control Bits Enter Search Mode Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME); + LOG("%s: Misc Control Bits Enter Search Mode Command - not implemented\n", FUNCNAME); break; case WR14_CMD_RMC: /* Issuing this command disables the DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode state */ - LOG("\"%s\": %c : %s Misc Control Bits Reset Missing Clocks Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME); + LOG("%s: Misc Control Bits Reset Missing Clocks Command - not implemented\n", FUNCNAME); break; case WR14_CMD_DISABLE_DPLL: /* Issuing this command disables the DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode state.*/ - LOG("\"%s\": %c : %s Misc Control Bits Disable DPLL Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME); + LOG("%s: Misc Control Bits Disable DPLL Command - not implemented\n", FUNCNAME); break; case WR14_CMD_SS_BRG: /* Issuing this command forces the clock for the DPLL to come from the output of the BRG. */ - LOG("\"%s\": %c : %s Misc Control Bits Baudrate Generator Input DPLL Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME); + LOG("%s: Misc Control Bits Baudrate Generator Input DPLL Command - not implemented\n", FUNCNAME); break; case WR14_CMD_SS_RTXC: /* Issuing the command forces the clock for the DPLL to come from the /RTxC pin or the crystal oscillator, depending on the state of the XTAL/no XTAL bit in WR11. This mode is selected by a channel or hardware reset*/ - LOG("\"%s\": %c : %s Misc Control Bits RTxC Input DPLL Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME); + LOG("%s: Misc Control Bits RTxC Input DPLL Command - not implemented\n", FUNCNAME); break; case WR14_CMD_SET_FM: /* This command forces the DPLL to operate in the FM mode and is used to recover the clock from FM or Manchester-Encoded data. (Manchester is decoded by placing the receiver in NRZ mode while the DPLL is in FM mode.)*/ - LOG("\"%s\": %c : %s Misc Control Bits Set FM Mode Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME); + LOG("%s: Misc Control Bits Set FM Mode Command - not implemented\n", FUNCNAME); break; case WR14_CMD_SET_NRZI: /* Issuing this command forces the DPLL to operate in the NRZI mode. This mode is also selected by a hardware or channel reset.*/ - LOG("\"%s\": %c : %s Mics Control Bits Set NRZI Mode Command - not implemented\n", owner()->tag(), 'A' + m_index, FUNCNAME); + LOG("%s: Misc Control Bits Set NRZI Mode Command - not implemented\n", FUNCNAME); break; default: - logerror("\"%s\": %c : %s Mics Control Bits command %02x - not implemented \n", owner()->tag(), 'A' + m_index, FUNCNAME, data); + logerror("%s: Misc Control Bits command %02x - not implemented\n", FUNCNAME, data); + break; } /* Based on baudrate code from 8530scc.cpp */ if ( !(m_wr14 & WR14_BRG_ENABLE) && (data & WR14_BRG_ENABLE) ) // baud rate generator being enabled? { - LOG("\"%s\": %c : %s Mics Control Bits Baudrate generator enabled with ", owner()->tag(), 'A' + m_index, FUNCNAME); + LOG("%s: Misc Control Bits Baudrate generator enabled with %s source\n", FUNCNAME, (data & WR14_BRG_SOURCE) ? "PCLK" : "external clock"); if (data & WR14_BRG_SOURCE) // Do we use the PCLK as baudrate source { - LOG(" - PCLK as source\n"); - #if Z80SCC_USE_LOCAL_BRG baudtimer->adjust(attotime::from_hz(rate), TIMER_ID_BAUD, attotime::from_hz(rate)); // Start the baudrate generator #if START_BIT_HUNT @@ -2305,10 +2290,6 @@ void z80scc_channel::do_sccreg_wr14(uint8_t data) #endif #endif } - else - { - LOG("external clock source\n"); - } } else if ( (m_wr14 & WR14_BRG_ENABLE) && !(data & WR14_BRG_ENABLE) ) // baud rate generator being disabled? { @@ -2330,8 +2311,8 @@ void z80scc_channel::do_sccreg_wr14(uint8_t data) #define WR15NO "not implemented" void z80scc_channel::do_sccreg_wr15(uint8_t data) { - LOG("%s(%02x) \"%s\": %c : External/Status Control Bits\n", - FUNCNAME, data, owner()->tag(), 'A' + m_index); + LOG("%s(%02x): External/Status Control Bits\n", + FUNCNAME, data); LOG("WR7 prime ints : %s\n", data & WR15_WR7PRIME ? WR15NO : "disabled"); LOG("Zero count ints : %s\n", data & WR15_ZEROCOUNT ? WR15NO : "disabled"); LOG("14 bit Status FIFO : %s\n", data & WR15_STATUS_FIFO ? WR15NO : "disabled"); @@ -2364,7 +2345,8 @@ void z80scc_channel::scc_register_write(uint8_t reg, uint8_t data) case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break; case REG_WR15_EXT_ST_INT_CTRL: do_sccreg_wr15(data); break; default: - logerror("\"%s\": %c : Unsupported WRx register:%02x\n", owner()->tag(), 'A' + m_index, reg); + logerror("Unsupported WRx register:%02x\n", reg); + break; } } @@ -2403,7 +2385,7 @@ void z80scc_channel::control_write(uint8_t data) m_wr0 &= ~regmask; } - LOGSETUP(" * %s %c Reg %02x <- %02x - %s\n", owner()->tag(), 'A' + m_index, reg, data, std::array + LOGSETUP(" * Reg %02x <- %02x - %s\n", reg, data, std::array {{ "Command register", "Tx/Rx Interrupt and Data Transfer Modes", "Interrupt Vector", "Rx Parameters and Control", "Tx/Rx Misc Parameters and Modes", "Tx Parameters and Controls", "Sync Characters or SDLC Address Field","Sync Character or SDLC Flag/Prime", "Tx Buffer", "Master Interrupt Control", "Miscellaneous Tx/Rx Control Bits", "Clock Mode Control", @@ -2420,7 +2402,7 @@ uint8_t z80scc_channel::data_read() { uint8_t data = 0; - LOGRCV("%s \"%s\": %c : Data Register Read: ", FUNCNAME, owner()->tag(), 'A' + m_index); + LOGRCV("%s: Data Register Read", FUNCNAME); if (m_rx_fifo_wp != m_rx_fifo_rp) { @@ -2467,7 +2449,6 @@ uint8_t z80scc_channel::data_read() } else { - LOG("data_read: Attempt to read out character from empty FIFO\n"); logerror("data_read: Attempt to read out character from empty FIFO\n"); } @@ -2513,13 +2494,12 @@ void z80scc_device::db_w(offs_t offset, uint8_t data) { m_chanB->data_write(data void z80scc_channel::data_write(uint8_t data) { /* Tx FIFO is full or...? */ - LOG("%s \"%s\": %c : Data Register Write: %02d '%c'\n", FUNCNAME, owner()->tag(), 'A' + m_index, data, isprint(data) ? data : ' '); + LOG("%s: Data Register Write: %02d '%c'\n", FUNCNAME, data, isprint(data) ? data : ' '); if ( !(m_rr0 & RR0_TX_BUFFER_EMPTY) && // NMOS/CMOS 1 slot "FIFO" is controlled by the TBE bit instead of fifo logic ( (m_tx_fifo_wp + 1 == m_tx_fifo_rp) || ( (m_tx_fifo_wp + 1 == m_tx_fifo_sz) && (m_tx_fifo_rp == 0) ))) { logerror("- TX FIFO is full, discarding data\n"); - LOGTX("- TX FIFO is full, discarding data\n"); } else // ..there is still room { @@ -2616,7 +2596,7 @@ void z80scc_channel::data_write(uint8_t data) //------------------------------------------------- void z80scc_channel::receive_data(uint8_t data) { - LOGRCV("\"%s\": %c : Received Data Byte '%c'/%02x put into FIFO\n", owner()->tag(), 'A' + m_index, isprint(data) ? data : ' ', data); + LOGRCV("Received Data Byte '%c'/%02x put into FIFO\n", isprint(data) ? data : ' ', data); if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) )) { @@ -2668,7 +2648,7 @@ void z80scc_channel::receive_data(uint8_t data) //------------------------------------------------- void z80scc_channel::cts_w(int state) { - LOG("\"%s\"%s: %c : CTS %u\n", owner()->tag(), FUNCNAME, 'A' + m_index, state); + LOG("%s(%d)\n", FUNCNAME, state); if ((m_rr0 & RR0_CTS) != (state ? 0 : RR0_CTS)) // SCC change detection logic { @@ -2705,7 +2685,7 @@ void z80scc_channel::cts_w(int state) //------------------------------------------------- void z80scc_channel::dcd_w(int state) { - LOGDCD("\"%s\": %c : DCD %u\n", owner()->tag(), 'A' + m_index, state); + LOGDCD("%s(%d)\n", FUNCNAME, state); if ((m_rr0 & RR0_DCD) != (state ? 0 : RR0_DCD)) // SCC change detection logic { @@ -2744,7 +2724,7 @@ void z80scc_channel::dcd_w(int state) //------------------------------------------------- void z80scc_channel::sync_w(int state) { - LOGSYNC("\"%s\": %c : SYNC %u\n", owner()->tag(), 'A' + m_index, state); + LOGSYNC("%s(%d)\n", FUNCNAME, state); /* * The /SYNC pin is a general purpose input whose state is reported in the @@ -2784,7 +2764,7 @@ void z80scc_channel::rxc_w(int state) { /* Support for external clock as source for BRG yet to be finished */ #if 0 - //LOG("\"%s\": %c : Receiver Clock Pulse\n", owner()->tag(), m_index + 'A'); + //LOG("Receiver Clock Pulse\n"); if ( ((m_wr3 & WR3_RX_ENABLE) | (m_wr5 & WR5_TX_ENABLE)) && m_wr14 & WR14_BRG_ENABLE) { if (!(m_wr14 & WR14_BRG_SOURCE)) // Is the Baud rate Generator driven by RTxC? @@ -2834,7 +2814,7 @@ void z80scc_channel::rxc_w(int state) //------------------------------------------------- void z80scc_channel::txc_w(int state) { - //LOG("\"%s\": %c : Transmitter Clock Pulse\n", owner()->tag(), m_index + 'A'); + //LOG("Transmitter Clock Pulse\n"); if (m_wr5 & WR5_TX_ENABLE) { int clocks = get_clock_mode(); @@ -2917,7 +2897,7 @@ void z80scc_channel::update_serial() parity = PARITY_NONE; } - LOG("%s \"%s \"Channel %c setting data frame %d+%d%c%d\n", FUNCNAME, owner()->tag(), 'A' + m_index, 1, + LOG("%s: setting data frame %d+%d%c%d\n", FUNCNAME, 1, data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2); set_data_frame(1, data_bit_count, parity, stop_bits); @@ -2964,7 +2944,7 @@ void z80scc_channel::update_serial() if (m_txc > 0 && !(m_wr14 & WR14_BRG_ENABLE)) { set_tra_rate(m_txc / clocks); - LOG(" - Transmit clock: %d mode: %d rate: %d/%xh\n", m_rxc, clocks, m_rxc / clocks, m_rxc / clocks); + LOG(" - Transmit clock: %d mode: %d rate: %d/%xh\n", m_txc, clocks, m_txc / clocks, m_txc / clocks); } } -- cgit v1.2.3