diff options
Diffstat (limited to 'src/mame/machine/interpro_ioga.h')
-rw-r--r-- | src/mame/machine/interpro_ioga.h | 86 |
1 files changed, 73 insertions, 13 deletions
diff --git a/src/mame/machine/interpro_ioga.h b/src/mame/machine/interpro_ioga.h index 94e282a9e2c..530790cb3e0 100644 --- a/src/mame/machine/interpro_ioga.h +++ b/src/mame/machine/interpro_ioga.h @@ -19,9 +19,16 @@ devcb = &interpro_ioga_device::static_set_dma_r_callback(*device, _channel, DEVCB_##_dma_r); \ devcb = &interpro_ioga_device::static_set_dma_w_callback(*device, _channel, DEVCB_##_dma_w); +#define MCFG_INTERPRO_IOGA_DMA_SERIAL_CB(_channel, _dma_r, _dma_w) \ + devcb = &interpro_ioga_device::static_set_dma_serial_r_callback(*device, _channel, DEVCB_##_dma_r); \ + devcb = &interpro_ioga_device::static_set_dma_serial_w_callback(*device, _channel, DEVCB_##_dma_w); + #define MCFG_INTERPRO_IOGA_FDCTC_CB(_tc) \ devcb = &interpro_ioga_device::static_set_fdc_tc_callback(*device, DEVCB_##_tc); +#define MCFG_INTERPRO_IOGA_ETH_CA_CB(_ca) \ + devcb = &interpro_ioga_device::static_set_eth_ca_callback(*device, DEVCB_##_ca); + #define MCFG_INTERPRO_IOGA_DMA_BUS(_mmu, _space) // timer 0 seem to be a 60Hz cycle @@ -54,11 +61,15 @@ #define IOGA_INTERRUPT_SOFT_LO 4 #define IOGA_INTERRUPT_SOFT_HI 5 -#define IOGA_DMA_CHANNELS 4 -#define IOGA_DMA_PLOTTER 0 -#define IOGA_DMA_SCSI 1 -#define IOGA_DMA_FLOPPY 2 -#define IOGA_DMA_SERIAL 3 +#define IOGA_DMA_CHANNELS 3 +#define IOGA_DMA_PLOTTER 0 +#define IOGA_DMA_SCSI 1 +#define IOGA_DMA_FLOPPY 2 + +#define IOGA_DMA_SERIAL_CHANNELS 3 +#define IOGA_DMA_SERIAL0 0 +#define IOGA_DMA_SERIAL1 1 +#define IOGA_DMA_SERIAL2 2 class interpro_ioga_device : public device_t { @@ -71,7 +82,11 @@ public: template<class _Object> static devcb_base &static_set_dma_r_callback(device_t &device, int channel, _Object object) { return downcast<interpro_ioga_device &>(device).m_dma_channel[channel].device_r.set_callback(object); } template<class _Object> static devcb_base &static_set_dma_w_callback(device_t &device, int channel, _Object object) { return downcast<interpro_ioga_device &>(device).m_dma_channel[channel].device_w.set_callback(object); } + template<class _Object> static devcb_base &static_set_dma_serial_r_callback(device_t &device, int channel, _Object object) { return downcast<interpro_ioga_device &>(device).m_dma_serial_channel[channel].device_r.set_callback(object); } + template<class _Object> static devcb_base &static_set_dma_serial_w_callback(device_t &device, int channel, _Object object) { return downcast<interpro_ioga_device &>(device).m_dma_serial_channel[channel].device_w.set_callback(object); } + template<class _Object> static devcb_base &static_set_fdc_tc_callback(device_t &device, _Object object) { return downcast<interpro_ioga_device &>(device).m_fdc_tc_func.set_callback(object); } + template<class _Object> static devcb_base &static_set_eth_ca_callback(device_t &device, _Object object) { return downcast<interpro_ioga_device &>(device).m_eth_ca_func.set_callback(object); } virtual DECLARE_ADDRESS_MAP(map, 32); @@ -97,6 +112,10 @@ public: DECLARE_WRITE_LINE_MEMBER(drq_scsi) { drq(state, IOGA_DMA_SCSI); } DECLARE_WRITE_LINE_MEMBER(drq_floppy) { drq(state, IOGA_DMA_FLOPPY); } + DECLARE_WRITE_LINE_MEMBER(drq_serial0) { drq_serial(state, IOGA_DMA_SERIAL0); } + DECLARE_WRITE_LINE_MEMBER(drq_serial1) { drq_serial(state, IOGA_DMA_SERIAL1); } + DECLARE_WRITE_LINE_MEMBER(drq_serial2) { drq_serial(state, IOGA_DMA_SERIAL2); } + enum eth_remap_mask { ETH_REMAP_CHA_FLUSH = 0x00000008, @@ -123,7 +142,7 @@ public: enum eth_control_mask { - ETH_CA = 0x00000001, + ETH_CA = 0x00000001, // channel attention ETH_MAPEN = 0x00000002, ETH_REMAP_CHC_BUF = 0x00000010, ETH_REMAP_CHC_QUAD = 0x00000020, @@ -210,7 +229,7 @@ public: DMA_CTRL_BERR = 0x00400000, // bus error DMA_CTRL_ERR = 0x00800000, // checked for in scsi isr - DMA_CTRL_BUSY = 0x01000000, // cleared when command complete (maybe bus grant required?) + DMA_CTRL_BGR = 0x01000000, // cleared when command complete (maybe bus grant required?) DMA_CTRL_WAIT = 0x02000000, // waiting for bus grant DMA_CTRL_X = 0x04000000, // set during fdc dma? @@ -226,8 +245,26 @@ public: DECLARE_READ32_MEMBER(dma_floppy_r) { return dma_r(space, offset, mem_mask, IOGA_DMA_FLOPPY); } DECLARE_WRITE32_MEMBER(dma_floppy_w) { dma_w(space, offset, data, mem_mask, IOGA_DMA_FLOPPY); } - DECLARE_READ32_MEMBER(dma_serial_r); - DECLARE_WRITE32_MEMBER(dma_serial_w); + DECLARE_READ32_MEMBER(dma_serial0_addr_r) { return dma_serial_addr_r(space, offset, mem_mask, IOGA_DMA_SERIAL0); } + DECLARE_WRITE32_MEMBER(dma_serial0_addr_w) { dma_serial_addr_w(space, offset, data, mem_mask, IOGA_DMA_SERIAL0); } + DECLARE_READ16_MEMBER(dma_serial0_count_r) { return dma_serial_count_r(space, offset, mem_mask, IOGA_DMA_SERIAL0); } + DECLARE_WRITE16_MEMBER(dma_serial0_count_w) { dma_serial_count_w(space, offset, data, mem_mask, IOGA_DMA_SERIAL0); } + DECLARE_READ16_MEMBER(dma_serial0_ctrl_r) { return dma_serial_ctrl_r(space, offset, mem_mask, IOGA_DMA_SERIAL0); } + DECLARE_WRITE16_MEMBER(dma_serial0_ctrl_w) { dma_serial_ctrl_w(space, offset, data, mem_mask, IOGA_DMA_SERIAL0); } + + DECLARE_READ32_MEMBER(dma_serial1_addr_r) { return dma_serial_addr_r(space, offset, mem_mask, IOGA_DMA_SERIAL1); } + DECLARE_WRITE32_MEMBER(dma_serial1_addr_w) { dma_serial_addr_w(space, offset, data, mem_mask, IOGA_DMA_SERIAL1); } + DECLARE_READ16_MEMBER(dma_serial1_count_r) { return dma_serial_count_r(space, offset, mem_mask, IOGA_DMA_SERIAL1); } + DECLARE_WRITE16_MEMBER(dma_serial1_count_w) { dma_serial_count_w(space, offset, data, mem_mask, IOGA_DMA_SERIAL1); } + DECLARE_READ16_MEMBER(dma_serial1_ctrl_r) { return dma_serial_ctrl_r(space, offset, mem_mask, IOGA_DMA_SERIAL1); } + DECLARE_WRITE16_MEMBER(dma_serial1_ctrl_w) { dma_serial_ctrl_w(space, offset, data, mem_mask, IOGA_DMA_SERIAL1); } + + DECLARE_READ32_MEMBER(dma_serial2_addr_r) { return dma_serial_addr_r(space, offset, mem_mask, IOGA_DMA_SERIAL2); } + DECLARE_WRITE32_MEMBER(dma_serial2_addr_w) { dma_serial_addr_w(space, offset, data, mem_mask, IOGA_DMA_SERIAL2); } + DECLARE_READ16_MEMBER(dma_serial2_count_r) { return dma_serial_count_r(space, offset, mem_mask, IOGA_DMA_SERIAL2); } + DECLARE_WRITE16_MEMBER(dma_serial2_count_w) { dma_serial_count_w(space, offset, data, mem_mask, IOGA_DMA_SERIAL2); } + DECLARE_READ16_MEMBER(dma_serial2_ctrl_r) { return dma_serial_ctrl_r(space, offset, mem_mask, IOGA_DMA_SERIAL2); } + DECLARE_WRITE16_MEMBER(dma_serial2_ctrl_w) { dma_serial_ctrl_w(space, offset, data, mem_mask, IOGA_DMA_SERIAL2); } DECLARE_READ32_MEMBER(dma_plotter_eosl_r) { return m_dma_plotter_eosl; } DECLARE_WRITE32_MEMBER(dma_plotter_eosl_w) { m_dma_plotter_eosl = data; } @@ -278,8 +315,10 @@ private: void interrupt_clock(); void dma_clock(); + void dma_serial_clock(); void drq(int state, int channel); + void drq_serial(int state, int channel); devcb_write_line m_out_nmi_func; devcb_write_line m_out_irq_func; address_space *m_memory_space; @@ -290,7 +329,8 @@ private: WAIT, COMMAND, TRANSFER, - COMPLETE + COMPLETE, + FINAL }; // dma channels struct dma @@ -300,6 +340,7 @@ private: u32 transfer_count; u32 control; + int drq_state; dma_states state; devcb_read8 device_r; devcb_write8 device_w; @@ -310,13 +351,25 @@ private: } m_dma_channel[IOGA_DMA_CHANNELS]; u32 m_dma_plotter_eosl; - struct serial_dma + // dma serial channels + struct dma_serial { u32 address; - u32 control; - } m_dma_serial[3]; + u16 count; + u16 control; + + int drq_state; + dma_states state; + devcb_read8 device_r; + devcb_write8 device_w; + + const u16 arb_mask; + const int channel; + const char *name; + } m_dma_serial_channel[IOGA_DMA_SERIAL_CHANNELS]; devcb_write_line m_fdc_tc_func; + devcb_write_line m_eth_ca_func; u32 m_active_interrupt_type; u32 m_active_interrupt_number; @@ -338,6 +391,13 @@ private: u32 dma_r(address_space &space, offs_t offset, u32 mem_mask, int channel); void dma_w(address_space &space, offs_t offset, u32 data, u32 mem_mask, int channel); + u32 dma_serial_addr_r(address_space &space, offs_t offset, u32 mem_mask, int channel) { return m_dma_serial_channel[channel].address; } + void dma_serial_addr_w(address_space &space, offs_t offset, u32 data, u32 mem_mask, int channel); + u16 dma_serial_count_r(address_space &space, offs_t offset, u16 mem_mask, int channel) { return m_dma_serial_channel[channel].count; } + void dma_serial_count_w(address_space &space, offs_t offset, u16 data, u16 mem_mask, int channel); + u16 dma_serial_ctrl_r(address_space &space, offs_t offset, u16 mem_mask, int channel) { return m_dma_serial_channel[channel].control; } + void dma_serial_ctrl_w(address_space &space, offs_t offset, u16 data, u16 mem_mask, int channel); + u16 m_arbctl; u32 m_error_address; |