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Diffstat (limited to 'src/mame/machine/hpc3.h')
-rw-r--r--src/mame/machine/hpc3.h117
1 files changed, 81 insertions, 36 deletions
diff --git a/src/mame/machine/hpc3.h b/src/mame/machine/hpc3.h
index aa59275eb9d..3630cbf9058 100644
--- a/src/mame/machine/hpc3.h
+++ b/src/mame/machine/hpc3.h
@@ -12,6 +12,7 @@
#pragma once
#include "machine/hal2.h"
+#include "machine/edlc.h"
class hpc3_device : public device_t, public device_memory_interface
{
@@ -41,15 +42,8 @@ public:
template <typename T> void set_gio64_space(T &&tag, int spacenum) { m_gio64_space.set_tag(std::forward<T>(tag), spacenum); }
template <typename T> void set_hal2_tag(T &&tag) { m_hal2.set_tag(std::forward<T>(tag)); }
+ template <typename T> void set_enet(T &&tag) { m_enet.set_tag(std::forward<T>(tag)); }
- auto enet_rd_cb() { return m_enet_rd_cb.bind(); }
- auto enet_wr_cb() { return m_enet_wr_cb.bind(); }
- auto enet_rxrd_cb() { return m_enet_rxrd_cb.bind(); }
- auto enet_txwr_cb() { return m_enet_txwr_cb.bind(); }
- auto enet_d8_rd_cb() { return m_enet_d8_rd_cb.bind(); }
- auto enet_d8_wr_cb() { return m_enet_d8_wr_cb.bind(); }
- auto enet_reset_cb() { return m_enet_reset_cb.bind(); }
- auto enet_loopback_cb() { return m_enet_loopback_cb.bind(); }
auto enet_intr_out_cb() { return m_enet_intr_out_cb.bind(); }
template <int N> auto hd_rd_cb() { return m_hd_rd_cb[N].bind(); }
template <int N> auto hd_wr_cb() { return m_hd_wr_cb[N].bind(); }
@@ -67,11 +61,8 @@ public:
void map(address_map &map);
- DECLARE_WRITE_LINE_MEMBER(enet_txrdy_w);
- DECLARE_WRITE_LINE_MEMBER(enet_rxrdy_w);
- DECLARE_WRITE_LINE_MEMBER(enet_rxdc_w);
- DECLARE_WRITE_LINE_MEMBER(enet_txret_w);
- DECLARE_WRITE_LINE_MEMBER(enet_intr_in_w);
+ void enet_rxrdy_w(int state);
+ void enet_intr_in_w(int state);
DECLARE_WRITE_LINE_MEMBER(scsi0_drq);
DECLARE_WRITE_LINE_MEMBER(scsi1_drq);
@@ -128,6 +119,10 @@ protected:
void scsi_drq(bool state, int channel);
//void scsi_dma(int channel);
+ void enet_transmit(void *ptr = nullptr, int param = 0);
+ void enet_misc_w(u32 data);
+ bool enet_rx_bc_dec(unsigned const count = 1);
+
static const device_timer_id TIMER_PBUS_DMA = 0;
struct pbus_dma_t
@@ -187,15 +182,8 @@ protected:
required_address_space m_gio64_space;
address_space *m_pio_space[10];
required_device<hal2_device> m_hal2;
+ required_device<seeq80c03_device> m_enet;
- devcb_read8 m_enet_rd_cb;
- devcb_write8 m_enet_wr_cb;
- devcb_read8 m_enet_rxrd_cb;
- devcb_write8 m_enet_txwr_cb;
- devcb_read_line m_enet_d8_rd_cb;
- devcb_write_line m_enet_d8_wr_cb;
- devcb_write_line m_enet_reset_cb;
- devcb_write_line m_enet_loopback_cb;
devcb_write_line m_enet_intr_out_cb;
devcb_read8::array<2> m_hd_rd_cb;
devcb_write8::array<2> m_hd_wr_cb;
@@ -230,21 +218,6 @@ protected:
bool m_active;
};
- struct enet_dma_t
- {
- uint32_t m_cbp;
- uint32_t m_nbdp;
- uint32_t m_bc;
- uint32_t m_ctrl;
- uint32_t m_gio_fifo_ptr;
- uint32_t m_dev_fifo_ptr;
- };
-
- enet_dma_t m_enet_dma[2];
- uint32_t m_enet_reset;
- uint32_t m_enet_dmacfg;
- uint32_t m_enet_piocfg;
-
scsi_dma_t m_scsi_dma[2];
pbus_dma_t m_pbus_dma[8];
uint32_t m_pio_config[10];
@@ -252,6 +225,78 @@ protected:
std::unique_ptr<uint32_t[]> m_pbus_fifo;
std::unique_ptr<uint32_t[]> m_scsi_fifo[2];
std::unique_ptr<uint32_t[]> m_enet_fifo[2];
+
+private:
+ emu_timer *m_enet_tx_timer;
+
+ enum enet_dma_rx_ctrl : u32
+ {
+ RXC_ST = 0x0000'00bf, // edlc receive status
+ RXC_LC = 0x0000'0040, // late receive collision
+ RXC_LE = 0x0000'0100, // receive little endian
+ RXC_CA = 0x0000'0200, // receive channel active
+ RXC_CAM = 0x0000'0400, // receive channel active mask
+ RXC_RBO = 0x0000'0800, // receive buffer overflow
+
+ // individual receive status bits
+ RXC_ST_V = 0x0000'0001, // received frame with overflow error
+ RXC_ST_C = 0x0000'0002, // received frame with crc error
+ RXC_ST_D = 0x0000'0004, // received frame with dribble error
+ RXC_ST_S = 0x0000'0008, // received short frame
+ RXC_ST_E = 0x0000'0010, // received end of frame
+ RXC_ST_G = 0x0000'0020, // received good frame
+ RXC_ST_O = 0x0000'0080, // old/new status
+ };
+ enum enet_dma_tx_ctrl : u32
+ {
+ TXC_ST = 0x0000'00ef, // edlc transmit status
+ TXC_LC = 0x0000'0010, // late transmit collision
+ TXC_LE = 0x0000'0100, // transmit little endian
+ TXC_CA = 0x0000'0200, // transmit channel active
+ TXC_CAM = 0x0000'0400, // transmit channel active mask
+
+ // individual transmit status bits
+ TXC_ST_U = 0x0000'0001, // transmit underflow
+ TXC_ST_C = 0x0000'0002, // transmit collision
+ TXC_ST_R = 0x0000'0004, // 16 transmission attempts
+ TXC_ST_S = 0x0000'0008, // transmission successful
+ TXC_ST_O = 0x0000'0080, // old/new status
+ };
+ enum enet_dma_bc : u32
+ {
+ BC_BC = 0x0000'3fff, // byte count
+ BC_TXD = 0x0000'8000, // transmit done
+ BC_IPG = 0x00ff'0000, // inter-packet gap
+ BC_XIE = 0x2000'0000, // transmit interrupt enable
+ BC_EOXP = 0x4000'0000, // end of packet
+ BC_EOX = 0x8000'0000, // end of descriptor chain
+ };
+ enum enet_enet_misc : u32
+ {
+ MISC_RESET = 0x0000'0001, // channel reset
+ MISC_INT = 0x0000'0002, // interrupt
+ MISC_LOOPBACK = 0x0000'0004, // loopback
+ };
+
+ // ethernet registers
+ u32 m_enet_rx_cbp; // current receive buffer pointer
+ u32 m_enet_rx_nbdp; // next receive buffer descriptor pointer
+ u32 m_enet_rx_bc; // receive byte count
+ u32 m_enet_rx_ctrl; // receive status
+ u32 m_enet_rx_gio; // receive gio fifo pointer
+ u32 m_enet_rx_dev; // receive device fifo pointer
+ u32 m_enet_misc; // reset, clear interrupt, loopback
+ u32 m_enet_piocfg; // pio configuration
+ u32 m_enet_dmacfg; // dma configuration
+ u32 m_enet_tx_cbp; // current transmit buffer pointer
+ u32 m_enet_tx_nbdp; // next transmit buffer descriptor pointer
+ u32 m_enet_tx_bc; // transmit byte count
+ u32 m_enet_tx_ctrl; // transmit status
+ u32 m_enet_tx_gio; // transmit gio fifo pointer
+ u32 m_enet_tx_dev; // transmit device fifo pointer
+ u32 m_enet_rx_cbdp; // current receive buffer descriptor pointer
+ u32 m_enet_tx_cpfbdp; // current/previous first transmit buffer descriptor pointer
+ u32 m_enet_tx_ppfbdp; // previous/previous? first transmit buffer descriptor pointer
};
DECLARE_DEVICE_TYPE(SGI_HPC3, hpc3_device)