summaryrefslogtreecommitdiffstatshomepage
path: root/src/mame/machine/electron.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'src/mame/machine/electron.cpp')
-rw-r--r--src/mame/machine/electron.cpp47
1 files changed, 47 insertions, 0 deletions
diff --git a/src/mame/machine/electron.cpp b/src/mame/machine/electron.cpp
index f4cf0a0f12c..13bac53f86a 100644
--- a/src/mame/machine/electron.cpp
+++ b/src/mame/machine/electron.cpp
@@ -144,12 +144,18 @@ TIMER_CALLBACK_MEMBER(electron_state::electron_tape_timer_handler)
READ8_MEMBER(electron_state::electron_mem_r)
{
+ /* The processor will run at 1MHz during an access cycle to the RAM */
+ m_maincpu->set_clock_scale(0.5f);
+
//waitforramsync();
return m_ram->read(offset);
}
WRITE8_MEMBER(electron_state::electron_mem_w)
{
+ /* The processor will run at 1MHz during an access cycle to the RAM */
+ m_maincpu->set_clock_scale(0.5f);
+
//waitforramsync();
m_ram->write(offset, data);
}
@@ -175,6 +181,9 @@ READ8_MEMBER(electron_state::electron_paged_r)
uint8_t data = 0;
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
switch (m_ula.rompage)
{
case 8:
@@ -205,17 +214,34 @@ READ8_MEMBER(electron_state::electron_paged_r)
WRITE8_MEMBER(electron_state::electron_paged_w)
{
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
m_exp->expbus_w(space, 0x8000 + offset, data);
}
+READ8_MEMBER(electron_state::electron_mos_r)
+{
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
+ return m_region_mos->base()[offset & 0x3fff];
+}
+
WRITE8_MEMBER(electron_state::electron_mos_w)
{
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
logerror("MOS: write %04x %02x\n", offset + 0xc000, data);
m_exp->expbus_w(space, 0xc000 + offset, data);
}
READ8_MEMBER(electron_state::electron_fred_r)
{
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
/* The Issue 4 ULA returns data from OS ROM, whereas Issue 6 ULA will return 0xff */
//logerror("FRED: read fc%02x\n", offset);
return m_exp->expbus_r(space, 0xfc00 + offset, 0xff);
@@ -223,12 +249,24 @@ READ8_MEMBER(electron_state::electron_fred_r)
WRITE8_MEMBER(electron_state::electron_fred_w)
{
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
//logerror("FRED: write fc%02x\n", offset);
m_exp->expbus_w(space, 0xfc00 + offset, data);
+
+ /* Master RAM Board */
+ if (offset == 0x7f && m_mrb.read_safe(0))
+ {
+
+ }
}
READ8_MEMBER(electron_state::electron_jim_r)
{
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
/* The Issue 4 ULA returns data from OS ROM, whereas Issue 6 ULA will return 0xff */
//logerror("JIM: read fd%02x\n", offset);
return m_exp->expbus_r(space, 0xfd00 + offset, 0xff);
@@ -236,12 +274,18 @@ READ8_MEMBER(electron_state::electron_jim_r)
WRITE8_MEMBER(electron_state::electron_jim_w)
{
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
//logerror("JIM: write fd%02x\n", offset);
m_exp->expbus_w(space, 0xfd00 + offset, data);
}
READ8_MEMBER(electron_state::electron_sheila_r)
{
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
/* The Issue 4 ULA returns data from OS ROM, whereas Issue 6 ULA will return 0xfe */
uint8_t data = 0xff;
@@ -267,6 +311,9 @@ static const uint16_t electron_screen_base[8] = { 0x3000, 0x3000, 0x3000, 0x4000
WRITE8_MEMBER(electron_state::electron_sheila_w)
{
+ /* The processor will run at 2MHz during an access cycle to the ROM */
+ m_maincpu->set_clock_scale(1.0f);
+
m_exp->expbus_w(space, 0xfe00 + offset, data);
int i = electron_palette_offset[(( offset >> 1 ) & 0x03)];