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path: root/src/mame/drivers/x68k.cpp
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Diffstat (limited to 'src/mame/drivers/x68k.cpp')
-rw-r--r--src/mame/drivers/x68k.cpp48
1 files changed, 24 insertions, 24 deletions
diff --git a/src/mame/drivers/x68k.cpp b/src/mame/drivers/x68k.cpp
index 2004230c84f..a2eca47417d 100644
--- a/src/mame/drivers/x68k.cpp
+++ b/src/mame/drivers/x68k.cpp
@@ -243,7 +243,7 @@ int x68k_state::read_mouse()
0xe98005 - Z8530 command port A
0xe98007 - Z8530 data port A (RS232)
*/
-READ16_MEMBER(x68k_state::scc_r )
+uint16_t x68k_state::scc_r(offs_t offset)
{
offset %= 4;
switch(offset)
@@ -261,7 +261,7 @@ READ16_MEMBER(x68k_state::scc_r )
}
}
-WRITE16_MEMBER(x68k_state::scc_w )
+void x68k_state::scc_w(offs_t offset, uint16_t data)
{
offset %= 4;
@@ -595,7 +595,7 @@ void x68k_state::ppi_port_c_w(uint8_t data)
// NEC uPD72065 at 0xe94000
-WRITE16_MEMBER(x68k_state::fdc_w)
+void x68k_state::fdc_w(offs_t offset, uint16_t data)
{
unsigned int drive, x;
switch(offset)
@@ -639,7 +639,7 @@ WRITE16_MEMBER(x68k_state::fdc_w)
}
}
-READ16_MEMBER(x68k_state::fdc_r)
+uint16_t x68k_state::fdc_r(offs_t offset)
{
unsigned int ret;
int x;
@@ -719,7 +719,7 @@ void x68k_state::ct_w(uint8_t data)
- bits 7-2 = vector
- bits 1,0 = device (00 = FDC, 01 = FDD, 10 = HDD, 11 = Printer)
*/
-WRITE16_MEMBER(x68k_state::ioc_w)
+void x68k_state::ioc_w(offs_t offset, uint16_t data)
{
switch(offset)
{
@@ -751,7 +751,7 @@ WRITE16_MEMBER(x68k_state::ioc_w)
}
}
-READ16_MEMBER(x68k_state::ioc_r)
+uint16_t x68k_state::ioc_r(offs_t offset)
{
switch(offset)
{
@@ -783,7 +783,7 @@ READ16_MEMBER(x68k_state::ioc_r)
Any other value, then SRAM is read only.
Port 8 (0xe8e00f) - Power off control - write 0x00, 0x0f, 0x0f sequentially to switch power off.
*/
-WRITE16_MEMBER(x68k_state::sysport_w)
+void x68k_state::sysport_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset)
{
@@ -806,7 +806,7 @@ WRITE16_MEMBER(x68k_state::sysport_w)
}
}
-READ16_MEMBER(x68k_state::sysport_r)
+uint16_t x68k_state::sysport_r(offs_t offset)
{
int ret = 0;
switch(offset)
@@ -826,18 +826,18 @@ READ16_MEMBER(x68k_state::sysport_r)
}
}
-WRITE16_MEMBER(x68k_state::ppi_w)
+void x68k_state::ppi_w(offs_t offset, uint16_t data)
{
m_ppi->write(offset & 0x03,data);
}
-READ16_MEMBER(x68k_state::ppi_r)
+uint16_t x68k_state::ppi_r(offs_t offset)
{
return m_ppi->read(offset & 0x03);
}
-WRITE16_MEMBER(x68k_state::sram_w)
+void x68k_state::sram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if(m_sysport.sram_writeprotect == 0x31)
{
@@ -845,7 +845,7 @@ WRITE16_MEMBER(x68k_state::sram_w)
}
}
-READ16_MEMBER(x68k_state::sram_r)
+uint16_t x68k_state::sram_r(offs_t offset)
{
// HACKS!
// if(offset == 0x5a/2) // 0x5a should be 0 if no SASI HDs are present.
@@ -855,7 +855,7 @@ READ16_MEMBER(x68k_state::sram_r)
return m_nvram[offset];
}
-WRITE16_MEMBER(x68k_state::vid_w)
+void x68k_state::vid_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset)
{
@@ -892,7 +892,7 @@ WRITE16_MEMBER(x68k_state::vid_w)
}
}
-READ16_MEMBER(x68k_state::vid_r)
+uint16_t x68k_state::vid_r(offs_t offset)
{
switch(offset)
{
@@ -909,19 +909,19 @@ READ16_MEMBER(x68k_state::vid_r)
return 0xff;
}
-READ16_MEMBER(x68k_state::areaset_r)
+uint16_t x68k_state::areaset_r()
{
// register is write-only
return 0xffff;
}
-WRITE16_MEMBER(x68k_state::areaset_w)
+void x68k_state::areaset_w(uint16_t data)
{
// TODO
LOGMASKED(LOG_SYS, "SYS: Supervisor area set: 0x%02x\n",data & 0xff);
}
-WRITE16_MEMBER(x68k_state::enh_areaset_w )
+void x68k_state::enh_areaset_w(offs_t offset, uint16_t data)
{
// TODO
LOGMASKED(LOG_SYS, "SYS: Enhanced Supervisor area set (from %iMB): 0x%02x\n",(offset + 1) * 2,data & 0xff);
@@ -946,7 +946,7 @@ void x68k_state::set_bus_error(uint32_t address, bool rw, uint16_t mem_mask)
LOGMASKED(LOG_SYS, "%s: Bus error: Unused RAM access [%08x]\n", machine().describe_context(), address);
}
-READ16_MEMBER(x68k_state::rom0_r)
+uint16_t x68k_state::rom0_r(offs_t offset, uint16_t mem_mask)
{
/* this location contains the address of some expansion device ROM, if no ROM exists,
then access causes a bus error */
@@ -955,7 +955,7 @@ READ16_MEMBER(x68k_state::rom0_r)
return 0xff;
}
-WRITE16_MEMBER(x68k_state::rom0_w)
+void x68k_state::rom0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
/* this location contains the address of some expansion device ROM, if no ROM exists,
then access causes a bus error */
@@ -963,7 +963,7 @@ WRITE16_MEMBER(x68k_state::rom0_w)
set_bus_error((offset << 1) + 0xbffffc, false, mem_mask);
}
-READ16_MEMBER(x68k_state::emptyram_r)
+uint16_t x68k_state::emptyram_r(offs_t offset, uint16_t mem_mask)
{
/* this location is unused RAM, access here causes a bus error
Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
@@ -972,7 +972,7 @@ READ16_MEMBER(x68k_state::emptyram_r)
return 0xff;
}
-WRITE16_MEMBER(x68k_state::emptyram_w)
+void x68k_state::emptyram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
/* this location is unused RAM, access here causes a bus error
Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
@@ -980,7 +980,7 @@ WRITE16_MEMBER(x68k_state::emptyram_w)
set_bus_error((offset << 1), 1, mem_mask);
}
-READ16_MEMBER(x68k_state::exp_r)
+uint16_t x68k_state::exp_r(offs_t offset, uint16_t mem_mask)
{
/* These are expansion devices, if not present, they cause a bus error */
if((m_options->read() & 0x02) && !machine().side_effects_disabled())
@@ -988,7 +988,7 @@ READ16_MEMBER(x68k_state::exp_r)
return 0xff;
}
-WRITE16_MEMBER(x68k_state::exp_w)
+void x68k_state::exp_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
/* These are expansion devices, if not present, they cause a bus error */
if((m_options->read() & 0x02) && !machine().side_effects_disabled())
@@ -1021,7 +1021,7 @@ WRITE_LINE_MEMBER(x68k_state::fm_irq)
}
}
-WRITE8_MEMBER(x68k_state::adpcm_w)
+void x68k_state::adpcm_w(offs_t offset, uint8_t data)
{
switch(offset)
{