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Diffstat (limited to 'src/mame/drivers/lucky74.cpp')
-rw-r--r--src/mame/drivers/lucky74.cpp52
1 files changed, 27 insertions, 25 deletions
diff --git a/src/mame/drivers/lucky74.cpp b/src/mame/drivers/lucky74.cpp
index 020aace5b80..c48e7062f4c 100644
--- a/src/mame/drivers/lucky74.cpp
+++ b/src/mame/drivers/lucky74.cpp
@@ -926,31 +926,33 @@ INTERRUPT_GEN_MEMBER(lucky74_state::nmi_interrupt)
* Memory Map Information *
*************************/
-ADDRESS_MAP_START(lucky74_state::lucky74_map)
- AM_RANGE(0x0000, 0xbfff) AM_ROM
- AM_RANGE(0xc000, 0xcfff) AM_RAM AM_SHARE("nvram") /* NVRAM */
- AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE(lucky74_fg_videoram_w) AM_SHARE("fg_videoram") /* VRAM1-1 */
- AM_RANGE(0xd800, 0xdfff) AM_RAM_WRITE(lucky74_fg_colorram_w) AM_SHARE("fg_colorram") /* VRAM1-2 */
- AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE(lucky74_bg_videoram_w) AM_SHARE("bg_videoram") /* VRAM2-1 */
- AM_RANGE(0xe800, 0xefff) AM_RAM_WRITE(lucky74_bg_colorram_w) AM_SHARE("bg_colorram") /* VRAM2-2 */
- AM_RANGE(0xf000, 0xf003) AM_DEVREADWRITE("ppi8255_0", i8255_device, read, write) /* Input Ports 0 & 1 */
- AM_RANGE(0xf080, 0xf083) AM_DEVREADWRITE("ppi8255_2", i8255_device, read, write) /* DSW 1, 2 & 3 */
- AM_RANGE(0xf0c0, 0xf0c3) AM_DEVREADWRITE("ppi8255_3", i8255_device, read, write) /* DSW 4 */
- AM_RANGE(0xf100, 0xf100) AM_DEVWRITE("sn1", sn76489_device, write) /* SN76489 #1 */
- AM_RANGE(0xf200, 0xf203) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write) /* Input Ports 2 & 4 */
- AM_RANGE(0xf300, 0xf300) AM_DEVWRITE("sn2", sn76489_device, write) /* SN76489 #2 */
- AM_RANGE(0xf400, 0xf400) AM_DEVWRITE("aysnd", ay8910_device, address_w) /* YM2149 control */
- AM_RANGE(0xf500, 0xf500) AM_DEVWRITE("sn3", sn76489_device, write) /* SN76489 #3 */
- AM_RANGE(0xf600, 0xf600) AM_DEVREADWRITE("aysnd", ay8910_device, data_r, data_w) /* YM2149 (Input Port 1) */
- AM_RANGE(0xf700, 0xf701) AM_READWRITE(usart_8251_r, usart_8251_w) /* USART 8251 port */
- AM_RANGE(0xf800, 0xf803) AM_READWRITE(copro_sm7831_r, copro_sm7831_w) /* SM7831 Co-Processor */
-ADDRESS_MAP_END
-
-ADDRESS_MAP_START(lucky74_state::lucky74_portmap)
- ADDRESS_MAP_GLOBAL_MASK(0xff)
- AM_RANGE(0x00, 0x05) AM_READWRITE(custom_09R81P_port_r, custom_09R81P_port_w) /* custom 09R81P (samples system) */
- AM_RANGE(0xff, 0xff) AM_RAM // presumably HS satellite control port (check patched in Lucky 74)
-ADDRESS_MAP_END
+void lucky74_state::lucky74_map(address_map &map)
+{
+ map(0x0000, 0xbfff).rom();
+ map(0xc000, 0xcfff).ram().share("nvram"); /* NVRAM */
+ map(0xd000, 0xd7ff).ram().w(this, FUNC(lucky74_state::lucky74_fg_videoram_w)).share("fg_videoram"); /* VRAM1-1 */
+ map(0xd800, 0xdfff).ram().w(this, FUNC(lucky74_state::lucky74_fg_colorram_w)).share("fg_colorram"); /* VRAM1-2 */
+ map(0xe000, 0xe7ff).ram().w(this, FUNC(lucky74_state::lucky74_bg_videoram_w)).share("bg_videoram"); /* VRAM2-1 */
+ map(0xe800, 0xefff).ram().w(this, FUNC(lucky74_state::lucky74_bg_colorram_w)).share("bg_colorram"); /* VRAM2-2 */
+ map(0xf000, 0xf003).rw("ppi8255_0", FUNC(i8255_device::read), FUNC(i8255_device::write)); /* Input Ports 0 & 1 */
+ map(0xf080, 0xf083).rw("ppi8255_2", FUNC(i8255_device::read), FUNC(i8255_device::write)); /* DSW 1, 2 & 3 */
+ map(0xf0c0, 0xf0c3).rw("ppi8255_3", FUNC(i8255_device::read), FUNC(i8255_device::write)); /* DSW 4 */
+ map(0xf100, 0xf100).w("sn1", FUNC(sn76489_device::write)); /* SN76489 #1 */
+ map(0xf200, 0xf203).rw("ppi8255_1", FUNC(i8255_device::read), FUNC(i8255_device::write)); /* Input Ports 2 & 4 */
+ map(0xf300, 0xf300).w("sn2", FUNC(sn76489_device::write)); /* SN76489 #2 */
+ map(0xf400, 0xf400).w("aysnd", FUNC(ay8910_device::address_w)); /* YM2149 control */
+ map(0xf500, 0xf500).w("sn3", FUNC(sn76489_device::write)); /* SN76489 #3 */
+ map(0xf600, 0xf600).rw("aysnd", FUNC(ay8910_device::data_r), FUNC(ay8910_device::data_w)); /* YM2149 (Input Port 1) */
+ map(0xf700, 0xf701).rw(this, FUNC(lucky74_state::usart_8251_r), FUNC(lucky74_state::usart_8251_w)); /* USART 8251 port */
+ map(0xf800, 0xf803).rw(this, FUNC(lucky74_state::copro_sm7831_r), FUNC(lucky74_state::copro_sm7831_w)); /* SM7831 Co-Processor */
+}
+
+void lucky74_state::lucky74_portmap(address_map &map)
+{
+ map.global_mask(0xff);
+ map(0x00, 0x05).rw(this, FUNC(lucky74_state::custom_09R81P_port_r), FUNC(lucky74_state::custom_09R81P_port_w)); /* custom 09R81P (samples system) */
+ map(0xff, 0xff).ram(); // presumably HS satellite control port (check patched in Lucky 74)
+}
/* unknown I/O byte R/W