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Diffstat (limited to 'src/mame/drivers/hng64.cpp')
-rw-r--r--src/mame/drivers/hng64.cpp44
1 files changed, 22 insertions, 22 deletions
diff --git a/src/mame/drivers/hng64.cpp b/src/mame/drivers/hng64.cpp
index c42ae48fa77..9ba52e3bc4b 100644
--- a/src/mame/drivers/hng64.cpp
+++ b/src/mame/drivers/hng64.cpp
@@ -450,35 +450,35 @@ or Fatal Fury for example).
#define VERBOSE 1
#include "logmacro.h"
-READ32_MEMBER(hng64_state::hng64_com_r)
+uint32_t hng64_state::hng64_com_r(offs_t offset)
{
//LOG("com read (PC=%08x): %08x %08x = %08x\n", m_maincpu->pc(), (offset*4)+0xc0000000, mem_mask, m_idt7133_dpram[offset]);
return m_idt7133_dpram[offset];
}
-WRITE32_MEMBER(hng64_state::hng64_com_w)
+void hng64_state::hng64_com_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
//LOG("com write (PC=%08x): %08x %08x = %08x\n", m_maincpu->pc(), (offset*4)+0xc0000000, mem_mask, data);
COMBINE_DATA(&m_idt7133_dpram[offset]);
}
/* TODO: fully understand this */
-WRITE8_MEMBER(hng64_state::hng64_com_share_mips_w)
+void hng64_state::hng64_com_share_mips_w(offs_t offset, uint8_t data)
{
m_com_shared[offset ^ 3] = data;
}
-READ8_MEMBER(hng64_state::hng64_com_share_mips_r)
+uint8_t hng64_state::hng64_com_share_mips_r(offs_t offset)
{
return m_com_shared[offset];
}
-WRITE8_MEMBER(hng64_state::hng64_com_share_w)
+void hng64_state::hng64_com_share_w(offs_t offset, uint8_t data)
{
m_com_shared[offset] = data;
}
-READ8_MEMBER(hng64_state::hng64_com_share_r)
+uint8_t hng64_state::hng64_com_share_r(offs_t offset)
{
if(offset == 4)
return m_com_shared[offset] | 1; // some busy flag?
@@ -487,7 +487,7 @@ READ8_MEMBER(hng64_state::hng64_com_share_r)
}
-READ32_MEMBER(hng64_state::hng64_rtc_r)
+uint32_t hng64_state::hng64_rtc_r(offs_t offset, uint32_t mem_mask)
{
if (offset & 1)
{
@@ -526,7 +526,7 @@ void hng64_state::do_dma(address_space &space)
}
}
-READ32_MEMBER(hng64_state::hng64_dmac_r)
+uint32_t hng64_state::hng64_dmac_r(offs_t offset, uint32_t mem_mask)
{
// DMAC seems to be mapped as 4 bytes in every 8
if ((offset * 4) == 0x54)
@@ -537,7 +537,7 @@ READ32_MEMBER(hng64_state::hng64_dmac_r)
return 0xffffffff;
}
-WRITE32_MEMBER(hng64_state::hng64_dmac_w)
+void hng64_state::hng64_dmac_w(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask)
{
// DMAC seems to be mapped as 4 bytes in every 8
switch (offset * 4)
@@ -561,7 +561,7 @@ WRITE32_MEMBER(hng64_state::hng64_dmac_w)
}
}
-WRITE32_MEMBER(hng64_state::hng64_rtc_w)
+void hng64_state::hng64_rtc_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (offset & 1)
{
@@ -575,14 +575,14 @@ WRITE32_MEMBER(hng64_state::hng64_rtc_w)
}
}
-WRITE32_MEMBER(hng64_state::hng64_mips_to_iomcu_irq_w)
+void hng64_state::hng64_mips_to_iomcu_irq_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// guess, written after a write to 0x00 in dpram, which is where the command goes, and the IRQ onthe MCU reads the command
LOG("%s: HNG64 writing to SYSTEM Registers %08x (%08x) (IO MCU IRQ TRIGGER?)\n", machine().describe_context(), data, mem_mask);
if (mem_mask & 0xffff0000) m_tempio_irqon_timer->adjust(attotime::zero);
}
-READ32_MEMBER(hng64_state::hng64_irqc_r)
+uint32_t hng64_state::hng64_irqc_r(offs_t offset, uint32_t mem_mask)
{
if ((offset * 4) == 0x04)
{
@@ -597,7 +597,7 @@ READ32_MEMBER(hng64_state::hng64_irqc_r)
return 0xffffffff;
}
-WRITE32_MEMBER(hng64_state::hng64_irqc_w)
+void hng64_state::hng64_irqc_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
switch (offset * 4)
{
@@ -644,7 +644,7 @@ WRITE32_MEMBER(hng64_state::hng64_irqc_w)
----
*/
-READ32_MEMBER(hng64_state::hng64_sysregs_r)
+uint32_t hng64_state::hng64_sysregs_r(offs_t offset, uint32_t mem_mask)
{
//LOG("%s: hng64_sysregs_r (%04x) (%08x)\n", machine().describe_context(), offset * 4, mem_mask);
@@ -661,7 +661,7 @@ READ32_MEMBER(hng64_state::hng64_sysregs_r)
return m_sysregs[offset];
}
-WRITE32_MEMBER(hng64_state::hng64_sysregs_w)
+void hng64_state::hng64_sysregs_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA (&m_sysregs[offset]);
@@ -686,7 +686,7 @@ WRITE32_MEMBER(hng64_state::hng64_sysregs_w)
* MIPS side Dual Port RAM hookup for MCU
**************************************/
-READ8_MEMBER(hng64_state::hng64_dualport_r)
+uint8_t hng64_state::hng64_dualport_r(offs_t offset)
{
LOG("%s: dualport R %04x\n", machine().describe_context(), offset);
@@ -729,7 +729,7 @@ Beast Busters 2 outputs (all at offset == 0x1c):
it seems correct, see hng64_mips_to_iomcu_irq_w )
*/
-WRITE8_MEMBER(hng64_state::hng64_dualport_w)
+void hng64_state::hng64_dualport_w(offs_t offset, uint8_t data)
{
m_dt71321_dpram->right_w(offset, data);
LOG("%s: dualport WRITE %04x %02x\n", machine().describe_context(), offset, data);
@@ -738,7 +738,7 @@ WRITE8_MEMBER(hng64_state::hng64_dualport_w)
/************************************************************************************************************/
/* The following is guesswork, needs confirmation with a test on the real board. */
-WRITE32_MEMBER(hng64_state::hng64_sprite_clear_even_w)
+void hng64_state::hng64_sprite_clear_even_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
auto &mspace = m_maincpu->space(AS_PROGRAM);
uint32_t spr_offs;
@@ -761,7 +761,7 @@ WRITE32_MEMBER(hng64_state::hng64_sprite_clear_even_w)
}
}
-WRITE32_MEMBER(hng64_state::hng64_sprite_clear_odd_w)
+void hng64_state::hng64_sprite_clear_odd_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
auto &mspace = m_maincpu->space(AS_PROGRAM);
uint32_t spr_offs;
@@ -784,13 +784,13 @@ WRITE32_MEMBER(hng64_state::hng64_sprite_clear_odd_w)
}
}
-WRITE32_MEMBER(hng64_state::hng64_vregs_w)
+void hng64_state::hng64_vregs_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// printf("hng64_vregs_w %02x, %08x %08x\n", offset * 4, data, mem_mask);
COMBINE_DATA(&m_videoregs[offset]);
}
-READ16_MEMBER(hng64_state::main_sound_comms_r)
+uint16_t hng64_state::main_sound_comms_r(offs_t offset)
{
switch(offset *2)
{
@@ -805,7 +805,7 @@ READ16_MEMBER(hng64_state::main_sound_comms_r)
return 0;
}
-WRITE16_MEMBER(hng64_state::main_sound_comms_w)
+void hng64_state::main_sound_comms_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch(offset * 2)
{