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Diffstat (limited to 'src/mame/drivers/f1gp.cpp')
-rw-r--r--src/mame/drivers/f1gp.cpp60
1 files changed, 32 insertions, 28 deletions
diff --git a/src/mame/drivers/f1gp.cpp b/src/mame/drivers/f1gp.cpp
index cfc71d8f96e..7e3cd72442b 100644
--- a/src/mame/drivers/f1gp.cpp
+++ b/src/mame/drivers/f1gp.cpp
@@ -58,16 +58,16 @@ void f1gp_state::f1gp_cpu1_map(address_map &map)
map(0x000000, 0x03ffff).rom();
map(0x100000, 0x2fffff).rom().region("user1", 0);
map(0xa00000, 0xbfffff).rom().region("user2", 0);
- map(0xc00000, 0xc3ffff).ram().w(FUNC(f1gp_state::rozgfxram_w)).share("rozgfxram");
- map(0xd00000, 0xd01fff).mirror(0x006000).ram().w(FUNC(f1gp_state::rozvideoram_w)).share("rozvideoram");
- map(0xe00000, 0xe03fff).ram().share("spr1cgram"); // SPR-1 CG RAM
- map(0xe04000, 0xe07fff).ram().share("spr2cgram"); // SPR-2 CG RAM
- map(0xf00000, 0xf003ff).ram().share("spr1vram"); // SPR-1 VRAM
- map(0xf10000, 0xf103ff).ram().share("spr2vram"); // SPR-2 VRAM
- map(0xff8000, 0xffbfff).ram(); // WORK RAM-1
- map(0xffc000, 0xffcfff).ram().share("sharedram"); // DUAL RAM
- map(0xffd000, 0xffdfff).ram().w(FUNC(f1gp_state::fgvideoram_w)).share("fgvideoram"); // CHARACTER
- map(0xffe000, 0xffefff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette"); // PALETTE
+ map(0xc00000, 0xc3ffff).ram().w(FUNC(f1gp_state::rozgfxram_w)).share(m_rozgfxram);
+ map(0xd00000, 0xd01fff).mirror(0x006000).ram().w(FUNC(f1gp_state::rozvideoram_w)).share(m_rozvideoram);
+ map(0xe00000, 0xe03fff).ram().share(m_sprcgram[0]); // SPR-1 CG RAM
+ map(0xe04000, 0xe07fff).ram().share(m_sprcgram[1]); // SPR-2 CG RAM
+ map(0xf00000, 0xf003ff).ram().share(m_sprvram[0]); // SPR-1 VRAM
+ map(0xf10000, 0xf103ff).ram().share(m_sprvram[1]); // SPR-2 VRAM
+ map(0xff8000, 0xffbfff).ram(); // WORK RAM-1
+ map(0xffc000, 0xffcfff).ram().share(m_sharedram); // DUAL RAM
+ map(0xffd000, 0xffdfff).ram().w(FUNC(f1gp_state::fgvideoram_w)).share(m_fgvideoram); // CHARACTER
+ map(0xffe000, 0xffefff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette"); // PALETTE
map(0xfff000, 0xfff001).portr("INPUTS");
map(0xfff001, 0xfff001).w(FUNC(f1gp_state::gfxctrl_w));
map(0xfff002, 0xfff003).portr("WHEEL");
@@ -84,13 +84,13 @@ void f1gp2_state::f1gp2_cpu1_map(address_map &map)
{
map(0x000000, 0x03ffff).rom();
map(0x100000, 0x2fffff).rom().region("user1", 0);
- map(0xa00000, 0xa07fff).ram().share("spr1cgram"); // SPR-1 CG RAM + SPR-2 CG RAM
- map(0xd00000, 0xd01fff).ram().w(FUNC(f1gp2_state::rozvideoram_w)).share("rozvideoram"); // BACK VRAM
- map(0xe00000, 0xe00fff).ram().share("spr1vram"); // not checked + SPR-1 VRAM + SPR-2 VRAM
- map(0xff8000, 0xffbfff).ram(); // WORK RAM-1
- map(0xffc000, 0xffcfff).ram().share("sharedram"); // DUAL RAM
- map(0xffd000, 0xffdfff).ram().w(FUNC(f1gp2_state::fgvideoram_w)).share("fgvideoram"); // CHARACTER
- map(0xffe000, 0xffefff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette"); // PALETTE
+ map(0xa00000, 0xa07fff).ram().share(m_sprcgram[0]); // SPR-1 CG RAM + SPR-2 CG RAM
+ map(0xd00000, 0xd01fff).ram().w(FUNC(f1gp2_state::rozvideoram_w)).share(m_rozvideoram); // BACK VRAM
+ map(0xe00000, 0xe00fff).ram().share(m_sprvram[0]); // not checked + SPR-1 VRAM + SPR-2 VRAM
+ map(0xff8000, 0xffbfff).ram(); // WORK RAM-1
+ map(0xffc000, 0xffcfff).ram().share(m_sharedram); // DUAL RAM
+ map(0xffd000, 0xffdfff).ram().w(FUNC(f1gp2_state::fgvideoram_w)).share(m_fgvideoram); // CHARACTER
+ map(0xffe000, 0xffefff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette"); // PALETTE
map(0xfff000, 0xfff001).portr("INPUTS");
map(0xfff000, 0xfff000).w(FUNC(f1gp2_state::rozbank_w));
map(0xfff001, 0xfff001).w(FUNC(f1gp2_state::gfxctrl_w));
@@ -107,7 +107,7 @@ void f1gp_state::f1gp_cpu2_map(address_map &map)
{
map(0x000000, 0x01ffff).rom();
map(0xff8000, 0xffbfff).ram();
- map(0xffc000, 0xffcfff).ram().share("sharedram");
+ map(0xffc000, 0xffcfff).ram().share(m_sharedram);
map(0xfff030, 0xfff033).rw(m_acia, FUNC(acia6850_device::read), FUNC(acia6850_device::write)).umask16(0x00ff);
}
@@ -115,7 +115,7 @@ void f1gp_state::sound_map(address_map &map)
{
map(0x0000, 0x77ff).rom();
map(0x7800, 0x7fff).ram();
- map(0x8000, 0xffff).bankr("z80bank");
+ map(0x8000, 0xffff).bankr(m_z80bank);
}
void f1gp_state::sound_io_map(address_map &map)
@@ -157,16 +157,16 @@ void f1gp_state::f1gpb_cpu1_map(address_map &map)
map(0x000000, 0x03ffff).rom();
map(0x100000, 0x2fffff).rom().region("user1", 0);
map(0xa00000, 0xbfffff).rom().region("user2", 0);
- map(0x800000, 0x801fff).ram().share("spriteram");
- map(0xc00000, 0xc3ffff).ram().w(FUNC(f1gp_state::rozgfxram_w)).share("rozgfxram");
- map(0xd00000, 0xd01fff).mirror(0x006000).ram().w(FUNC(f1gp_state::rozvideoram_w)).share("rozvideoram");
+ map(0x800000, 0x801fff).ram().share(m_spriteram);
+ map(0xc00000, 0xc3ffff).ram().w(FUNC(f1gp_state::rozgfxram_w)).share(m_rozgfxram);
+ map(0xd00000, 0xd01fff).mirror(0x006000).ram().w(FUNC(f1gp_state::rozvideoram_w)).share(m_rozvideoram);
map(0xe00000, 0xe03fff).ram(); //unused
map(0xe04000, 0xe07fff).ram(); //unused
map(0xf00000, 0xf003ff).ram(); //unused
map(0xf10000, 0xf103ff).ram(); //unused
map(0xff8000, 0xffbfff).ram();
- map(0xffc000, 0xffcfff).ram().share("sharedram");
- map(0xffd000, 0xffdfff).ram().w(FUNC(f1gp_state::fgvideoram_w)).share("fgvideoram");
+ map(0xffc000, 0xffcfff).ram().share(m_sharedram);
+ map(0xffd000, 0xffdfff).ram().w(FUNC(f1gp_state::fgvideoram_w)).share(m_fgvideoram);
map(0xffe000, 0xffefff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
map(0xfff000, 0xfff001).portr("INPUTS");
map(0xfff002, 0xfff003).portr("WHEEL");
@@ -174,20 +174,20 @@ void f1gp_state::f1gpb_cpu1_map(address_map &map)
map(0xfff006, 0xfff007).portr("DSW2");
map(0xfff008, 0xfff009).nopr(); //?
map(0xfff006, 0xfff007).nopw();
- map(0xfff00a, 0xfff00b).ram().share("fgregs");
+ map(0xfff00a, 0xfff00b).ram().share(m_fgregs);
map(0xfff00f, 0xfff00f).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write));
map(0xfff00c, 0xfff00d).w(FUNC(f1gp_state::f1gpb_misc_w));
map(0xfff010, 0xfff011).nopw();
map(0xfff020, 0xfff023).nopw(); // GGA access
map(0xfff050, 0xfff051).portr("DSW3");
- map(0xfff800, 0xfff809).ram().share("rozregs");
+ map(0xfff800, 0xfff809).ram().share(m_rozregs);
}
void f1gp_state::f1gpb_cpu2_map(address_map &map)
{
map(0x000000, 0x01ffff).rom();
map(0xff8000, 0xffbfff).ram();
- map(0xffc000, 0xffcfff).ram().share("sharedram");
+ map(0xffc000, 0xffcfff).ram().share(m_sharedram);
map(0xfff030, 0xfff033).rw(m_acia, FUNC(acia6850_device::read), FUNC(acia6850_device::write)).umask16(0x00ff);
}
@@ -333,6 +333,10 @@ GFXDECODE_END
void f1gp_state::machine_start()
{
+ // assumes it can make an address mask with .length() - 1
+ assert(!m_sprcgram[0].found() || !(m_sprcgram[0].length() & (m_sprcgram[0].length() - 1)));
+ assert(!m_sprcgram[1].found() || !(m_sprcgram[1].length() & (m_sprcgram[1].length() - 1)));
+
if (m_z80bank)
m_z80bank->configure_entries(0, 2, memregion("audiocpu")->base() + 0x8000, 0x8000);
@@ -357,7 +361,7 @@ void f1gp2_state::machine_reset()
template<int Chip>
uint32_t f1gp_state::tile_callback( uint32_t code )
{
- return m_sprcgram[Chip][code & (m_sprcgram[Chip].mask()>>1)];
+ return m_sprcgram[Chip][code & (m_sprcgram[Chip].length() - 1)];
}
void f1gp_state::f1gp(machine_config &config)