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Diffstat (limited to 'src/mame/drivers/dfs500.cpp')
-rw-r--r--src/mame/drivers/dfs500.cpp34
1 files changed, 17 insertions, 17 deletions
diff --git a/src/mame/drivers/dfs500.cpp b/src/mame/drivers/dfs500.cpp
index 0a5c76194cf..661bcda7d6a 100644
--- a/src/mame/drivers/dfs500.cpp
+++ b/src/mame/drivers/dfs500.cpp
@@ -234,7 +234,7 @@ uint32_t dfs500_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap
const bitmap_argb32 *input_bitmap = &m_input[m_input_sel_A & 3]->get_bitmap();
// FIXME: This is simply bypassing the inputs directly into the output.
// Emulation of the video hardware (DSP signal path) for GFX processing is still needed here.
- if (input_bitmap)
+ if (input_bitmap->valid())
{
// convert arbitrary sized ARGB32 image to a full-screen image
double stepx = double (input_bitmap->width()) / VIDEO_WIDTH;
@@ -577,7 +577,7 @@ void dfs500_state::cpanel_reg1_w(offs_t offset, uint8_t data)
break;
case 7: // WR20 on IC47 KY-223
// Here "data" holds the 8-bit value of the "interrupt vector number"
- // to be put on the data bus when the CPU asserts /INTAK (Interrupt Acknowledge)
+ // to be put on the data bus when the CPU asserts /INTAK (Interrupt Acknowledge)
m_int_vector = data;
// FIXME: Is this an alternative way of doing it?
// m_cpanelcpu->set_input_line_and_vector(0, HOLD_LINE, data);
@@ -645,9 +645,9 @@ void dfs500_state::cpanel_reg2_w(offs_t offset, uint8_t data)
m_LD[32] = BIT(data, 0); // location
break;
case 6: // WR27 on IC21 KY-225
- m_sel54 = (data >> 6) & 3; // D7/D6 = SEL5/SEL4 signals to IC26
+ m_sel54 = (data >> 6) & 3; // D7/D6 = SEL5/SEL4 signals to IC26
// Dot-points on 7seg digits:
- // D5 = LD150 = DP on user program status
+ // D5 = LD150 = DP on user program status
// D4 = LD142 = DP on user program edit
// D3 = LD134 = DP on trail_duration_1
// D2 = LD126 = DP on trail_duration_0
@@ -673,8 +673,8 @@ void dfs500_state::cpanel_reg2_w(offs_t offset, uint8_t data)
uint8_t dfs500_state::cpanel_buzzer_r(offs_t offset)
{
// FIXME: Not sure yet what to do here...
-// TODO: m_buzzer_state = !m_buzzer_state;
-// TODO: m_buzzer->set_state(m_buzzer_state);
+// TODO: m_buzzer_state = !m_buzzer_state;
+// TODO: m_buzzer->set_state(m_buzzer_state);
return 0;
}
@@ -701,7 +701,7 @@ void dfs500_state::maincpu_mem_map(address_map &map)
{
//FIXME: The RAM mirror should be 0xe0000 according to IC49 on board SY-172 (as it is wired on the service manual schematics)
// but I saw unmapped accesses to the A15 mirror of this range on the MAME debugger, which suggests the 0xe8000 value used below:
- map(0x00000, 0x07fff).mirror(0xe8000).ram(); // 4x 8kb SRAM chips at IC59/IC60/IC61/IC62
+ map(0x00000, 0x07fff).mirror(0xe8000).ram(); // 4x 8kb SRAM chips at IC59/IC60/IC61/IC62
map(0x10000, 0x1ffff).mirror(0xe0000).rom().region("maincpu", 0); // 2x 32kb EPROMs at IC1/IC2
}
@@ -723,22 +723,22 @@ void dfs500_state::effectcpu_mem_map(address_map &map)
{
// Note: As far as I can tell by the schematics in the service manual, the ram mirror should be 0x90000.
// But I see unmapped read acesses to 0x4800, which induces me to make the mirror 0x94000, instead.
- // FIXME: This should be double-checked!
- map(0x00000, 0x03fff).mirror(0x94000).ram(); // 2x 8kb SRAM chips at IC23/IC24
+ // FIXME: This should be double-checked!
+ map(0x00000, 0x03fff).mirror(0x94000).ram(); // 2x 8kb SRAM chips at IC23/IC24
map(0x08000, 0x0bfff).mirror(0x90000).bankr("rombank1"); // Effect data on 4x 512kb EPROMs at IC5/IC6/IC7/IC8
map(0x0c000, 0x0ffff).mirror(0x90000).bankr("rombank2"); // Second banked view of the contents of the same effect data EPROMs
map(0x20000, 0x20001).mirror(0x9fffe).noprw(); // FIXME: Do something with the MTRX signal generated by this memory access
map(0x46000, 0x46fff).mirror(0x91000).ram().share("sgram"); // IC80/IC81 at FM-29 (4/6)
- // Selected by IC201 at FM-29 (3/6)
+ // Selected by IC201 at FM-29 (3/6)
map(0x68000, 0x68001).mirror(0x907fe).rw(FUNC(dfs500_state::RA0_r), FUNC(dfs500_state::WA0_w)); // "RA0" IC26/IC27 & "WA0" IC32/IC33
- // 16-bit data latches for communication between CPUs
+ // 16-bit data latches for communication between CPUs
map(0x68800, 0x68801).mirror(0x907fe).r(FUNC(dfs500_state::RA1_r)); // "RA1" IC25/IC64
map(0x69000, 0x69000).mirror(0x907ff).w(FUNC(dfs500_state::rombank2_entry_w)); // "WA2" IC29
map(0x69800, 0x69800).mirror(0x907ff).w(FUNC(dfs500_state::rombank1_entry_w)); // "WA3" IC30
map(0x6a000, 0x6a000).mirror(0x907ff).w(FUNC(dfs500_state::input_select_w)); // "WA4" IC31
map(0x70000, 0x7ffff).mirror(0x80000).rom().region("effectcpu", 0); // 2x 64kb EPROMs at IC3/IC4,
- // Note: the 1st half of each is entirely made of 0xFF
-
+ // Note: the 1st half of each is entirely made of 0xFF
+
// ==== "ORG1" registers ====
// "controlsignals" (Not sure yet of their actual use)
// D13: PS2
@@ -788,7 +788,7 @@ void dfs500_state::effectcpu_mem_map(address_map &map)
// WRA: /WR
// WAn: !REGA & !WRA & n=AA13/12/11
// WAn: ?11? 10nn n??? ???? ????
-
+
// ARAM = AA18/17=10
// ARAMW = ?
// MTRX = ?
@@ -895,7 +895,7 @@ static INPUT_PORTS_START(dfs500)
PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYPAD) PORT_NAME("KEYPAD 8") PORT_CODE(KEYCODE_8_PAD) // SW71
PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYPAD) PORT_NAME("KEYPAD 9") PORT_CODE(KEYCODE_9_PAD) // SW72
PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYPAD) PORT_NAME("KEYPAD INS") PORT_CODE(KEYCODE_INSERT)// SW73
-
+
PORT_START("RD10")
PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYPAD) PORT_NAME("LIGHTING INTENSITY") // SW8
PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYPAD) PORT_NAME("LIGHTING WIDTH") // SW7
@@ -960,10 +960,10 @@ void dfs500_state::dfs500(machine_config &config)
// TODO: m_adc->in_callback<1>().set_ioport("TCLIP2");
// TODO: m_adc->in_callback<0>().set_ioport("TCLIP1");
- //Buzzer
+ //Buzzer
SPEAKER(config, "mono").front_center();
BEEP(config, "buzzer", 4000).add_route(ALL_OUTPUTS, "mono", 0.05); // incorrect/arbitrary freq.
- // I did not calculate the correct one yet.
+ // I did not calculate the correct one yet.
/******************* Effects Processing Unit ********************/
// CXQ70116P-10 at IC40 (same as V20, but with a 16-bit data bus)