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Diffstat (limited to 'src/mame/drivers/dccons.cpp')
-rw-r--r--src/mame/drivers/dccons.cpp79
1 files changed, 41 insertions, 38 deletions
diff --git a/src/mame/drivers/dccons.cpp b/src/mame/drivers/dccons.cpp
index bcca1a1e08e..1ee148f590a 100644
--- a/src/mame/drivers/dccons.cpp
+++ b/src/mame/drivers/dccons.cpp
@@ -361,21 +361,22 @@ WRITE8_MEMBER(dc_cons_state::dc_flash_w)
}
#endif
-ADDRESS_MAP_START(dc_cons_state::dc_map)
- AM_RANGE(0x00000000, 0x001fffff) AM_ROM AM_WRITENOP // BIOS
- AM_RANGE(0x00200000, 0x0021ffff) AM_ROM AM_REGION("dcflash",0)//AM_READWRITE8(dc_flash_r,dc_flash_w, 0xffffffffffffffffU)
- AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE(dc_sysctrl_r, dc_sysctrl_w )
- AM_RANGE(0x005f6c00, 0x005f6cff) AM_DEVICE32( "maple_dc", maple_dc_device, amap, 0xffffffffffffffffU )
- AM_RANGE(0x005f7000, 0x005f701f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0x0000ffff0000ffffU )
- AM_RANGE(0x005f7080, 0x005f709f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0x0000ffff0000ffffU )
- AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE32(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w, 0xffffffffffffffffU )
- AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
- AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVICE32("powervr2", powervr2_device, pd_dma_map, 0xffffffffffffffffU)
- AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVICE32("powervr2", powervr2_device, ta_map, 0xffffffffffffffffU)
- AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(dc_modem_r, dc_modem_w )
- AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE32(dc_aica_reg_r, dc_aica_reg_w, 0xffffffffffffffffU)
- AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_DEVREADWRITE16("aicartc", aicartc_device, read, write, 0x0000ffff0000ffffU )
- AM_RANGE(0x00800000, 0x009fffff) AM_READWRITE(sh4_soundram_r, sh4_soundram_w )
+void dc_cons_state::dc_map(address_map &map)
+{
+ map(0x00000000, 0x001fffff).rom().nopw(); // BIOS
+ map(0x00200000, 0x0021ffff).rom().region("dcflash", 0);//AM_READWRITE8(dc_flash_r,dc_flash_w, 0xffffffffffffffffU)
+ map(0x005f6800, 0x005f69ff).rw(this, FUNC(dc_cons_state::dc_sysctrl_r), FUNC(dc_cons_state::dc_sysctrl_w));
+ map(0x005f6c00, 0x005f6cff).m(m_maple, FUNC(maple_dc_device::amap));
+ map(0x005f7000, 0x005f701f).rw(m_ata, FUNC(ata_interface_device::read_cs1), FUNC(ata_interface_device::write_cs1)).umask64(0x0000ffff0000ffff);
+ map(0x005f7080, 0x005f709f).rw(m_ata, FUNC(ata_interface_device::read_cs0), FUNC(ata_interface_device::write_cs0)).umask64(0x0000ffff0000ffff);
+ map(0x005f7400, 0x005f74ff).rw(this, FUNC(dc_cons_state::dc_mess_g1_ctrl_r), FUNC(dc_cons_state::dc_mess_g1_ctrl_w));
+ map(0x005f7800, 0x005f78ff).rw(this, FUNC(dc_cons_state::dc_g2_ctrl_r), FUNC(dc_cons_state::dc_g2_ctrl_w));
+ map(0x005f7c00, 0x005f7cff).m(m_powervr2, FUNC(powervr2_device::pd_dma_map));
+ map(0x005f8000, 0x005f9fff).m(m_powervr2, FUNC(powervr2_device::ta_map));
+ map(0x00600000, 0x006007ff).rw(this, FUNC(dc_cons_state::dc_modem_r), FUNC(dc_cons_state::dc_modem_w));
+ map(0x00700000, 0x00707fff).rw(this, FUNC(dc_cons_state::dc_aica_reg_r), FUNC(dc_cons_state::dc_aica_reg_w));
+ map(0x00710000, 0x0071000f).mirror(0x02000000).rw("aicartc", FUNC(aicartc_device::read), FUNC(aicartc_device::write)).umask64(0x0000ffff0000ffff);
+ map(0x00800000, 0x009fffff).rw(this, FUNC(dc_cons_state::sh4_soundram_r), FUNC(dc_cons_state::sh4_soundram_w));
// AM_RANGE(0x01000000, 0x01ffffff) G2 Ext Device #1
// AM_RANGE(0x02700000, 0x02707fff) AICA reg mirror
// AM_RANGE(0x02800000, 0x02ffffff) AICA wave mem mirror
@@ -383,40 +384,42 @@ ADDRESS_MAP_START(dc_cons_state::dc_map)
// AM_RANGE(0x03000000, 0x03ffffff) G2 Ext Device #2
/* Area 1 */
- AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
- AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
+ map(0x04000000, 0x04ffffff).ram().share("dc_texture_ram"); // texture memory 64 bit access
+ map(0x05000000, 0x05ffffff).ram().share("frameram"); // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
/* Area 3 */
- AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_SHARE("dc_ram")
- AM_RANGE(0x0d000000, 0x0dffffff) AM_RAM AM_SHARE("dc_ram")// extra ram on Naomi (mirror on DC)
- AM_RANGE(0x0e000000, 0x0effffff) AM_RAM AM_SHARE("dc_ram")// mirror
- AM_RANGE(0x0f000000, 0x0fffffff) AM_RAM AM_SHARE("dc_ram")// mirror
+ map(0x0c000000, 0x0cffffff).ram().share("dc_ram");
+ map(0x0d000000, 0x0dffffff).ram().share("dc_ram");// extra ram on Naomi (mirror on DC)
+ map(0x0e000000, 0x0effffff).ram().share("dc_ram");// mirror
+ map(0x0f000000, 0x0fffffff).ram().share("dc_ram");// mirror
/* Area 4 */
- AM_RANGE(0x10000000, 0x107fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_poly_w)
- AM_RANGE(0x10800000, 0x10ffffff) AM_DEVWRITE8("powervr2", powervr2_device, ta_fifo_yuv_w, 0xffffffffffffffffU)
- AM_RANGE(0x11000000, 0x117fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath0_w) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
+ map(0x10000000, 0x107fffff).w(m_powervr2, FUNC(powervr2_device::ta_fifo_poly_w));
+ map(0x10800000, 0x10ffffff).w(m_powervr2, FUNC(powervr2_device::ta_fifo_yuv_w));
+ map(0x11000000, 0x117fffff).w(m_powervr2, FUNC(powervr2_device::ta_texture_directpath0_w)).mirror(0x00800000); // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
- AM_RANGE(0x12000000, 0x127fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_poly_w)
- AM_RANGE(0x12800000, 0x12ffffff) AM_DEVWRITE8("powervr2", powervr2_device, ta_fifo_yuv_w, 0xffffffffffffffffU)
- AM_RANGE(0x13000000, 0x137fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath1_w) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
+ map(0x12000000, 0x127fffff).w(m_powervr2, FUNC(powervr2_device::ta_fifo_poly_w));
+ map(0x12800000, 0x12ffffff).w(m_powervr2, FUNC(powervr2_device::ta_fifo_yuv_w));
+ map(0x13000000, 0x137fffff).w(m_powervr2, FUNC(powervr2_device::ta_texture_directpath1_w)).mirror(0x00800000); // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
// AM_RANGE(0x14000000, 0x17ffffff) G2 Ext Device #3
- AM_RANGE(0x8c000000, 0x8cffffff) AM_RAM AM_SHARE("dc_ram") // another RAM mirror
+ map(0x8c000000, 0x8cffffff).ram().share("dc_ram"); // another RAM mirror
- AM_RANGE(0xa0000000, 0xa01fffff) AM_ROM AM_REGION("maincpu", 0)
-ADDRESS_MAP_END
+ map(0xa0000000, 0xa01fffff).rom().region("maincpu", 0);
+}
-ADDRESS_MAP_START(dc_cons_state::dc_port)
- AM_RANGE(0x00000000, 0x00000007) AM_READWRITE(dc_pdtra_r, dc_pdtra_w )
-ADDRESS_MAP_END
+void dc_cons_state::dc_port(address_map &map)
+{
+ map(0x00000000, 0x00000007).rw(this, FUNC(dc_cons_state::dc_pdtra_r), FUNC(dc_cons_state::dc_pdtra_w));
+}
-ADDRESS_MAP_START(dc_cons_state::dc_audio_map)
- ADDRESS_MAP_UNMAP_HIGH
- AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_SHARE("dc_sound_ram") /* shared with SH-4 */
- AM_RANGE(0x00800000, 0x00807fff) AM_READWRITE(dc_arm_aica_r, dc_arm_aica_w)
-ADDRESS_MAP_END
+void dc_cons_state::dc_audio_map(address_map &map)
+{
+ map.unmap_value_high();
+ map(0x00000000, 0x001fffff).ram().share("dc_sound_ram"); /* shared with SH-4 */
+ map(0x00800000, 0x00807fff).rw(this, FUNC(dc_cons_state::dc_arm_aica_r), FUNC(dc_cons_state::dc_arm_aica_w));
+}
static INPUT_PORTS_START( dc )
PORT_START("P1:0")