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-rw-r--r--src/mame/drivers/crystal.cpp789
1 files changed, 406 insertions, 383 deletions
diff --git a/src/mame/drivers/crystal.cpp b/src/mame/drivers/crystal.cpp
index beafc934ced..43349c843d4 100644
--- a/src/mame/drivers/crystal.cpp
+++ b/src/mame/drivers/crystal.cpp
@@ -237,38 +237,60 @@ GUN_xP are 6 pin gun connectors (pins 3-6 match the UNICO sytle guns):
#include "screen.h"
#include "speaker.h"
+#include <algorithm>
+
#define IDLE_LOOP_SPEEDUP
class crystal_state : public driver_device
{
public:
- crystal_state(const machine_config &mconfig, device_type type, const char *tag)
- : driver_device(mconfig, type, tag),
+ crystal_state(const machine_config &mconfig, device_type type, const char *tag) :
+ driver_device(mconfig, type, tag),
m_sysregs(*this, "sysregs"),
+ m_crtcregs(*this, "crtcregs"),
m_workram(*this, "workram"),
m_vidregs(*this, "vidregs"),
m_textureram(*this, "textureram"),
m_frameram(*this, "frameram"),
m_reset_patch(*this, "reset_patch"),
+ m_flash(*this, "flash"),
+ m_mainbank(*this, "mainbank"),
m_maincpu(*this, "maincpu"),
- m_vr0(*this, "vr0"),
- m_video(*this, "vrender"),
+ m_vr0vid(*this, "vr0vid"),
+ m_vr0snd(*this, "vr0snd"),
m_ds1302(*this, "rtc"),
m_screen(*this, "screen")
{ }
+ void init_topbladv();
+ void init_officeye();
+ void init_crysking();
+ void init_evosocc();
+ void init_donghaer();
+ void init_psattack();
+
+ void crospuzl(machine_config &config);
+ void crystal(machine_config &config);
+ void crzyddz2(machine_config &config);
+ void trivrus(machine_config &config);
+
+private:
/* memory pointers */
required_shared_ptr<uint32_t> m_sysregs;
+ required_shared_ptr<uint32_t> m_crtcregs;
required_shared_ptr<uint32_t> m_workram;
required_shared_ptr<uint32_t> m_vidregs;
required_shared_ptr<uint32_t> m_textureram;
required_shared_ptr<uint32_t> m_frameram;
optional_shared_ptr<uint32_t> m_reset_patch; // not needed for trivrus
+ optional_region_ptr<uint32_t> m_flash;
+
+ optional_memory_bank m_mainbank;
/* devices */
- required_device<cpu_device> m_maincpu;
- required_device<vr0video_device> m_vr0;
- required_device<vrender0_device> m_video;
+ required_device<se3208_device> m_maincpu;
+ required_device<vr0video_device> m_vr0vid;
+ required_device<vr0sound_device> m_vr0snd;
required_device<ds1302_device> m_ds1302;
required_device<screen_device> m_screen;
@@ -277,6 +299,7 @@ public:
#endif
uint32_t m_Bank;
+ uint32_t m_maxbank;
uint8_t m_FlipCount;
uint8_t m_IntHigh;
emu_timer *m_Timer[4];
@@ -290,34 +313,24 @@ public:
DECLARE_READ32_MEMBER(FlipCount_r);
DECLARE_WRITE32_MEMBER(FlipCount_w);
- DECLARE_READ32_MEMBER(Input_r);
DECLARE_WRITE32_MEMBER(IntAck_w);
+ template<int Which> DECLARE_WRITE32_MEMBER(Timer_w);
+ template<int Which> DECLARE_READ32_MEMBER(Timer_r);
+ template<int Which> DECLARE_READ32_MEMBER(DMA_r);
+ template<int Which> DECLARE_WRITE32_MEMBER(DMA_w);
+ DECLARE_READ32_MEMBER(crtc_r);
+ DECLARE_WRITE32_MEMBER(crtc_w);
+ void crtc_update();
+
+ DECLARE_READ32_MEMBER(Input_r);
DECLARE_WRITE32_MEMBER(Banksw_w);
- DECLARE_WRITE32_MEMBER(Timer0_w);
- DECLARE_READ32_MEMBER(Timer0_r);
- DECLARE_WRITE32_MEMBER(Timer1_w);
- DECLARE_READ32_MEMBER(Timer1_r);
- DECLARE_WRITE32_MEMBER(Timer2_w);
- DECLARE_READ32_MEMBER(Timer2_r);
- DECLARE_WRITE32_MEMBER(Timer3_w);
- DECLARE_READ32_MEMBER(Timer3_r);
- DECLARE_READ32_MEMBER(FlashCmd_r);
- DECLARE_WRITE32_MEMBER(FlashCmd_w);
DECLARE_READ32_MEMBER(PIO_r);
DECLARE_WRITE32_MEMBER(PIO_w);
- DECLARE_READ32_MEMBER(DMA0_r);
- DECLARE_WRITE32_MEMBER(DMA0_w);
- DECLARE_READ32_MEMBER(DMA1_r);
- DECLARE_WRITE32_MEMBER(DMA1_w);
- void init_topbladv();
- void init_officeye();
- void init_crysking();
- void init_evosocc();
- void init_donghaer();
- void init_psattack();
+ DECLARE_READ32_MEMBER(FlashCmd_r);
+ DECLARE_WRITE32_MEMBER(FlashCmd_w);
- DECLARE_READ32_MEMBER(trivrus_input_r);
- DECLARE_WRITE32_MEMBER(trivrus_input_w);
+ DECLARE_READ8_MEMBER(trivrus_input_r);
+ DECLARE_WRITE8_MEMBER(trivrus_input_w);
uint8_t m_trivrus_input;
DECLARE_READ32_MEMBER(crzyddz2_key_r);
@@ -326,25 +339,19 @@ public:
virtual void machine_start() override;
virtual void machine_reset() override;
- uint32_t screen_update_crystal(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
- DECLARE_WRITE_LINE_MEMBER(screen_vblank_crystal);
- INTERRUPT_GEN_MEMBER(crystal_interrupt);
+ uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+ DECLARE_WRITE_LINE_MEMBER(screen_vblank);
TIMER_CALLBACK_MEMBER(Timercb);
IRQ_CALLBACK_MEMBER(icallback);
- void crystal_banksw_postload();
void IntReq( int num );
- inline void Timer_w( address_space &space, int which, uint32_t data, uint32_t mem_mask );
inline void DMA_w( address_space &space, int which, uint32_t data, uint32_t mem_mask );
void PatchReset( );
uint16_t GetVidReg( address_space &space, uint16_t reg );
void SetVidReg( address_space &space, uint16_t reg, uint16_t val );
- void crospuzl(machine_config &config);
- void crystal(machine_config &config);
- void crzyddz2(machine_config &config);
- void trivrus(machine_config &config);
void crospuzl_mem(address_map &map);
void crystal_mem(address_map &map);
void crzyddz2_mem(address_map &map);
+ void internal_map(address_map &map);
void trivrus_mem(address_map &map);
};
@@ -388,25 +395,6 @@ WRITE32_MEMBER(crystal_state::FlipCount_w)
}
}
-READ32_MEMBER(crystal_state::Input_r)
-{
- if (offset == 0)
- return ioport("P1_P2")->read();
- else if (offset == 1)
- return ioport("P3_P4")->read();
- else if( offset == 2)
- {
- uint8_t Port4 = ioport("SYSTEM")->read();
- if (!(Port4 & 0x10) && ((m_OldPort4 ^ Port4) & 0x10)) //coin buttons trigger IRQs
- IntReq(12);
- if (!(Port4 & 0x20) && ((m_OldPort4 ^ Port4) & 0x20))
- IntReq(19);
- m_OldPort4 = Port4;
- return /*dips*/ioport("DSW")->read() | (Port4 << 16);
- }
- return 0;
-}
-
WRITE32_MEMBER(crystal_state::IntAck_w)
{
uint32_t IntPend = space.read_dword(0x01800c0c);
@@ -438,15 +426,6 @@ IRQ_CALLBACK_MEMBER(crystal_state::icallback)
return 0; //This should never happen
}
-WRITE32_MEMBER(crystal_state::Banksw_w)
-{
- m_Bank = (data >> 1) & 7;
- if (m_Bank <= 2)
- membank("bank1")->set_base(memregion("user1")->base() + m_Bank * 0x1000000);
- else
- membank("bank1")->set_base(memregion("user2")->base());
-}
-
uint32_t *crystal_state::TimerRegsPtr(int which) const
{
return &m_sysregs[0x1400/4 + which * 8/4];
@@ -458,7 +437,7 @@ void crystal_state::TimerStart(int which)
int PD = (regs[0] >> 8) & 0xff;
int TCV = regs[1] & 0xffff;
- attotime period = attotime::from_hz(43000000) * ((PD + 1) * (TCV + 1));
+ attotime period = attotime::from_hz(14318180 * 3) * ((PD + 1) * (TCV + 1)); // TODO : related to CPU clock
m_Timer[which]->adjust(period);
// printf("timer %d start, PD = %x TCV = %x period = %s\n", which, PD, TCV, period.as_string());
@@ -479,9 +458,10 @@ TIMER_CALLBACK_MEMBER(crystal_state::Timercb)
IntReq(num[which]);
}
-void crystal_state::Timer_w( address_space &space, int which, uint32_t data, uint32_t mem_mask )
+template<int Which>
+WRITE32_MEMBER(crystal_state::Timer_w)
{
- uint32_t *regs = TimerRegsPtr(which);
+ uint32_t *regs = TimerRegsPtr(Which);
uint32_t old = regs[0];
data = COMBINE_DATA(&regs[0]);
@@ -490,82 +470,253 @@ void crystal_state::Timer_w( address_space &space, int which, uint32_t data, uin
{
if (data & 1)
{
- TimerStart(which);
+ TimerStart(Which);
}
else
{
// Timer stop
- m_Timer[which]->adjust(attotime::never);
-// printf("timer %d stop\n", which);
+ m_Timer[Which]->adjust(attotime::never);
+// printf("timer %d stop\n", Which);
}
}
}
-WRITE32_MEMBER(crystal_state::Timer0_w)
+template<int Which>
+READ32_MEMBER(crystal_state::Timer_r)
{
- Timer_w(space, 0, data, mem_mask);
+ return *TimerRegsPtr(Which);
}
-READ32_MEMBER(crystal_state::Timer0_r)
+template<int Which>
+READ32_MEMBER(crystal_state::DMA_r)
{
- return *TimerRegsPtr(0);
+ return m_DMActrl[Which];
}
-WRITE32_MEMBER(crystal_state::Timer1_w)
+template<int Which>
+WRITE32_MEMBER(crystal_state::DMA_w)
{
- Timer_w(space, 1, data, mem_mask);
-}
+ if (((data ^ m_DMActrl[Which]) & (1 << 10)) && (data & (1 << 10))) //DMAOn
+ {
+ uint32_t CTR = data;
+ uint32_t SRC = space.read_dword(0x01800804 + Which * 0x10);
+ uint32_t DST = space.read_dword(0x01800808 + Which * 0x10);
+ uint32_t CNT = space.read_dword(0x0180080C + Which * 0x10);
+ int i;
-READ32_MEMBER(crystal_state::Timer1_r)
-{
- return *TimerRegsPtr(1);
+ if (CTR & 0x2) //32 bits
+ {
+ for (i = 0; i < CNT; ++i)
+ {
+ uint32_t v = space.read_dword(SRC + i * 4);
+ space.write_dword(DST + i * 4, v);
+ }
+ }
+ else if (CTR & 0x1) //16 bits
+ {
+ for (i = 0; i < CNT; ++i)
+ {
+ uint16_t v = space.read_word(SRC + i * 2);
+ space.write_word(DST + i * 2, v);
+ }
+ }
+ else //8 bits
+ {
+ for (i = 0; i < CNT; ++i)
+ {
+ uint8_t v = space.read_byte(SRC + i);
+ space.write_byte(DST + i, v);
+ }
+ }
+ data &= ~(1 << 10);
+ space.write_dword(0x0180080C + Which * 0x10, 0);
+ IntReq(7 + Which);
+ }
+ COMBINE_DATA(&m_DMActrl[Which]);
}
-WRITE32_MEMBER(crystal_state::Timer2_w)
+READ32_MEMBER(crystal_state::crtc_r)
{
- Timer_w(space, 2, data, mem_mask);
+ uint32_t res = m_crtcregs[offset];
+ uint32_t hdisp = (m_crtcregs[0x0c / 4] + 1);
+ uint32_t vdisp = (m_crtcregs[0x1c / 4] + 1);
+ switch (offset)
+ {
+ case 0: // CRTC Status / Mode
+ if ((m_crtcregs[0x30 / 4] & 1) == 0) // Interrace
+ vdisp <<= 1;
+
+ if (m_screen->vpos() <= vdisp) // Vertical display enable status
+ res |= 0x4000;
+
+ if (m_screen->hpos() > hdisp) // horizontal & vertical blank period
+ res &= ~0x2000;
+ else
+ res |= 0x2000;
+
+ break;
+ default:
+ break;
+ }
+ return res;
}
-READ32_MEMBER(crystal_state::Timer2_r)
+WRITE32_MEMBER(crystal_state::crtc_w)
{
- return *TimerRegsPtr(2);
+ if (((m_crtcregs[0] & 0x0100) == 0x0100) && (offset > 0)) // Write protect
+ return;
+
+ uint32_t old = m_crtcregs[offset];
+ switch (offset * 4)
+ {
+ case 0: // CRTC Status / Mode Register (CRTMOD)
+ mem_mask &= ~0xfffffc00; // Bit 31-10 Reserved
+ break;
+ case 0x04: // CRTC Timing Control Register (CRTTIM)
+ mem_mask &= ~0xffffc000; // Bit 31-14 Reserved
+ break;
+ case 0x08: // Horizontal Sync Width / Back Porch Register (HSWBP)
+ mem_mask &= ~0xffff0000; // Bit 31-16 Reserved
+ break;
+ case 0x0c: // Horizontal Display Total Register (HDISP)
+ mem_mask &= ~0xfffffc00; // Bit 31-10 Reserved
+ break;
+ case 0x10: // Horizontal Sync Front Porch Register (HSFP)
+ mem_mask &= ~0xfffffe00; // Bit 31-9 Reserved
+ break;
+ case 0x14: // Field Window Bound Register (FWINB)
+ mem_mask &= ~0xffff80c0; // Bit 31-15, 7-6 Reserved
+ break;
+ case 0x18: // Vertical Sync Back Porch Register (VSBP)
+ mem_mask &= ~0xffffff00; // Bit 31-8 Reserved
+ break;
+ case 0x1c: // Vertical Display Total Register (VDISP)
+ mem_mask &= ~0xfffffe00; // Bit 31-9 Reserved
+ break;
+ case 0x20: // Horizontal Total Register (HTOT)
+ mem_mask &= ~0xffffe000; // Bit 31-13 Reserved
+ break;
+ case 0x24: // Vertical Total Register (VTOT)
+ mem_mask &= ~0xfffff000; // Bit 31-12 Reserved
+ break;
+ case 0x28: // Horizontal Line Back Porch Register (HLBP)
+ mem_mask &= ~0xfffffc00; // Bit 31-10 Reserved
+ break;
+ case 0x2c: // CRT Display Start Address 0 Register (STAD0)
+ mem_mask &= ~0xffff8000; // Bit 31-15 Reserved
+ break;
+ case 0x30: // CRT Display Start Address 1 Register (STAD1)
+ mem_mask &= ~0xffff8000; // Bit 31-15 Reserved
+ break;
+ case 0x38: // Light Pen 0 X Register (LIGHT0X)
+ mem_mask &= ~0xfffff800; // Bit 31-11 Reserved
+ break;
+ case 0x3c: // Light Pen 0 Y Register (LIGHT0Y)
+ mem_mask &= ~0xfffffe00; // Bit 31-9 Reserved
+ break;
+ case 0x40: // Light Pen 1 X Register (LIGHT1X)
+ mem_mask &= ~0xfffff800; // Bit 31-11 Reserved
+ break;
+ case 0x44: // Light Pen 1 Y Register (LIGHT1Y)
+ mem_mask &= ~0xfffffe00; // Bit 31-9 Reserved
+ break;
+ case 0x48: // Light Pen Input Control Register (LIGHTC)
+ mem_mask &= ~0xfffffffc; // Bit 31-2 Reserved
+ break;
+ default:
+ return;
+ }
+ COMBINE_DATA(&m_crtcregs[offset]);
+ if (((offset == (0xc / 4)) || (offset == (0x1c / 4)) || (offset == (0x30 / 4))) && (old ^ m_crtcregs[offset]))
+ crtc_update();
+
}
-WRITE32_MEMBER(crystal_state::Timer3_w)
+void crystal_state::crtc_update()
{
- Timer_w(space, 3, data, mem_mask);
+ // TODO : Implement other CRTC parameters
+ uint32_t hdisp = m_crtcregs[0x0c / 4] + 1;
+ uint32_t vdisp = m_crtcregs[0x1c / 4] + 1;
+ if ((m_crtcregs[0x30 / 4] & 1) == 0) // Interrace
+ vdisp <<= 1;
+
+ rectangle visarea;
+ visarea.set(0, hdisp - 1, 0, vdisp - 1);
+ m_screen->configure(hdisp, vdisp, visarea, m_screen->frame_period().attoseconds() );
}
-READ32_MEMBER(crystal_state::Timer3_r)
+void crystal_state::internal_map(address_map &map)
{
- return *TimerRegsPtr(3);
+// map(0x00000000, 0x00ffffff) // Local ROM
+// map(0x01000000, 0x010fffff) // Peripheral Device 0
+// map(0x01100000, 0x011fffff) // Peripheral Device 1
+// map(0x01200000, 0x012fffff) // Peripheral Device 2
+// map(0x01300000, 0x013fffff) // Peripheral Device 3
+// map(0x01400000, 0x014fffff) // Peripheral Device 4
+// map(0x01500000, 0x015fffff) // Peripheral Device 5
+// map(0x01600000, 0x016fffff) // Peripheral Device 6
+// map(0x01700000, 0x017fffff) // Peripheral Device 7
+// map(0x01800000, 0x01ffffff) // Internal Registers(VRender0, or Amazon)
+
+ map(0x01800000, 0x0180ffff).ram().share("sysregs");
+// map(0x01800000, 0x018003ff) // System/General
+// map(0x01800400, 0x018007ff) // Local Memory Controller
+// map(0x01800800, 0x01800bff) // DMA
+ map(0x01800800, 0x01800803).rw(FUNC(crystal_state::DMA_r<0>), FUNC(crystal_state::DMA_w<0>));
+ map(0x01800810, 0x01800813).rw(FUNC(crystal_state::DMA_r<1>), FUNC(crystal_state::DMA_w<1>));
+// map(0x01800c00, 0x01800fff) // Interrupt Controller
+ map(0x01800c04, 0x01800c07).w(FUNC(crystal_state::IntAck_w));
+// map(0x01801000, 0x018013ff) // UART
+// map(0x01801400, 0x018017ff) // Timer & Counter
+ map(0x01801400, 0x01801403).rw(FUNC(crystal_state::Timer_r<0>), FUNC(crystal_state::Timer_w<0>));
+ map(0x01801408, 0x0180140b).rw(FUNC(crystal_state::Timer_r<1>), FUNC(crystal_state::Timer_w<1>));
+ map(0x01801410, 0x01801413).rw(FUNC(crystal_state::Timer_r<2>), FUNC(crystal_state::Timer_w<2>));
+ map(0x01801418, 0x0180141b).rw(FUNC(crystal_state::Timer_r<3>), FUNC(crystal_state::Timer_w<3>));
+// map(0x01801800, 0x01801bff) // Pulse Width Modulation
+// map(0x01802000, 0x018023ff) // PIO (Port)
+// map(0x01802004, 0x01802007).rw(FUNC(crystal_state::PIO_r), FUNC(crystal_state::PIO_w)); // PIOLDAT
+// map(0x01802008, 0x0180200b) // PIOEDAT
+// map(0x01802400, 0x018027ff) // Peripheral Chip Select
+// map(0x01802800, 0x01802bff) // SIO
+// map(0x01803400, 0x018037ff) // CRT Controller
+ map(0x01803400, 0x018037ff).rw(FUNC(crystal_state::crtc_r), FUNC(crystal_state::crtc_w)).share("crtcregs");
+// map(0x01804000, 0x018043ff) // RAMDAC & PLL
+
+// map(0x02000000, 0x02ffffff).ram().share("workram"); // Local RAM/DRAM (Max.16MB)
+
+ map(0x03000000, 0x0300ffff).ram().share("vidregs");
+ map(0x030000a4, 0x030000a7).rw(FUNC(crystal_state::FlipCount_r), FUNC(crystal_state::FlipCount_w));
+// map(0x03800000, 0x03ffffff).ram().share("textureram"); // Texture Buffer Memory (Max.8MB)
+// map(0x04000000, 0x047fffff).ram().share("frameram"); // Frame Buffer Memory (Max.8MB)
+ map(0x04800000, 0x04800fff).rw(m_vr0snd, FUNC(vr0sound_device::vr0_snd_read), FUNC(vr0sound_device::vr0_snd_write));
+
+// map(0x05000000, 0x0fffffff) // Expansion ROM
}
-READ32_MEMBER(crystal_state::FlashCmd_r)
+
+READ32_MEMBER(crystal_state::Input_r)
{
- if ((m_FlashCmd & 0xff) == 0xff)
- {
- if (m_Bank <= 2)
- {
- uint32_t *ptr = (uint32_t*)(memregion("user1")->base() + m_Bank * 0x1000000);
- return ptr[0];
- }
- else
- return 0xffffffff;
- }
- if ((m_FlashCmd & 0xff) == 0x90)
+ if (offset == 0)
+ return ioport("P1_P2")->read();
+ else if (offset == 1)
+ return ioport("P3_P4")->read();
+ else if( offset == 2)
{
- if (m_Bank <= 2)
- return 0x00180089; //Intel 128MBit
- else
- return 0xffffffff;
+ uint8_t Port4 = ioport("SYSTEM")->read();
+ if (!(Port4 & 0x10) && ((m_OldPort4 ^ Port4) & 0x10)) //coin buttons trigger IRQs
+ IntReq(12);
+ if (!(Port4 & 0x20) && ((m_OldPort4 ^ Port4) & 0x20))
+ IntReq(19);
+ m_OldPort4 = Port4;
+ return /*dips*/ioport("DSW")->read() | (Port4 << 16);
}
return 0;
}
-WRITE32_MEMBER(crystal_state::FlashCmd_w)
+WRITE32_MEMBER(crystal_state::Banksw_w)
{
- m_FlashCmd = data;
+ m_Bank = (data >> 1) & 7;
+ m_mainbank->set_entry(m_Bank);
}
READ32_MEMBER(crystal_state::PIO_r)
@@ -591,98 +742,50 @@ WRITE32_MEMBER(crystal_state::PIO_w)
COMBINE_DATA(&m_PIO);
}
-void crystal_state::DMA_w( address_space &space, int which, uint32_t data, uint32_t mem_mask )
+READ32_MEMBER(crystal_state::FlashCmd_r)
{
- if (((data ^ m_DMActrl[which]) & (1 << 10)) && (data & (1 << 10))) //DMAOn
+ if ((m_FlashCmd & 0xff) == 0xff)
{
- uint32_t CTR = data;
- uint32_t SRC = space.read_dword(0x01800804 + which * 0x10);
- uint32_t DST = space.read_dword(0x01800808 + which * 0x10);
- uint32_t CNT = space.read_dword(0x0180080C + which * 0x10);
- int i;
-
- if (CTR & 0x2) //32 bits
- {
- for (i = 0; i < CNT; ++i)
- {
- uint32_t v = space.read_dword(SRC + i * 4);
- space.write_dword(DST + i * 4, v);
- }
- }
- else if (CTR & 0x1) //16 bits
+ if (m_Bank < m_maxbank)
{
- for (i = 0; i < CNT; ++i)
- {
- uint16_t v = space.read_word(SRC + i * 2);
- space.write_word(DST + i * 2, v);
- }
- }
- else //8 bits
- {
- for (i = 0; i < CNT; ++i)
- {
- uint8_t v = space.read_byte(SRC + i);
- space.write_byte(DST + i, v);
- }
+ uint32_t *ptr = (uint32_t*)(m_mainbank->base());
+ return ptr[0];
}
- data &= ~(1 << 10);
- space.write_dword(0x0180080C + which * 0x10, 0);
- IntReq(7 + which);
+ else
+ return 0xffffffff;
}
- COMBINE_DATA(&m_DMActrl[which]);
-}
-
-READ32_MEMBER(crystal_state::DMA0_r)
-{
- return m_DMActrl[0];
-}
-
-WRITE32_MEMBER(crystal_state::DMA0_w)
-{
- DMA_w(space, 0, data, mem_mask);
-}
-
-READ32_MEMBER(crystal_state::DMA1_r)
-{
- return m_DMActrl[1];
+ if ((m_FlashCmd & 0xff) == 0x90)
+ {
+ if (m_Bank < m_maxbank)
+ return 0x00180089; //Intel 128MBit
+ else
+ return 0xffffffff;
+ }
+ return 0;
}
-WRITE32_MEMBER(crystal_state::DMA1_w)
+WRITE32_MEMBER(crystal_state::FlashCmd_w)
{
- DMA_w(space, 1, data, mem_mask);
+ m_FlashCmd = data;
}
-
void crystal_state::crystal_mem(address_map &map)
{
+ internal_map(map);
map(0x00000000, 0x0001ffff).rom().nopw();
map(0x01200000, 0x0120000f).r(FUNC(crystal_state::Input_r));
map(0x01280000, 0x01280003).w(FUNC(crystal_state::Banksw_w));
map(0x01400000, 0x0140ffff).ram().share("nvram");
- map(0x01800000, 0x0180ffff).ram().share("sysregs");
-
- map(0x01800800, 0x01800803).rw(FUNC(crystal_state::DMA0_r), FUNC(crystal_state::DMA0_w));
- map(0x01800810, 0x01800813).rw(FUNC(crystal_state::DMA1_r), FUNC(crystal_state::DMA1_w));
-
- map(0x01800c04, 0x01800c07).w(FUNC(crystal_state::IntAck_w));
-
- map(0x01801400, 0x01801403).rw(FUNC(crystal_state::Timer0_r), FUNC(crystal_state::Timer0_w));
- map(0x01801408, 0x0180140b).rw(FUNC(crystal_state::Timer1_r), FUNC(crystal_state::Timer1_w));
- map(0x01801410, 0x01801413).rw(FUNC(crystal_state::Timer2_r), FUNC(crystal_state::Timer2_w));
- map(0x01801418, 0x0180141b).rw(FUNC(crystal_state::Timer3_r), FUNC(crystal_state::Timer3_w));
map(0x01802004, 0x01802007).rw(FUNC(crystal_state::PIO_r), FUNC(crystal_state::PIO_w));
map(0x02000000, 0x027fffff).ram().share("workram");
- map(0x03000000, 0x0300ffff).ram().share("vidregs");
- map(0x030000a4, 0x030000a7).rw(FUNC(crystal_state::FlipCount_r), FUNC(crystal_state::FlipCount_w));
map(0x03800000, 0x03ffffff).ram().share("textureram");
map(0x04000000, 0x047fffff).ram().share("frameram");
- map(0x04800000, 0x04800fff).rw("vrender", FUNC(vrender0_device::vr0_snd_read), FUNC(vrender0_device::vr0_snd_write));
- map(0x05000000, 0x05ffffff).bankr("bank1");
+ map(0x05000000, 0x05ffffff).bankr("mainbank");
map(0x05000000, 0x05000003).rw(FUNC(crystal_state::FlashCmd_r), FUNC(crystal_state::FlashCmd_w));
map(0x44414F4C, 0x44414F7F).ram().share("reset_patch");
@@ -691,7 +794,7 @@ void crystal_state::crystal_mem(address_map &map)
// Trivia R Us
// To do: touch panel, RTC
-READ32_MEMBER(crystal_state::trivrus_input_r)
+READ8_MEMBER(crystal_state::trivrus_input_r)
{
switch (m_trivrus_input)
{
@@ -703,21 +806,21 @@ READ32_MEMBER(crystal_state::trivrus_input_r)
case 6: return ioport("DSW")->read();
}
logerror("%s: unknown input %02x read\n", machine().describe_context(), m_trivrus_input);
- return 0xffffffff;
+ return 0xff;
}
-WRITE32_MEMBER(crystal_state::trivrus_input_w)
+WRITE8_MEMBER(crystal_state::trivrus_input_w)
{
- if (ACCESSING_BITS_0_7)
- m_trivrus_input = data & 0xff;
+ m_trivrus_input = data & 0xff;
}
void crystal_state::trivrus_mem(address_map &map)
{
+ internal_map(map);
map(0x00000000, 0x0007ffff).rom().nopw();
// 0x01280000 & 0x0000ffff (written at boot)
- map(0x01500000, 0x01500003).rw(FUNC(crystal_state::trivrus_input_r), FUNC(crystal_state::trivrus_input_w));
+ map(0x01500000, 0x01500000).rw(FUNC(crystal_state::trivrus_input_r), FUNC(crystal_state::trivrus_input_w));
// 0x01500010 & 0x000000ff = sec
// 0x01500010 & 0x00ff0000 = min
// 0x01500014 & 0x000000ff = hour
@@ -726,29 +829,14 @@ void crystal_state::trivrus_mem(address_map &map)
// 0x0150001c & 0x000000ff = year - 2000
map(0x01600000, 0x01607fff).ram().share("nvram");
- map(0x01800000, 0x0180ffff).ram().share("sysregs");
-
- map(0x01800800, 0x01800803).rw(FUNC(crystal_state::DMA0_r), FUNC(crystal_state::DMA0_w));
- map(0x01800810, 0x01800813).rw(FUNC(crystal_state::DMA1_r), FUNC(crystal_state::DMA1_w));
-
- map(0x01800c04, 0x01800c07).w(FUNC(crystal_state::IntAck_w));
-
- map(0x01801400, 0x01801403).rw(FUNC(crystal_state::Timer0_r), FUNC(crystal_state::Timer0_w));
- map(0x01801408, 0x0180140b).rw(FUNC(crystal_state::Timer1_r), FUNC(crystal_state::Timer1_w));
- map(0x01801410, 0x01801413).rw(FUNC(crystal_state::Timer2_r), FUNC(crystal_state::Timer2_w));
- map(0x01801418, 0x0180141b).rw(FUNC(crystal_state::Timer3_r), FUNC(crystal_state::Timer3_w));
map(0x01802004, 0x01802007).rw(FUNC(crystal_state::PIO_r), FUNC(crystal_state::PIO_w));
map(0x02000000, 0x027fffff).ram().share("workram");
-
- map(0x03000000, 0x0300ffff).ram().share("vidregs");
- map(0x030000a4, 0x030000a7).rw(FUNC(crystal_state::FlipCount_r), FUNC(crystal_state::FlipCount_w));
map(0x03800000, 0x03ffffff).ram().share("textureram");
map(0x04000000, 0x047fffff).ram().share("frameram");
- map(0x04800000, 0x04800fff).rw("vrender", FUNC(vrender0_device::vr0_snd_read), FUNC(vrender0_device::vr0_snd_write));
- map(0x05000000, 0x05ffffff).bankr("bank1");
+ map(0x05000000, 0x05ffffff).bankr("mainbank");
map(0x05000000, 0x05000003).rw(FUNC(crystal_state::FlashCmd_r), FUNC(crystal_state::FlashCmd_w));
// AM_RANGE(0x44414F4C, 0x44414F7F) AM_RAM AM_SHARE("reset_patch")
@@ -809,6 +897,7 @@ crzyddz2 in out
void crystal_state::crzyddz2_mem(address_map &map)
{
+ internal_map(map);
map(0x00000000, 0x00ffffff).rom().nopw();
map(0x01280000, 0x01280003).w(FUNC(crystal_state::Banksw_w));
@@ -816,29 +905,14 @@ void crystal_state::crzyddz2_mem(address_map &map)
map(0x01500000, 0x01500003).portr("P1_P2");
map(0x01500004, 0x01500007).r(FUNC(crystal_state::crzyddz2_key_r));
- map(0x01800000, 0x0180ffff).ram().share("sysregs");
-
- map(0x01800800, 0x01800803).rw(FUNC(crystal_state::DMA0_r), FUNC(crystal_state::DMA0_w));
- map(0x01800810, 0x01800813).rw(FUNC(crystal_state::DMA1_r), FUNC(crystal_state::DMA1_w));
-
- map(0x01800c04, 0x01800c07).w(FUNC(crystal_state::IntAck_w));
-
- map(0x01801400, 0x01801403).rw(FUNC(crystal_state::Timer0_r), FUNC(crystal_state::Timer0_w));
- map(0x01801408, 0x0180140b).rw(FUNC(crystal_state::Timer1_r), FUNC(crystal_state::Timer1_w));
- map(0x01801410, 0x01801413).rw(FUNC(crystal_state::Timer2_r), FUNC(crystal_state::Timer2_w));
- map(0x01801418, 0x0180141b).rw(FUNC(crystal_state::Timer3_r), FUNC(crystal_state::Timer3_w));
map(0x01802004, 0x01802007).rw(FUNC(crystal_state::PIO_r), FUNC(crystal_state::crzyddz2_PIO_w));
map(0x02000000, 0x027fffff).ram().share("workram");
-
- map(0x03000000, 0x0300ffff).ram().share("vidregs");
- map(0x030000a4, 0x030000a7).rw(FUNC(crystal_state::FlipCount_r), FUNC(crystal_state::FlipCount_w));
map(0x03800000, 0x03ffffff).ram().share("textureram");
map(0x04000000, 0x047fffff).ram().share("frameram");
- map(0x04800000, 0x04800fff).rw("vrender", FUNC(vrender0_device::vr0_snd_read), FUNC(vrender0_device::vr0_snd_write));
- map(0x05000000, 0x05ffffff).bankr("bank1");
+ map(0x05000000, 0x05ffffff).bankr("mainbank");
map(0x05000000, 0x05000003).rw(FUNC(crystal_state::FlashCmd_r), FUNC(crystal_state::FlashCmd_w));
// AM_RANGE(0x44414F4C, 0x44414F7F) AM_RAM AM_SHARE("reset_patch")
@@ -897,23 +971,28 @@ loop:
#endif
}
-void crystal_state::crystal_banksw_postload()
-{
- if (m_Bank <= 2)
- membank("bank1")->set_base(memregion("user1")->base() + m_Bank * 0x1000000);
- else
- membank("bank1")->set_base(memregion("user2")->base());
-}
-
void crystal_state::machine_start()
{
- int i;
-
- for (i = 0; i < 4; i++)
+ for (int i = 0; i < 4; i++)
m_Timer[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(crystal_state::Timercb),this), (void*)(uintptr_t)i);
PatchReset();
+ if (m_mainbank)
+ {
+ m_maxbank = (m_flash) ? m_flash.bytes() / 0x1000000 : 0;
+ uint8_t *dummy_region = auto_alloc_array(machine(), uint8_t, 0x1000000);
+ std::fill_n(&dummy_region[0], 0x1000000, 0xff); // 0xff Filled at Unmapped area
+ uint8_t *ROM = (m_flash) ? (uint8_t *)&m_flash[0] : dummy_region;
+ for (int i = 0; i < 8; i++)
+ {
+ if ((i < m_maxbank))
+ m_mainbank->configure_entry(i, ROM + i * 0x1000000);
+ else
+ m_mainbank->configure_entry(i, dummy_region);
+ }
+ }
+
#ifdef IDLE_LOOP_SPEEDUP
save_item(NAME(m_FlipCntRead));
#endif
@@ -926,18 +1005,19 @@ void crystal_state::machine_start()
save_item(NAME(m_DMActrl));
save_item(NAME(m_OldPort4));
save_item(NAME(m_trivrus_input));
- machine().save().register_postload(save_prepost_delegate(FUNC(crystal_state::crystal_banksw_postload), this));
}
void crystal_state::machine_reset()
{
- memset(m_sysregs, 0, 0x10000);
- memset(m_vidregs, 0, 0x10000);
+ std::fill_n(&m_sysregs[0], m_sysregs.bytes() / 4, 0);
+ std::fill_n(&m_vidregs[0], m_vidregs.bytes() / 4, 0);
+ std::fill_n(&m_crtcregs[0], m_crtcregs.bytes() / 4, 0);
+ m_crtcregs[1] = 0x00000022;
m_FlipCount = 0;
m_IntHigh = 0;
m_Bank = 0;
- membank("bank1")->set_base(memregion("user1")->base() + 0);
+ m_mainbank->set_entry(m_Bank);
m_FlashCmd = 0xff;
m_OldPort4 = 0;
@@ -950,7 +1030,7 @@ void crystal_state::machine_reset()
m_Timer[i]->adjust(attotime::never);
}
- m_video->set_areas(m_textureram, m_frameram);
+ m_vr0snd->set_areas(m_textureram, m_frameram);
#ifdef IDLE_LOOP_SPEEDUP
m_FlipCntRead = 0;
#endif
@@ -971,25 +1051,13 @@ void crystal_state::SetVidReg( address_space &space, uint16_t reg, uint16_t val
}
-uint32_t crystal_state::screen_update_crystal(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+uint32_t crystal_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
- int xres = 320;
- int yres = 240;
-
- // probably more registers around here control height / interlace enable etc.
- // 0x341c looks like height, but doesn't change for interlace mode.
- xres = m_sysregs[0x340c / 4]+1;
- if (xres > 640) xres = 640;
-
- // force double height if 640 wide (probably a reg for this)
- if (xres == 640) yres = 480;
-
-
- rectangle visarea;
- visarea.set(0, xres-1, 0, yres-1);
- m_screen->configure(xres, yres, visarea, m_screen->frame_period().attoseconds() );
-
-
+ if ((m_crtcregs[0] & 0x0200) == 0x0200) // Blank Screen
+ {
+ bitmap.fill(0, cliprect);
+ return 0;
+ }
address_space &space = m_maincpu->space(AS_PROGRAM);
int DoFlip;
@@ -1001,7 +1069,7 @@ uint32_t crystal_state::screen_update_crystal(screen_device &screen, bitmap_ind1
uint16_t *srcline;
int y;
uint16_t head, tail;
- uint32_t width = screen.width();
+ uint32_t width = cliprect.width();
if (GetVidReg(space, 0x8e) & 1)
{
@@ -1034,7 +1102,7 @@ uint32_t crystal_state::screen_update_crystal(screen_device &screen, bitmap_ind1
while ((head & 0x7ff) != (tail & 0x7ff))
{
// ERROR: This cast is NOT endian-safe without the use of BYTE/WORD/DWORD_XOR_* macros!
- DoFlip = m_vr0->vrender0_ProcessPacket(0x03800000 + head * 64, DrawDest, reinterpret_cast<uint8_t*>(m_textureram.target()));
+ DoFlip = m_vr0vid->vrender0_ProcessPacket(0x03800000 + head * 64, DrawDest, reinterpret_cast<uint8_t*>(m_textureram.target()));
head++;
head &= 0x7ff;
if (DoFlip)
@@ -1045,13 +1113,14 @@ uint32_t crystal_state::screen_update_crystal(screen_device &screen, bitmap_ind1
SetVidReg(space, 0x8e, GetVidReg(space, 0x8e) ^ 1);
srcline = (uint16_t *) Visible;
- for (y = 0; y < screen.height(); y++)
- memcpy(&bitmap.pix16(y), &srcline[y * 1024], width * 2);
+ uint32_t dx = cliprect.left();
+ for (y = cliprect.top(); y <= cliprect.bottom(); y++)
+ std::copy_n( &srcline[(y * 1024) + dx], width, &bitmap.pix16(y, dx));
return 0;
}
-WRITE_LINE_MEMBER(crystal_state::screen_vblank_crystal)
+WRITE_LINE_MEMBER(crystal_state::screen_vblank)
{
// rising edge
if (state)
@@ -1079,14 +1148,10 @@ WRITE_LINE_MEMBER(crystal_state::screen_vblank_crystal)
m_FlipCount--;
}
+ IntReq(24); //VRender0 VBlank
}
}
-INTERRUPT_GEN_MEMBER(crystal_state::crystal_interrupt)
-{
- IntReq(24); //VRender0 VBlank
-}
-
static INPUT_PORTS_START(crystal)
PORT_START("P1_P2")
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
@@ -1238,52 +1303,47 @@ INPUT_PORTS_END
static INPUT_PORTS_START(trivrus)
PORT_START("IN1")
- PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Up") PORT_CODE(KEYCODE_UP)
- PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Left/True") PORT_CODE(KEYCODE_LEFT)
- PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Down") PORT_CODE(KEYCODE_DOWN)
- PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Up") PORT_CODE(KEYCODE_UP)
+ PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Left/True") PORT_CODE(KEYCODE_LEFT)
+ PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Down") PORT_CODE(KEYCODE_DOWN)
PORT_START("IN2")
- PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Enter/Exit")
- PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Next")
- PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Right/False") PORT_CODE(KEYCODE_RIGHT)
- PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(1)
- PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Enter/Exit")
+ PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Next")
+ PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Right/False") PORT_CODE(KEYCODE_RIGHT)
+ PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(1)
+ PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("IN3")
- PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Sound")
- PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Sound")
+ PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("IN4")
- PORT_BIT( 0x000000ff, IP_ACTIVE_LOW, IPT_OTHER )PORT_CODE(KEYCODE_9)
- PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_OTHER )PORT_CODE(KEYCODE_9)
PORT_START("IN5")
- PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_SERVICE1 ) // Free Game
- PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) // Free Game
+ PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW ) // Setup
- PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("DSW")
PORT_DIPNAME( 0x01, 0x01, "Interlace?" )
@@ -1310,7 +1370,6 @@ static INPUT_PORTS_START(trivrus)
PORT_DIPNAME( 0x80, 0x80, "Touch Screen" )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
- PORT_BIT( 0xffffff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
static INPUT_PORTS_START(crospuzl)
@@ -1486,90 +1545,82 @@ static INPUT_PORTS_START(crzyddz2)
INPUT_PORTS_END
-MACHINE_CONFIG_START(crystal_state::crystal)
-
- MCFG_DEVICE_ADD("maincpu", SE3208, 43000000)
- MCFG_DEVICE_PROGRAM_MAP(crystal_mem)
- MCFG_DEVICE_VBLANK_INT_DRIVER("screen", crystal_state, crystal_interrupt)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(crystal_state, icallback)
+void crystal_state::crystal(machine_config &config)
+{
+ SE3208(config, m_maincpu, 14318180 * 3); // TODO : different between each PCBs
+ m_maincpu->set_addrmap(AS_PROGRAM, &crystal_state::crystal_mem);
+ m_maincpu->set_irq_acknowledge_callback(FUNC(crystal_state::icallback));
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
- MCFG_SCREEN_ADD("screen", RASTER)
- MCFG_SCREEN_REFRESH_RATE(60)
- MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
- MCFG_SCREEN_SIZE(640, 480)
- MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 479)
- MCFG_SCREEN_UPDATE_DRIVER(crystal_state, screen_update_crystal)
- MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, crystal_state, screen_vblank_crystal))
- MCFG_SCREEN_PALETTE("palette")
+ SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+ m_screen->set_refresh(HZ_TO_ATTOSECONDS(60));
+ m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+ m_screen->set_size(640, 480);
+ m_screen->set_visarea(0, 639, 0, 479);
+ m_screen->set_screen_update(FUNC(crystal_state::screen_update));
+ m_screen->screen_vblank().set(FUNC(crystal_state::screen_vblank));
+ m_screen->set_palette("palette");
- MCFG_DEVICE_ADD("vr0", VIDEO_VRENDER0, 0, "maincpu")
+ VIDEO_VRENDER0(config, m_vr0vid, 14318180, m_maincpu);
- MCFG_PALETTE_ADD_RRRRRGGGGGGBBBBB("palette")
+ PALETTE(config, "palette", 65536).set_init("palette", FUNC(palette_device::palette_init_RRRRRGGGGGGBBBBB));
- MCFG_DEVICE_ADD("rtc", DS1302, 32.768_kHz_XTAL)
+ DS1302(config, m_ds1302, 32.768_kHz_XTAL);
SPEAKER(config, "lspeaker").front_left();
SPEAKER(config, "rspeaker").front_right();
- MCFG_SOUND_VRENDER0_ADD("vrender", 0)
- MCFG_VR0_REGBASE(0x04800000)
- MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
- MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
-MACHINE_CONFIG_END
+ SOUND_VRENDER0(config, m_vr0snd, 0);
+ m_vr0snd->add_route(0, "lspeaker", 1.0);
+ m_vr0snd->add_route(1, "rspeaker", 1.0);
+}
-MACHINE_CONFIG_START(crystal_state::trivrus)
+void crystal_state::trivrus(machine_config &config)
+{
crystal(config);
- MCFG_DEVICE_MODIFY("maincpu")
- MCFG_DEVICE_PROGRAM_MAP(trivrus_mem)
-MACHINE_CONFIG_END
+ m_maincpu->set_addrmap(AS_PROGRAM, &crystal_state::trivrus_mem);
+}
-MACHINE_CONFIG_START(crystal_state::crospuzl)
+void crystal_state::crospuzl(machine_config &config)
+{
crystal(config);
- MCFG_DEVICE_MODIFY("maincpu")
- MCFG_DEVICE_PROGRAM_MAP(crospuzl_mem)
-MACHINE_CONFIG_END
+ m_maincpu->set_addrmap(AS_PROGRAM, &crystal_state::crospuzl_mem);
+}
-MACHINE_CONFIG_START(crystal_state::crzyddz2)
+void crystal_state::crzyddz2(machine_config &config)
+{
crystal(config);
- MCFG_DEVICE_MODIFY("maincpu")
- MCFG_DEVICE_PROGRAM_MAP(crzyddz2_mem)
-MACHINE_CONFIG_END
+ m_maincpu->set_addrmap(AS_PROGRAM, &crystal_state::crzyddz2_mem);
+}
ROM_START( crysbios )
ROM_REGION( 0x20000, "maincpu", 0 ) // bios
ROM_LOAD("mx27l1000.u14", 0x000000, 0x020000, CRC(beff39a9) SHA1(b6f6dda58d9c82273f9422c1bd623411e58982cb) )
- ROM_REGION32_LE( 0x3000000, "user1", ROMREGION_ERASEFF ) // Flash
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
+ ROM_REGION32_LE( 0x1000000, "flash", ROMREGION_ERASEFF ) // Flash
ROM_END
ROM_START( crysking )
ROM_REGION( 0x20000, "maincpu", 0 ) // bios
ROM_LOAD("mx27l1000.u14", 0x000000, 0x020000, CRC(beff39a9) SHA1(b6f6dda58d9c82273f9422c1bd623411e58982cb))
- ROM_REGION32_LE( 0x3000000, "user1", 0 ) // Flash
+ ROM_REGION32_LE( 0x3000000, "flash", 0 ) // Flash
ROM_LOAD("bcsv0004f01.u1", 0x0000000, 0x1000000, CRC(8feff120) SHA1(2ea42fa893bff845b5b855e2556789f8354e9066) )
ROM_LOAD("bcsv0004f02.u2", 0x1000000, 0x1000000, CRC(0e799845) SHA1(419674ce043cb1efb18303f4cb7fdbbae642ee39) )
ROM_LOAD("bcsv0004f03.u3", 0x2000000, 0x1000000, CRC(659e2d17) SHA1(342c98f3f695ef4dea8b533612451c4d2fb58809) )
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
ROM_END
ROM_START( evosocc )
ROM_REGION( 0x20000, "maincpu", 0 ) // bios
ROM_LOAD("mx27l1000.u14", 0x000000, 0x020000, CRC(beff39a9) SHA1(b6f6dda58d9c82273f9422c1bd623411e58982cb))
- ROM_REGION32_LE( 0x3000000, "user1", 0 ) // Flash
+ ROM_REGION32_LE( 0x3000000, "flash", 0 ) // Flash
ROM_LOAD("bcsv0001u01", 0x0000000, 0x1000000, CRC(2581a0ea) SHA1(ee483ac60a3ed00a21cb515974cec4af19916a7d) )
ROM_LOAD("bcsv0001u02", 0x1000000, 0x1000000, CRC(47ef1794) SHA1(f573706c17d1342b9b7aed9b40b8b648f0bf58db) )
ROM_LOAD("bcsv0001u03", 0x2000000, 0x1000000, CRC(f396a2ec) SHA1(f305eb10856fb5d4c229a6b09d6a2fb21b24ce66) )
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
ROM_END
ROM_START( topbladv )
@@ -1579,11 +1630,8 @@ ROM_START( topbladv )
ROM_REGION( 0x4300, "pic", 0 ) // pic16c727 - we don't have a core for this
ROM_LOAD("top_blade_v_pic16c727.bin", 0x000000, 0x4300, CRC(9cdea57b) SHA1(884156085f9e780cdf719aedc2e8a0fd5983613b) )
-
- ROM_REGION32_LE( 0x3000000, "user1", 0 ) // Flash
+ ROM_REGION32_LE( 0x1000000, "flash", 0 ) // Flash
ROM_LOAD("flash.u1", 0x0000000, 0x1000000, CRC(bd23f640) SHA1(1d22aa2c828642bb7c1dfea4e13f777f95acc701) )
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
ROM_END
ROM_START( officeye )
@@ -1593,12 +1641,9 @@ ROM_START( officeye )
ROM_REGION( 0x4280, "pic", 0 ) // pic16f84a - we don't have a core for this
ROM_LOAD("office_yeo_in_cheon_ha_pic16f84a.bin", 0x000000, 0x4280, CRC(7561cdf5) SHA1(eade592823a110019b4af81a7dc56d01f7d6589f) )
-
- ROM_REGION32_LE( 0x3000000, "user1", 0 ) // Flash
+ ROM_REGION32_LE( 0x2000000, "flash", 0 ) // Flash
ROM_LOAD("flash.u1", 0x0000000, 0x1000000, CRC(d3f3eec4) SHA1(ea728415bd4906964b7d37f4379a8a3bd42a1c2d) )
ROM_LOAD("flash.u2", 0x1000000, 0x1000000, CRC(e4f85d0a) SHA1(2ddfa6b3a30e69754aa9d96434ff3d37784bfa57) )
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
ROM_END
ROM_START( donghaer )
@@ -1608,32 +1653,26 @@ ROM_START( donghaer )
ROM_REGION( 0x4280, "pic", 0 ) // pic16f84a - we don't have a core for this (or the dump in this case)
ROM_LOAD("donghaer_pic16f84a.bin", 0x000000, 0x4280, NO_DUMP )
- ROM_REGION32_LE( 0x3000000, "user1", 0 ) // Flash
+ ROM_REGION32_LE( 0x2000000, "flash", 0 ) // Flash
ROM_LOAD( "u1", 0x0000000, 0x1000000, CRC(61217ad7) SHA1(2593f1356aa850f4f9aa5d00bec822aa59c59224) )
ROM_LOAD( "u2", 0x1000000, 0x1000000, CRC(6d82f1a5) SHA1(036bd45f0daac1ffeaa5ad9774fc1b56e3c75ff9) )
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
ROM_END
ROM_START( trivrus )
ROM_REGION( 0x80000, "maincpu", 0 )
ROM_LOAD( "u4", 0x00000, 0x80000, CRC(2d2e9a11) SHA1(73e7b19a032eae21312ca80f8c42cc16725496a7) )
- ROM_REGION32_LE( 0x3000000, "user1", ROMREGION_ERASEFF ) // Flash
+ ROM_REGION32_LE( 0x2000000, "flash", ROMREGION_ERASEFF ) // Flash
ROM_LOAD( "u3", 0x000000, 0x1000010, CRC(ba901707) SHA1(e281ba07024cd19ef1ab72d2197014f7b1f4d30f) )
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
ROM_END
ROM_START( crospuzl ) /* This PCB uses ADC 'Amazon-LF' SoC, EISC CPU core - However PCBs have been see with a standard VRenderZERO+ MagicEyes EISC chip */
ROM_REGION( 0x80010, "maincpu", 0 )
ROM_LOAD("en29lv040a.u5", 0x000000, 0x80010, CRC(d50e8500) SHA1(d681cd18cd0e48854c24291d417d2d6d28fe35c1) )
- ROM_REGION32_LE( 0x8400010, "user1", ROMREGION_ERASEFF ) // Flash
+ ROM_REGION32_LE( 0x8400010, "flash", ROMREGION_ERASEFF ) // NAND Flash
// mostly empty, but still looks good
ROM_LOAD("k9f1g08u0a.riser", 0x000000, 0x8400010, CRC(7f3c88c3) SHA1(db3169a7b4caab754e9d911998a2ece13c65ce5b) )
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
ROM_END
ROM_START( psattack )
@@ -1646,10 +1685,6 @@ ROM_START( psattack )
DISK_REGION( "cfcard" )
DISK_IMAGE_READONLY( "psattack", 0, SHA1(e99cd0dafc33ec13bf56061f81dc7c0a181594ee) )
-
- // keep driver happy
- ROM_REGION32_LE( 0x3000000, "user1", ROMREGION_ERASEFF )
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF )
ROM_END
ROM_START( ddz )
@@ -1657,10 +1692,6 @@ ROM_START( ddz )
ROM_LOAD("ddz.001.rom", 0x000000, 0x400000, CRC(b379f823) SHA1(531885b35d668d22c75a9759994f4aca6eacb046) )
ROM_LOAD("ddz.002.rom", 0x400000, 0x400000, CRC(285c744d) SHA1(2f8bc70825e55e3114015cb263e786df35cde275) )
ROM_LOAD("ddz.003.rom", 0x800000, 0x400000, CRC(61c9b5c9) SHA1(0438417398403456a1c49408881797a94aa86f49) )
-
- // keep driver happy
- ROM_REGION32_LE( 0x3000000, "user1", ROMREGION_ERASEFF )
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF )
ROM_END
@@ -1700,10 +1731,6 @@ ROM_START( crzclass ) // PCB marked MAH-JONG
ROM_LOAD("tjf-mahjong-rom2.bin", 0x400000, 0x400000, CRC(2a04e84a) SHA1(189b16fd4314fd2a5f8a1214618b5db83f8ac59a) ) // SHARP LH28F320BJD-TTL80
ROM_LOAD("tjf-mahjong-rom3.bin", 0x800000, 0x400000, CRC(1cacf3f9) SHA1(e6c88c98aeb7df4098f8e20f412018617005724d) ) // SHARP LH28F320BJD-TTL80
// rom4 not populated
-
- // keep driver happy
- ROM_REGION32_LE( 0x3000000, "user1", ROMREGION_ERASEFF )
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF )
ROM_END
/***************************************************************************
@@ -1752,18 +1779,16 @@ Notes:
***************************************************************************/
ROM_START( crzyddz2 )
- ROM_REGION32_LE( 0x3000000, "user1", ROMREGION_ERASEFF ) // Flash
+ ROM_REGION32_LE( 0x1000000, "flash", 0 ) // Flash
ROM_LOAD( "rom.u48", 0x000000, 0x1000000, CRC(0f3a1987) SHA1(6cad943846c79db31226676c7391f32216cfff79) )
ROM_REGION( 0x1000000, "maincpu", ROMREGION_ERASEFF )
- ROM_COPY( "user1", 0x000000, 0x000000, 0x1000000 ) // copy flash here
+ ROM_COPY( "flash", 0x000000, 0x000000, 0x1000000 ) // copy flash here
ROM_LOAD( "27c322.u49", 0x000000, 0x0200000, CRC(b3177f39) SHA1(2a28bf8045bd2e053d88549b79fbc11f30ef9a32) ) // 1ST AND 2ND HALF IDENTICAL
ROM_CONTINUE( 0x000000, 0x0200000 )
ROM_REGION( 0x4280, "pic", 0 ) // hy04
ROM_LOAD("hy04", 0x000000, 0x4280, NO_DUMP )
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
ROM_END
/***************************************************************************
@@ -1776,23 +1801,21 @@ Red PCB, very similar to crzyddz2
***************************************************************************/
ROM_START( menghong )
- ROM_REGION32_LE( 0x3000000, "user1", ROMREGION_ERASEFF ) // Flash
+ ROM_REGION32_LE( 0x1000000, "flash", 0 ) // Flash
ROM_LOAD( "rom.u48", 0x000000, 0x1000000, CRC(e24257c4) SHA1(569d79a61ff6d35100ba5727069363146df9e0b7) )
ROM_REGION( 0x1000000, "maincpu", 0 )
- ROM_COPY( "user1", 0x000000, 0x000000, 0x1000000 ) // copy flash here
+ ROM_COPY( "flash", 0x000000, 0x000000, 0x1000000 ) // copy flash here
ROM_LOAD( "060511_08-01-18.u49", 0x000000, 0x0200000, CRC(b0c12107) SHA1(b1753757bbdb7d996df563ac6abdc6b46676704b) ) // 27C160
ROM_REGION( 0x4280, "pic", 0 ) // hy04
ROM_LOAD("menghong_hy04", 0x000000, 0x4280, NO_DUMP )
-
- ROM_REGION( 0x1000000, "user2", ROMREGION_ERASEFF ) // Unmapped flash
ROM_END
void crystal_state::init_crysking()
{
- uint16_t *Rom = (uint16_t*) memregion("user1")->base();
+ uint16_t *Rom = (uint16_t*) memregion("flash")->base();
//patch the data feed by the protection
@@ -1811,7 +1834,7 @@ void crystal_state::init_crysking()
void crystal_state::init_evosocc()
{
- uint16_t *Rom = (uint16_t*) memregion("user1")->base();
+ uint16_t *Rom = (uint16_t*) memregion("flash")->base();
Rom += 0x1000000 * 2 / 2;
Rom[WORD_XOR_LE(0x97388E/2)] = 0x90FC; //PUSH R2..R7
@@ -1839,7 +1862,7 @@ also it seems that bit 0x40000000 is the PIC reset.
void crystal_state::init_topbladv()
{
// patches based on analysis of PIC dump
- uint16_t *Rom = (uint16_t*) memregion("user1")->base();
+ uint16_t *Rom = (uint16_t*) memregion("flash")->base();
/*
PIC Protection data:
- RAM ADDR - --PATCH--
@@ -1866,7 +1889,7 @@ void crystal_state::init_topbladv()
void crystal_state::init_officeye()
{
// patches based on analysis of PIC dump
- uint16_t *Rom = (uint16_t*) memregion("user1")->base();
+ uint16_t *Rom = (uint16_t*) memregion("flash")->base();
/*
PIC Protection data:
@@ -1892,7 +1915,7 @@ void crystal_state::init_officeye()
void crystal_state::init_donghaer()
{
- uint16_t *Rom = (uint16_t*)memregion("user1")->base();
+ uint16_t *Rom = (uint16_t*)memregion("flash")->base();
Rom[WORD_XOR_LE(0x037A2 / 2)] = 0x9004; // PUSH %R2
Rom[WORD_XOR_LE(0x037A4 / 2)] = 0x8202; // LD (%SP,0x8),%R2
@@ -1920,10 +1943,10 @@ GAME( 2001, officeye, 0, crystal, officeye, crystal_state, init_officeye
GAME( 2001, donghaer, 0, crystal, crystal, crystal_state, init_donghaer, ROT0, "Danbi", "Donggul Donggul Haerong", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION )
GAME( 2004?,menghong, 0, crzyddz2, crzyddz2, crystal_state, empty_init, ROT0, "Sealy", "Meng Hong Lou", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION )
GAME( 2006, crzyddz2, 0, crzyddz2, crzyddz2, crystal_state, empty_init, ROT0, "Sealy", "Crazy Dou Di Zhu II", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION )
-GAME( 2009, trivrus, 0, trivrus, trivrus, crystal_state, empty_init, ROT0, "AGT", "Trivia R Us (v1.07)", 0 ) // has a CF card instead of flash roms
+GAME( 2009, trivrus, 0, trivrus, trivrus, crystal_state, empty_init, ROT0, "AGT", "Trivia R Us (v1.07)", 0 )
GAME( 200?, crospuzl, 0, crospuzl, crospuzl, crystal_state, empty_init, ROT0, "<unknown>", "Cross Puzzle", MACHINE_NOT_WORKING )
-GAME( 2004, psattack, 0, crystal, crystal, crystal_state, init_psattack, ROT0, "Uniana", "P's Attack", MACHINE_IS_SKELETON )
+GAME( 2004, psattack, 0, crystal, crystal, crystal_state, init_psattack, ROT0, "Uniana", "P's Attack", MACHINE_IS_SKELETON ) // has a CF card instead of flash roms
// looks like the same kind of hw from strings in the ROM, but scrambled / encrypted?
GAME( 200?, ddz, 0, crystal, crystal, crystal_state, empty_init, ROT0, "IGS?", "Dou Di Zhu", MACHINE_IS_SKELETON )
GAME( 200?, crzclass, 0, crystal, crystal, crystal_state, empty_init, ROT0, "TJF", "Zhaoji Fengdou", MACHINE_IS_SKELETON ) // 'Crazy Class'