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-rw-r--r--src/lib/netlist/macro/nlm_ttl74xx_lib.cpp468
1 files changed, 0 insertions, 468 deletions
diff --git a/src/lib/netlist/macro/nlm_ttl74xx_lib.cpp b/src/lib/netlist/macro/nlm_ttl74xx_lib.cpp
index c720cb8f3e2..c96310d7f80 100644
--- a/src/lib/netlist/macro/nlm_ttl74xx_lib.cpp
+++ b/src/lib/netlist/macro/nlm_ttl74xx_lib.cpp
@@ -5,7 +5,6 @@
//- Identifier: TTL_7400_DIP
//- Title: 5400/DM5400/DM7400 Quad 2-Input NAND Gates
-//- Description: This device contains four independent gates each of which performs the logic NAND function.
//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -44,7 +43,6 @@ NETLIST_END()
//- Identifier: TTL_7402_DIP
//- Title: 5402/DM5402/DM7402 Quad 2-Input NOR Gates
-//- Description: This device contains four independent gates each of which performs the logic NOR function.
//- Pinalias: Y1,A1,B1,Y2,A2,B2,GND,A3,B3,Y3,A4,B4,Y4,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -83,7 +81,6 @@ NETLIST_END()
//- Identifier: TTL_7404_DIP
//- Title: 5404/DM5404/DM7404 Hex Inverting Gates
-//- Description: This device contains six independent gates each of which performs the logic INVERT function.
//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -122,8 +119,6 @@ NETLIST_END()
//- Identifier: TTL_7406_DIP
//- Title: DM5406/DM7406 Hex Inverting Buffers with High Voltage Open-Collector Outputs
-//- Description: This device contains six independent buffers each of which performs the logic INVERT function.
-//- The open-collector outputs require external pull-up resistors for proper logical operation.
//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -163,8 +158,6 @@ NETLIST_END()
//- Identifier: TTL_7407_DIP
//- Title: DM5407/DM7407 Hex Buffers with High Voltage Open-Collector Outputs
-//- Description: This device contains six independent gates each of which performs a buffer function.
-//- The open-collector outputs re-quire external pull-up resistors for proper logical operation.
//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -204,7 +197,6 @@ NETLIST_END()
//- Identifier: TTL_7408_DIP
//- Title: 5408/DM5408/DM7408 Quad 2-Input AND Gates
-//- Description: This device contains four independent gates each of which performs the logic AND function.
//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -243,7 +235,6 @@ NETLIST_END()
//- Identifier: TTL_7410_DIP
//- Title: 5410/DM5410/DM7410 Triple 3-Input NAND Gates
-//- Description: This device contains three independent gates each of which performs the logic NAND function.
//- Pinalias: A1,B1,A2,B2,C2,Y2,GND,Y3,A3,B3,C3,Y1,C1,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -281,7 +272,6 @@ NETLIST_END()
//- Identifier: TTL_7411_DIP
//- Title: DM7411 Triple 3-Input AND Gate
-//- Description: This device contains three independent gates with three data inputs each which perform the logic AND function.
//- Pinalias: A1,B1,A2,B2,C2,Y2,GND,Y3,A3,B3,C3,Y1,C1,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -319,9 +309,6 @@ NETLIST_END()
//- Identifier: TTL_7414_DIP
//- Title: DM5414/DM7414 Hex Inverter withSchmitt Trigger Inputs
-//- Description: This device contains six independent gates each of whichperforms the logic INVERT function.
-//- Each input has hysteresis which increases the noise immunity and transforms a slowly changing input
-//- signal to a fast changing, jitter free output.
//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -399,8 +386,6 @@ NETLIST_END()
//- Identifier: TTL_7416_DIP
//- Title: DM5416/DM7416 Hex Inverting Buffers with High Voltage Open-Collector Outputs
-//- Description: This device contains six independent gates each of which performs the logic INVERT function.
-//- The open-collector outputs require external pull-up resistors for proper logical operation.
//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -439,8 +424,6 @@ NETLIST_END()
//- Identifier: TTL_7417_DIP
//- Title: DM5417/DM7417 Hex Buffers withHigh Voltage Open-Collector Output
-//- Description: This device contains six independent gates each of which performs a buffer function.
-//- The open-collector outputs re-quire external pull-up resistors for proper logical operation.
//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -479,7 +462,6 @@ NETLIST_END()
//- Identifier: TTL_7420_DIP
//- Title: 5420/DM5420/DM7420 Dual 4-Input NAND Gates
-//- Description: This device contains two independent gates each of which performs the logic NAND function.
//- Pinalias: A1,B1,NC,C1,D1,Y1,GND,Y2,A2,B2,NC,C2,D2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -518,7 +500,6 @@ NETLIST_END()
//- Identifier: TTL_7421_DIP
//- Title: 54LS21/DM54LS21/DM74LS21 Dual 4-Input AND Gates
-//- Description: This device contains two independent 4-input gates each of which performs the logic AND function.
//- Pinalias: A1,B1,NC,C1,D1,Y1,GND,Y2,A2,B2,NC,C2,D2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -557,8 +538,6 @@ NETLIST_END()
//- Identifier: TTL_7425_DIP
//- Title: 5425/DM7425 Dual 4-Input NOR Gate (with Strobe)
-//- Description: This device contains 2, 4-input gates that perform the logical NOR function.
-//- The output of each NOR gate is gated (strobed) by pin 3 and 11 by positive true logic, i.e., logic "1" equals output on.
//- Pinalias: A1,B1,X1,C1,D1,Y1,GND,Y2,A2,B2,X2,C2,D2
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -600,7 +579,6 @@ NETLIST_END()
//- Identifier: TTL_7427_DIP
//- Title: DM7427 Triple 3-Input NOR Gates
-//- Description: This device contains three independent gates each of which performs the logic NOR function.
//- Pinalias: A1,B1,A2,B2,C2,Y2,GND,Y3,A3,B3,C3,Y1,C1,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -638,7 +616,6 @@ NETLIST_END()
//- Identifier: TTL_7430_DIP
//- Title: 5430/DM5430/DM7430 8-Input NAND Gate
-//- Description: This device contains a single gate which performs the logic NAND function.
//- Pinalias: A,B,C,D,E,F,GND,Y,NC,NC,G,H,NC,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -676,7 +653,6 @@ NETLIST_END()
//- Identifier: TTL_7432_DIP
//- Title: 5432/DM5432/DM7432 Quad 2-Input OR Gates
-//- Description: This device contains four independent gates each of whichperforms the logic OR function.
//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -715,7 +691,6 @@ NETLIST_END()
//- Identifier: TTL_7437_DIP
//- Title: 5437/DM5437/DM7437 Quad 2-Input NAND Buffers
-//- Description: This device contains four independent gates each of whichperforms the logic OR function.
//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -755,8 +730,6 @@ NETLIST_END()
//- Identifier: TTL_7438_DIP
//- Title: DM74LS38 Quad 2-Input NAND Buffer with Open-Collector Outputs
-//- Description: This device contains four independent gates, each of which performs the logic NAND function.
-//- The open-collector outputs require external pull-up resistors for proper logical operation..
//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -795,12 +768,6 @@ NETLIST_END()
//- Identifier: TTL_7442_DIP
//- Title: 5442A/DM5442A/DM7442A BCD to Decimal Decoders
-//- Description: These BCD-to-decimal decoders consist of eight inverters
-//- and ten, four-input NAND gates. The inverters are
-//- connected in pairs to make BCD input data available for
-//- decoding by the NAND gates. Full decoding of input
-//- logic ensures that all outputs remain off for all invalid
-//- (10-15) input conditions.
//- Pinalias: 0,1,2,3,4,5,6,GND,7,8,9,D,C,B,A,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -846,20 +813,6 @@ NETLIST_END()
//- Identifier: TTL_7448_DIP
//- Title: DM5448/DM48LS48/DM7448/DM74LS48 BCD to 7-Segment Decoder
-//- Description: The 48 and LS48 feature active-high outputs for
-//- driving lamp buffers or common-cathode LED's.
-//- These circuits have full ripple-blanking input/output controls
-//- and a lamp test input. Display patterns
-//- for BCD input counts above nine are unique symbols
-//- to authenticate input conditions.
-//- These circuits incorporate automatic
-//- leading and/or trailing-edge, zero-blanking control
-//- (RBI and RBO). Lamp test (LT) of these devices may
-//- be performed at any time when the BI/RBO node is at
-//- a high logic level. They contain
-//- an overriding blanking input (BI) which can be used
-//- to control the lamp intensity (by pulsing), or to inhibit
-//- the outputs.
//- Pinalias: A1,A2,LTQ,BIQ,RBIQ,A3,A0,GND,e,d,c,b,a,g,f,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -909,8 +862,6 @@ NETLIST_END()
//- Identifier: TTL_7450_DIP
//- Title: DM7450 Expandable Dual 2-Wide 2-Input AND-OR-INVERT Gate
-//- Description: This device contains two independent combinations of gates, each of which perform the logic AND-OR-INVERT function.
-//- One set of gates has an expander node.
//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -949,15 +900,6 @@ NETLIST_END()
//- Identifier: TTL_7473_DIP
//- Title: 5473/DM5473/DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
-//- Description: This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs.
-//- The J and K data is processed by the flip-flops after a complete clock pulse.
-//- While the clock is low the slave is isolated from the master.
-//- On the positive transition of the clock, the data from the J and K inputs is transferred to teh master.
-//- While the clock is high the J and K inputs are disabled.
-//- On the negative transition of the clock, the data from the master is transferred to the slave.
-//- The logic states of the J and K inputs must not be allowed to change while the clock is high.
-//- Data transfers to the outputs on the falling edge of the clock pulse.
-//- A low logic level on the clear input will reset the outputs regardless of the logic states of the other inputs.
//- Pinalias: CLK1,CLR1,K1,VCC,CLK2,CLR2,J2,QQ2,Q2,K2,GND,Q1,QQ1,J1
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -995,11 +937,6 @@ NETLIST_END()
//- Identifier: TTL_7473A_DIP
//- Title: DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
-//- Description: This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
-//- The J and K data is processed by the flip-flops on the falling edge of the clock pulse.
-//- The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse.
-//- The data on the J and K inputs is allowed to change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated.
-//- A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs.
//- Pinalias: CLK1,CLR1,K1,VCC,CLK2,CLR2,J2,QQ2,Q2,K2,GND,Q1,QQ1,J1
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semicouductor datasheet
@@ -1038,11 +975,6 @@ NETLIST_END()
//- Identifier: TTL_7474_DIP
//- Title: 5474/DM5474/DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
-//- Description: This device contains two independent positive-edge-triggered D flip-flops with complementary outputs.
-//- The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse.
-//- The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock.
-//- The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated.
-//- A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
//- Pinalias: CLR1,D1,CLK1,PR1,Q1,QQ1,GND,QQ2,Q2,PR2,CLK2,D2,CLR2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1081,21 +1013,6 @@ NETLIST_END()
//- Identifier: TTL_7475_DIP
//- Title: DM5475/DM7475/DM7475A/DM74LS75 4-bit D Latch
-//- Description: These latches are ideally suited for use as temporary
-//- storage for binary information between processing units
-//- and input/output or indicator units. Information present
-//- at a data (D) input is transferred to the Q output when
-//- the enable (G) is high, and the Q output will follow
-//- the data input as long as the enable remains high. When
-//- the enable goes low, the information (that was present
-//- at the data input at the time the transition occurred) is
-//- retained at the Q output until the enable is permitted
-//- to go high.
-//-
-//- The DM5475/DM7475, DM54L75A/DM74L75A, and
-//- DM54LS75/DM74LS75 feature complementary Q and
-//- QQ outputs from a 4-bit latch, and are available in 16-pin
-//- packages.
//- Pinalias: QQ1,D1,D2,E34,VCC,D3,D4,QQ4,Q4,Q3,QQ3,GND,E12,QQ2,Q2,Q1
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1137,16 +1054,6 @@ NETLIST_END()
//- Identifier: TTL_7477_DIP
//- Title: DM74LS77 4-bit D Latch
-//- Description: These latches are ideally suited for use as temporary
-//- storage for binary information between processing units
-//- and input/output or indicator units. Information present
-//- at a data (D) input is transferred to the Q output when
-//- the enable (G) is high, and the Q output will follow
-//- the data input as long as the enable remains high. When
-//- the enable goes low, the information (that was present
-//- at the data input at the time the transition occurred) is
-//- retained at the Q output until the enable is permitted
-//- to go high.
//- Pinalias: D1,D2,E34,VCC,D3,D4,NC,Q4,Q3,NC,GND,E12,Q2,Q1
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1189,18 +1096,6 @@ NETLIST_END()
//- Identifier: TTL_7483_DIP
//- Title: DM5483/DM7483/DM74LS83A 4-bit Binary Adders With Fast Carry
-//- Description: These full adders perform the addition of two 4-bit
-//- binary numbers. The sum (S) outputs are provided for
-//- each bit and the resultant carry (C4) is obtained from
-//- the fourth bit. These adders feature full internal look
-//- ahead across all four bits. This provides the system
-//- designer with partial look-ahead performance at the
-//- economy and reduced package count of a ripple-carry
-//- implementation.
-//-
-//- The adder logic, including the carry, is implemented in
-//- its true form meaning that the end-around carry can be
-//- accomplished without the need for logic or level inversion.
//- Pinalias: A4,S3,A3,B3,VCC,S2,B2,A2,S1,A1,B1,GND,C0,C4,S4,B4
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1225,22 +1120,6 @@ NETLIST_END()
//- Identifier: TTL_7485_DIP
//- Title: DM5485/DM7485/DM74L85/DM74LS85 4-Bit Magnitude Comparators
-//- Description: These four-bit magnitude comparators perform comparison
-//- of straight binary or BCD codes. Three
-//- fully-decoded decisions about two, 4-bit words (A, B)
-//- are made and are externally available at three outputs.
-//- These devices are fully expandable to any number of
-//- bits without external gates. Words of greater length may
-//- be compared by connecting comparators in cascade. The
-//- A > B, A < B, and A = B outputs of a stage handling
-//- less-significant bits are connected to the corresponding
-//- inputs of the next stage handling more-significant bits.
-//- The stage handling the least-significant bits must have a
-//- high-level voltage applied to the A = B input and in
-//- addition for the L85, low-level voltages applied to the
-//- A> B and A < B inputs. The cascading paths of the 85,
-//- and LS85 are implemented with only a two-gate-Ievel
-//- delay to reduce overall comparison times for long words.
//- Pinalias: B3,LTIN,EQIN,GTIN,GTOUT,EQOUT,LTOUT,GND,B0,A0,B1,A1,A2,B2,A3,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1265,7 +1144,6 @@ NETLIST_END()
//- Identifier: TTL_7486_DIP
//- Title: 5486/DM5486/DM7486 Quad 2-Input Exclusive-OR Gates
-//- Description: This device contains four independent gates each of which performs the logic exclusive-OR function.
//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1304,22 +1182,6 @@ NETLIST_END()
//- Identifier: TTL_7490_DIP
//- Title: DM5490/DM7490A Decade Counter
-//- Description: These monolithic counters contain four
-//- master-slave flip-flops and additional gating to provide
-//- a divide-by-two counter and a three-stage binary counter
-//- for which the count cycle length is divide-by-five.
-//-
-//- These counters have a gated zero reset and
-//- also have gated set-to-nine inputs
-//- for use in BCD nine's complement applications.
-//-
-//- To use their maximum count length (decade), the B input is connected
-//- to the QA output. The input count pulses are applied to
-//- input A and the outputs are as described in the appropriate
-//- truth table. A symmetrical divide-by-ten count can be
-//- obtained from the by connecting the QD output to
-//- the A input and applying the input count to the B input
-//- which gives a divide-by-ten square wave at output QA.
//- Pinalias: B,R01,R02,NC,VCC,R91,R92,QC,QB,GND,QD,QA,NC,A
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1373,18 +1235,6 @@ NETLIST_END()
//- Identifier: TTL_7492_DIP
//- Title: SN5492A, SN54LS92, SN7492A, SN74LS92 Divide-By-Twelve Counter
-//- Description: These monolithic counters contains four
-//- master-slave flip-flops and additional gating to provide
-//- a divide-by-two counter and a three-stage binary counter
-//- for which the count cycle length is divide-by-six.
-//-
-//- These counters have a gated zero reset.
-//-
-//- To use their maximum count length (divide-by-
-//- twelve), the B input is connected
-//- to the QA output. The input count pulses are applied to
-//- input A and the outputs are as described in the appropriate
-//- truth table.
//- Pinalias: CKB,NC,NC,NC,VCC,R01,R02,QD,QC,GND,QB,QA,NC,CLKA
//- Package: DIP
//- NamingConvention: Naming conventions follow Texas Instruments datasheet
@@ -1436,25 +1286,6 @@ NETLIST_END()
//- Identifier: TTL_7493_DIP
//- Title: 7493 Binary Counters
-//- Description:
-//- Each of these monolithic counters contains four master-slave
-//- flip-flops and additional gating to provide a divide-by-two
-//- counter and a three-stage binary counter for which the
-//- count cycle length is divide-by-five for the 90A and divide-by-eight
-//- for the 93A.
-//-
-//- All of these counters have a gated zero reset and the 90A
-//- also has gated set-to-nine inputs for use in BCD nine’s complement
-//- applications.
-//-
-//- To use their maximum count length (decade or four-bit binary),
-//- the B input is connected to the Q A output. The input count pulses
-//- are applied to input A and the outputs are as described in the
-//- appropriate truth table. A symmetrical divide-by-ten count can be
-//- obtained from the 90A counters by connecting the Q D output to the
-//- A input and applying the input count to the B input which gives
-//- a divide-by-ten square wave at output Q A.
-//-
//- Pinalias: B,R01,R02,NC,VCC,NC,NC,QC,QB,GND,QD,QA,NC,A
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1515,11 +1346,6 @@ NETLIST_END()
//- Identifier: TTL_7497_DIP
//- Title: 5497/DM7497 Synchronous Modulo-64 Bit Rate Multiplier
-//- Description: The ’97 contains a synchronous 6-stage binary counter and six decoding gates that serve to gate the clock through to the output at a sub-multiple of the input frequency.
-//- The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (S0–S5) inputs.
-//- Both true and complement outputs are available, along with an enable input for each.
-//- A Count Enable input and a Terminal Count output are provided for cascading two or more packages.
-//- An asynchronous Master Reset input prevents counting and resets the counter.
//- Pinalias: S1,S4,S5,S0,ZQ,Y,TCQ,GND,CP,EZQ,CEQ,EY,MR,S2,S3,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1544,10 +1370,6 @@ NETLIST_END()
//- Identifier: TTL_74107_DIP
//- Title: SN54107, SN74107 Dual J-K Flip-Flops With Clear
-//- Description: The '107 contains two independent J-K flip-flops with individual J-K, clock, and direct clear inputs.
-//- The '107 is a positive pulse-triggered flip-flop.
-//- The J-K input data is loaded into the master while the clock is high and transferred to teh slave and the outputs on the high-to-low clock transition.
-//- For these devices the J and K inputs must be stable while the clock is high.
//- Pinalias: 1J,1QQ,1Q,1K,2Q,2QQ,GND,2J,2CLK,2CLRQ,2K,1CLK,1CLRQ,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Texas Instruments datasheet
@@ -1585,11 +1407,6 @@ NETLIST_END()
//- Identifier: TTL_74107A_DIP
//- Title: DM54LS107A/DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops withClear and Complementary Outputs
-//- Description: This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
-//- The J and K data is processed by the flip-flops on the falling edge of the clock pulse.
-//- The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse.
-//- The data on the J and K inputs may change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated.
-//- A low logic level on the clear input will reset the outputs regardless of the logic levels of the other inputs.
//- Pinalias: J1,QQ1,Q1,K1,Q2,QQ2,GND,J2,CLK2,CLRQ2,K2,CLK1,CLRQ1,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1628,11 +1445,6 @@ NETLIST_END()
//- Identifier: TTL_74113_DIP
//- Title: DM54S113/DM74S113 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs
-//- Description: This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
-//- The J and K data is processed by the flip-flops on the falling edge of the clock pulse.
-//- The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse.
-//- Data on the J and K inputs may be changed while the clock is high or low without affecting the outputs as long as setup and hold times are not violated.
-//- A low logic level on the preset input will set the outputs regardless of the logic levels of the other inputs.
//- Pinalias: CLK1,K1,J1,PRQ1,Q1,QQ1,GND,QQ2,Q2,PRQ2,J2,K2,CLK2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Texas Instruments datasheet
@@ -1671,11 +1483,6 @@ NETLIST_END()
//- Identifier: TTL_74113A_DIP
//- Title: DM54S113/DM74S113 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs
-//- Description: This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
-//- The J and K data is processed by the flip-flops on the falling edge of the clock pulse.
-//- The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse.
-//- Data on the J and K inputs may be changed while the clock is high or low without affecting the outputs as long as setup and hold times are not violated.
-//- A low logic level on the preset input will set the outputs regardless of the logic levels of the other inputs.
//- Pinalias: CLK1,K1,J1,PRQ1,Q1,QQ1,GND,QQ2,Q2,PRQ2,J2,K2,CLK2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Texas Instruments datasheet
@@ -1714,18 +1521,6 @@ NETLIST_END()
//- Identifier: TTL_74121_DIP
//- Title: DM74121 One-Shot with Clear and Complementary Outputs
-//- Description: The DM74121 is a monostable multivibrator featuring both
-//- positive and negative edge triggering with complementary
-//- outputs. An internal 2kΩ timing resistor is provided for
-//- design convenience minimizing component count and layout problems. this device can be used with a single external capacitor. Inputs (A) are active-LOW trigger transition
-//- inputs and input (B) is and active-HIGH transition Schmitttrigger input that allows jitter-free triggering from inputs with
-//- transition rates as slow as 1 volt/second. A high immunity
-//- to VCC noise of typically 1.5V is also provided by internal
-//- circuitry at the input stage.
-//- To obtain optimum and trouble free operation please read
-//- operating rules and one-shot application notes carefully
-//- and observe recommendations.
-//-
//- Pinalias: QQ,NC,A1,A2,B,Q,GND,NC,RINT,C,RC,NC,NC,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
@@ -1762,20 +1557,6 @@ NETLIST_END()
//- Identifier: TTL_74123_DIP
//- Title: DM74123 Dual Retriggerable One-Shot with Clear and Complementary Outputs
-//- Description: The DM74123 is a dual retriggerable monostable multivibrator
-//- capable of generating output pulses from a few
-//- nano-seconds to extremely long duration up to 100% duty
-//- cycle. Each device has three inputs permitting the choice of
-//- either leading-edge or trailing edge triggering. Pin (A) is an
-//- active-LOW transition trigger input and pin (B) is an activeHIGH transition trigger input. A LOW at the clear (CLR)
-//- input terminates the output pulse: which also inhibits triggering. An internal connection from CLR to the input gate
-//- makes it possible to trigger the circuit by a positive-going
-//- signal on CLR as shown in the Truth Table.
-//-
-//- To obtain the best and trouble free operation from this
-//- device please read the Operating Rules as well as the
-//- One–Shot Application Notes carefully and observe recommendations.
-//-
//- Pinalias: A1,B1,CLRQ1,QQ1,Q2,C2,RC2,GND,A2,B2,CLRQ2,QQ2,Q1,C1,RC1,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
@@ -1809,16 +1590,6 @@ NETLIST_END()
//- Identifier: TTL_74125_DIP
//- Title: SN74125 QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
-//- Description: These bus buffers feature three-state outputs
-//- that, when enabled, have the low impedance characteristics of a
-//- TTL output with additional drive capability at high logic levels
-//- to permit driving heavily loaded bus lines without external
-//- pullup resistors. When disabled, both output transistors are turned
-//- off, presenting a high-impedance state to the bus so the output will
-//- act neither as a significant load nor as a driver. The ’125 and
-//- ’LS125A devices’ outputs are disabled when G is high.
-//- The ’126 and ’LS126A devices’ outputs are disabled when G is low
-//-
//- Pinalias: 1GQ,1A,1Y,2GQ,2A,2Y,GND,3Y,3A,3GQ,4Y,4A,4GQ,VCC
//- Package: DIP
//- Param: FORCE_TRISTATE_LOGIC
@@ -1868,12 +1639,6 @@ NETLIST_END()
//- Identifier: TTL_74126_DIP
//- Title: DM74LS126A Quad 3-STATE Buffer
-//- Description: This device contains four independent gates each of which performs a non-inverting buffer function.
-//- The outputs have the 3-STATE feature.
-//- When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of buslines without external resistors.
-//- When disabled, both the output transistors are turned OFF presenting a high-impedance state to the bus line.
-//- Thus the output will act neither as a significant load nor as a driver.
-//- To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.
//- Pinalias: C1,A1,Y1,C2,A2,Y2,GND,Y3,A3,C3,Y4,A4,C4,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1917,14 +1682,6 @@ NETLIST_END()
//- Identifier: TTL_74139_DIP
//- Title: 54LS139/DM54LS139/DM74LS139 Decoders/Demultiplexers
-//- Description: These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times.
-//- In high-performance memory systems these decoders can be used to minimize the effects of system decoding.
-//- When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory.
-//- This means that the effective system delay introduced by the decoder is negligible.
-//- The LS139 comprises two separate two-line-to-four-line decoders in a single package.
-//- The active-low enable input can be used as a data line in demultiplexing applications.
-//- All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit.
-// All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.
//- Pinalias: G1,A1,B1,1Y0,1Y1,1Y2,1Y3,GND,2Y3,2Y2,2Y1,2Y0,B2,A2,G2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -1963,8 +1720,6 @@ NETLIST_END()
//- Identifier: TTL_74153_DIP
//- Title: 54153/DM54153/DM74153 Dual 4-Line to 1-LineData Selectors/Multiplexers
-//- Description: Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates.
-//- Separate strobe inputs are provided for each of the two four-line sections.
//- Pinalias: G1,B,1C3,1C2,1C1,1C0,Y1,GND,Y2,2C0,2C1,2C2,2C3,A,G2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2010,12 +1765,6 @@ NETLIST_END()
//- Identifier: TTL_74155_DIP
//- Title: 54LS155/DM54LS155/DM74LS155 Dual 2-Line to 4-Line Decoders/Demultiplexers
-//- Description: These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package.
-//- When both sections are enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section.
-//- The individual strobes permit activating or inhibiting each of the 4-bit sections as desired.
-//- Data applied to input C1 is inverted at its outputs anddata applied at C2 is true through its outputs.
-//- The inverter following the C1 data input permits use as a 3-to-8-line decoder, or 1-to-8-line demultiplexer, without external gating.
-//- Input clamping diodes are provided on these circuits to minimize transmission-line effects and simplify system design.
//- Pinalias: C1,G1,B,1Y3,1Y2,1Y1,1Y0,GND,2Y0,2Y1,2Y2,2Y3,A,G2,C2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2074,12 +1823,6 @@ NETLIST_END()
//- Identifier: TTL_74156_DIP
//- Title: 54LS156/DM54LS156/DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers with Open-Collector Outputs
-//- Description: These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package.
-//- When both sections are enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section.
-//- The individual strobes permit activating or inhibiting each of the 4-bit sections as desired.
-//- Data applied to input C1 is inverted at its outputs anddata applied at C2 is true through its outputs.
-//- The inverter following the C1 data input permits use as a 3-to-8-line decoder, or 1-to-8-line demultiplexer, without external gating.
-//- Input clamping diodes are provided on these circuits to minimize transmission-line effects and simplify system design.
//- Pinalias: C1,G1,B,1Y3,1Y2,1Y1,1Y0,GND,2Y0,2Y1,2Y2,2Y3,A,G2,C2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2138,9 +1881,6 @@ NETLIST_END()
//- Identifier: TTL_74157_DIP
//- Title: 54157/DM54157/DM74157 Quad 2-Line to 1-Line Data Selectors/Multiplexers
-//- Description: These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four output gates.
-//- A separate strobe input is provided.
-//- A 4-bit word is selected from one of two sources and is routed to the four outputs.
//- Pinalias: S,A1,B1,Y1,A2,B2,Y2,GND,Y3,B3,A3,Y4,B4,A4,G,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2184,21 +1924,6 @@ NETLIST_END()
//- Identifier: TTL_74161_DIP
//- Title: DM54161/DM74161 Synchronous 4-Bit Counter
-//- Description: These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs.
-//- The 161 is a 4-bit binary counter.
-//- The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation.
-//- Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change co-incident with each other when so instructed by the count-enable inputs and internal gating.
-//- This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters.
-//- A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.
-//- These counters are fully programmable; that is, the outputs may be preset to either level.
-//- As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input.
-//- The clear function for the 161 is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs low, regardless of the levels of clock, load, or enable inputs.
-//- The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating.
-//- Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output.
-//- Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output.
-//- The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output.
-//- This high-level overflow ripple carry pulse can be used to enable successive cascaded stages.
-//- High-to-low-level transitions at the enable P or T inputs of the 161 may occur, regardless of the logic level on the clock.
//- Pinalias: CLRQ,CLK,A,B,C,D,ENP,GND,LOADQ,ENT,QD,QC,QB,QA,RC,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2223,24 +1948,6 @@ NETLIST_END()
//- Identifier: TTL_74163_DIP
//- Title: DM74163 Synchronous 4-Bit Counter
-//- Description: These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs.
-//- The 163 is a 4-bit binary counter.
-//- The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation.
-//- Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change co-incident with each other when so instructed by the count-enable inputs and internal gating.
-//- This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters.
-//- A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.
-//- These counters are fully programmable; that is, the outputs may be preset to either level.
-//- As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input.
-//- The clear function for the 163 is synchronous; and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs.
-//- This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate.
-//- The gate output is connected to the clear input to synchronously clear the counter to all low outputs.
-//- Low-to-high transitions at the clear input of the 163 are also permissible, regardless of the logic levels on the clock,enable, or load inputs.
-//- The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating.
-//- Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output.
-//- Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output.
-//- The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output.
-//- This high-level overflow ripple carry pulse can be used to enable successive cascaded stages.
-//- High-to-low-level transitions at the enable P or T inputs of the 163 may occur, regardless of the logic level on the clock.
//- Pinalias: CLRQ,CLK,A,B,C,D,ENP,GND,LOADQ,ENT,QD,QC,QB,QA,RC,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2265,12 +1972,6 @@ NETLIST_END()
//- Identifier: TTL_74164_DIP
//- Title: DM74164 8-Bit Serial In/Parallel Out Shift Registers
-//- Description: These 8-bit shift registers feature gated serial inputs and an asynchronous clear.
-//- A LOW logic level at either serial input inhibits entry of the new data, and resets the first flip-flop to the LOW level at the next clock pulse, thus providing complete control over incoming data.
-//- A HIGH logic level on either input enables the other input, which will then determine the state of the first flip-flop.
-//- Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered.
-//- Clocking occurs on the LOW-to-HIGH level transition of the clock input.
-//- All inputs are diode-clamped to minimize transmission-line effects
//- Pinalias: A,B,QA,QB,QC,QD,GND,CLOCK,CLEAR,QE,QF,QG,QH,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
@@ -2304,10 +2005,6 @@ NETLIST_END()
//- Identifier: TTL_74165_DIP
//- Title: 54165/DM74165 8-Bit Parallel-to-Serial Converter
-//- Description: The ’165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage.
-//- Parallel inputting occurs asynchronously when the Parallel Load (PL) input is LOW.
-//- With PL HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input.
-//- The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable.
//- Pinalias: PLQ,CP1,P4,P5,P6,P7,QQ7,GND,Q7,DS,P0,P1,P2,P3,CP2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2342,17 +2039,6 @@ NETLIST_END()
//- Identifier: TTL_74166_DIP
//- Title: DM74LS166 8-Bit Parallel-In/Serial-Out Shift Registers
-//- Description: These parallel-in or serial-in, serial-out shift registers feature gated clock inputs and an overriding clear input.
-//- All inputs are buffered to lower the drive requirements to one normalized load, and input clamping diodes minimize switching transients to simplify system design.
-//- The load mode is established by the shift/load input.
-//- When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse.
-//- When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse.
-//- During parallel loading, serial data flow is inhibited.
-//- Clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function.
-//- Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input.
-//- This allows the system clock to be free running, and the register can be stopped on command with the other clock input.
-//- The clock-inhibit input should be changed to the high level only while the clock input is high.
-//- A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
//- Pinalias: SER,A,B,C,D,CLKINH,CLK,GND,CLRQ,E,F,G,QH,H,SH/LDQ,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2388,11 +2074,6 @@ NETLIST_END()
//- Identifier: TTL_74174_DIP
//- Title: DM74174 Hex/Quad D-Type Flip-Flop with Clear
-//- Description: These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic.
-//- All have a direct clear input.
-//- Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.
-//- Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.
-//- When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.
//- Pinalias: CLRQ,Q1,D1,D2,Q2,D3,Q3,GND,CLK,Q4,D4,Q5,D5,Q6,D6,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
@@ -2499,7 +2180,6 @@ NETLIST_END()
//- Identifier: TTL_74260_DIP
//- Title: DM54LS260/DM74LS260 Dual 5-Input NOR Gate
-//- Description: This device contains two individual five input gates, each of which perform the logic NOR function.
//- Pinalias: A1,B1,C1,A2,Q1,Q2,GND,B2,C2,D2,E2,D1,E1,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2538,15 +2218,6 @@ NETLIST_END()
//- Identifier: TTL_74279_DIP
//- Title: 54279/DM74279 Quad Set-Reset Latch
-//- Description: These latches are ideaily suited ·for use as temporary
-//- storage of bfnary information between processing units
-//- and I/O units. When either one of the data inputs is at
-//- a low logic level, the output will follow the level of the
-//- R input. When both data inputs are high, the output will
-//- remain latched in its previous state. When both inputs
-//- are low, the output will .go high. However, this high
-//- level may not persist when either one of the data inputs
-//- returns to the high state.
//- Pinalias: 1RQ,1S1Q,1S2Q,1Q,2RQ,2SQ,2Q,GND,3Q,3RQ,3S1Q,3S2Q,4Q,4RQ,4SQ,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2613,13 +2284,6 @@ NETLIST_END()
//- Identifier: TTL_74290_DIP
//- Title: SN54290/SN74290, SN54LS290/SN74LS290 Decade Counter
-//- Description: The SN54290/SN74290 and SN54LS290/SN74LS290 counters are electrically and functionally identical to the NS5490A/SN7490A and SN54LS90/SN74LS90, respectively.
-//- Only the arrangement of the terminals has been changed for the '290 and 'LS290.
-//- Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five.
-//- All of these counters have a gated zero reset and also have gated set-to-nine inputs for use in BCD nine's complement applications.
-//- To use the maximum count length (decade) of these counters, the B input is connected to the QA output.
-//- The input count pulses are applied to input A and the outputs are as described in the appropriate function table.
-//- A symmetrical divide-by-ten count can be obtained by connecting the QD output to the A input and applying the input count ot the B input which gives a divide-by-ten square wave at output QA.
//- Pinalias: R91,NC,R92,QC,QB,NC,GND,QD,QA,CKA,CKB,R01,R02,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Texas Instruments datasheet
@@ -2673,12 +2337,6 @@ NETLIST_END()
//- Identifier: TTL_74293_DIP
//- Title: SN54293/SN74293, SN54LS293/SN74LS293 Binary Counters
-//- Description: The SN54293/SN74293 and SN54LS293/SN74LS293 counters are electrically and functionally identical to the SN5493A/SN7493A and SN54LS93/SN74LS93, respectively.
-//- Only the arrangement of the terminals has been changed for the '293 and 'LS293.
-//- Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-eight.
-//- All of these counters have a gated zero reset.
-//- To use the maximum count length (decade or four-bit binary) of these counters, the B input is connected to the QA output.
-//- The input count pulses are applied to input A and the outputs are as described in the appropriate function table.
//- Pinalias: B,R01,R02,NC,VCC,NC,NC,QC,QB,GND,QD,QA,NC,A
//- Package: DIP
//- NamingConvention: Naming conventions follow Texas Instruments datasheet
@@ -2738,9 +2396,6 @@ NETLIST_END()
//- Identifier: TTL_74377_DIP
//- Title: DM54LS377/DM74LS377 Octal D Flip-Flop with Common Enable and Clock
-//- Description: The ’LS377 is an 8-bit register built using advanced low power Schottky technology.
-//- This register consists of eight D-type flip-flops with a buffered common clock and a buffered common input enable.
-//- The device is packaged in the space-saving (0.3 inch row spacing) 20-pin package.
//- Pinalias: EQ,Q0,D0,D1,Q1,Q2,D2,D3,Q3,GND,CP,Q4,D4,D5,Q5,Q6,D6,D7,Q7,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2796,8 +2451,6 @@ NETLIST_END()
//- Identifier: TTL_74378_DIP
//- Title: DM54LS378/DM74LS378 Parallel D Register with Enable
-//- Description: The ’LS378 is a 6-bit register with a buffered common enable.
-//- This device is similar to the ’LS174, but with common Enable rather than common Master Reset.
//- Pinalias: EQ,Q0,D0,D1,Q1,D2,Q2,GND,CP,Q3,D3,Q4,D4,D5,Q6,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2840,8 +2493,6 @@ NETLIST_END()
//- Identifier: TTL_74379_DIP
//- Title: 54LS379/DM74LS379 Quad Parallel Register with Enable
-//- Description: The LS379 is a 4-bit register with buffered common Enable.
-//- This device is similar to the LS175 but features the common Enable rather than common Master Reset.
//- Pinalias: EEQ,Q0,QQ0,D0,QQ1,Q1,GND,CP,Q2,QQ2,D2,D3,QQ3,Q3,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2882,10 +2533,6 @@ NETLIST_END()
//- Identifier: TTL_74393_DIP
//- Title: Dual 4-Bit Binary Counter
-//- Description: DM74LS393 Each of these monolithic circuits contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters in a single package.
-//- The ’LS393 comprises two independent four-bit binary counters each having a clear and a clock input.
-//- N-bit binary counters can be implemented with each package providing the capability of divide-by-256.
-//- The LS393 has parallel outputs from each counter stage so that any submultiple of the input count freqency is available for system-timing signals.
//- Pinalias: 1A,1CLR,1QA,1QB,1QC,1QD,GND,2QD,2QC,2QB,2QA,2CLR,2A,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -2913,9 +2560,6 @@ NETLIST_END()
//- Identifier: SN74LS629_DIP
//- Title: SN74LS629 VOLTAGE-CONTROLLED OSCILLATORS
-//- Description: Please add a detailed description
-//- FIXME: Missing description
-//-
//- Pinalias: 2FC,1FC,1RNG,1CX1,1CX2,1ENQ,1Y,OSC_GND,GND,2Y,2ENQ,2CX2,2CX1,2RNG,OSC_VCC,VCC
//- Package: DIP
//- Param: A.CAP
@@ -2960,47 +2604,6 @@ NETLIST_END()
//- Identifier: TTL_9310_DIP
//- Title: DM9310/DM8310 Synchronous 4-Bit Decade Counter
-//- Description: These synchronous, presettable counters feature an
-//- internal carry look-ahead for application in high-speed
-//- counting designs. The DM9310/DM8310 are decade
-//- counters. The carry output is decoded by means of a
-//- NOR gate, thus preventing spikes during the normal
-//- counting mode of operation. Synchronous operation
-//- is provided by having all flip-flops clocked simultaneously
-//- so that the outputs change coincident with each
-//- other when so instructed by the count-enable inputs
-//- and internal gating. This mode of operation eliminates
-//- the output counting spikes which are normally
-//- associated with asynchronous (ripple clock) counters.
-//- A buffered clock input triggers the four flip-flops on
-//- the rising (positive-going) edge of the clock input
-//- waveform.
-//-
-//- These counters are fully programmable; that is, the
-//- outputs may be preset to either level. As presetting is
-//- synchronous, setting up a low level at the load input
-//- disables the counter and causes the outputs to agree
-//- with the setup data after the next clock pulse regardless
-//- of the levels of the enable input. Low-to-high transitions
-//- at the· load input are perfectly acceptable regardless of
-//- the logic levels on the clock or enable inputs. The clear
-//- function is asynchronous and a low level at the clear
-//- input sets all four of the flip-flop outputs low regardless
-//- of the levels of clock, load, or enable inputs.
-//-
-//- The carry look-ahead circuitry provides for cascading
-//- counters for n-bit synchronous applications without
-//- additional gating. Instrumental in accomplishing this
-//- function are two count-enable inputs and a ripple carry
-//- output. Both count-enable inputs (P and T) must be
-//- high to count, and input T is fed-forward to enable the
-//- ripple carry output. The ripple carry output thus
-//- enabled will produce a high-level output pulse with a
-//- duration approximately equal to the high-level portion
-//- of the QA output. This high-level overflow ripply carry
-//- pulse can be used to enable successive cascaded stages.
-//- High-to-Low level transitions at the enable P or T inputs
-//- may occur regardless of the logic level in the clock.
//- Pinalias: CLEARQ,CLOCK,A,B,C,D,ENABLEP,GND,LOADQ,ENABLET,QD,QC,QB,QA,RC,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -3025,14 +2628,6 @@ NETLIST_END()
//- Identifier: TTL_9312_DIP
//- Title: DM9312/DM8312 One of Eight Line Data Selectors/Multiplexers
-//- Description: These data selectors/multiplexers contain inverter/
-//- drivers to supply full complementary, on-chip, binary
-//- decoded data selection to the AND-OR-INVERT gates.
-//-
-//- The DM9312/8312 is a single 8-bit multiplexer with
-//- complementary outputs and a strobe control. When the
-//- strobe is low, the function is enabled. When a high logic
-//- level is applied to the strobe, the outputs are latched.
//- Pinalias: D0,D1,D2,D3,D4,D5,D6,GND,D7,G,A,B,C,YQ,Y,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -3088,47 +2683,6 @@ NETLIST_END()
//- Identifier: TTL_9316_DIP
//- Title: DM9316/DM8316 Synchronous 4-Bit Counters
-//- Description: These synchronous, presettable counters feature an
-//- internal carry look-ahead for application in high-speed
-//- counting designs. The DM9316/DM8316 are 4-bit binary
-//- counters. The carry output is decoded by means of a
-//- NOR gate, thus preventing spikes during the normal
-//- counting mode of operation. Synchronous operation
-//- is provided by having all flip-flops clocked simultaneously
-//- so that the outputs change coincident with each
-//- other when so instructed by the count-enable inputs
-//- and internal gating. This mode of operation eliminates
-//- the output counting spikes which are normally
-//- associated with asynchronous (ripple clock) counters.
-//- A buffered clock input triggers the four flip-flops on
-//- the rising (positive-going) edge of the clock input
-//- waveform.
-//-
-//- These counters are fully programmable; that is, the
-//- outputs may be preset to either level. As presetting is
-//- synchronous, setting up a low level at the load input
-//- disables the counter and causes the outputs to agree
-//- with the setup data after the next clock pulse regardless
-//- of the levels of the enable input. Low-to-high transitions
-//- at the· load input are perfectly acceptable regardless of
-//- the logic levels on the clock or enable inputs. The clear
-//- function is asynchronous and a low level at the clear
-//- input sets all four of the flip-flop outputs low regardless
-//- of the levels of clock, load, or enable inputs.
-//-
-//- The carry look-ahead circuitry provides for cascading
-//- counters for n-bit synchronous applications without
-//- additional gating. Instrumental in accomplishing this
-//- function are two count-enable inputs and a ripple carry
-//- output. Both count-enable inputs (P and T) must be
-//- high to count, and input T is fed-forward to enable the
-//- ripple carry output. The ripple carry output thus
-//- enabled will produce a high-level output pulse with a
-//- duration approximately equal to the high-level portion
-//- of the QA output. This high-level overflow ripply carry
-//- pulse can be used to enable successive cascaded stages.
-//- High-to-Low level transitions at the enable P or T inputs
-//- may occur regardless of the logic level in the clock.
//- Pinalias: CLEARQ,CLOCK,A,B,C,D,ENABLEP,GND,LOADQ,ENABLET,QD,QC,QB,QA,RC,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -3153,12 +2707,6 @@ NETLIST_END()
//- Identifier: TTL_9322_DIP
//- Title: DM9322/DM8322 Quad 2-Line to 1-Line Data Selectors/Multiplexers
-//- Description: These data selectors/multiplexers contain inverters and
-//- drivers to supply full on-chip data selection to the four
-//- output gates. A separate strobe input is provided. A
-//- 4-bit word is selected from one of two sources and is
-//- routed to the four outputs. True data is presented
-//- at the outputs.
//- Pinalias: SELECT,A1,B1,Y1,A2,B2,Y2,GND,Y3,B3,A3,Y4,B4,A4,STROBE,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow National Semiconductor datasheet
@@ -3227,22 +2775,6 @@ NETLIST_END()
//- Identifier: TTL_9602_DIP
//- Title: DM9602/DM6802 Dual Retriggerable, Resettable One Shots
-//- Description: These dual resettable, retriggerable one shots have two
-//- inputs per function; one which is active high, and one
-//- which is active low. This allows the designer to employ
-//- either leading-edge or trailing-edge triggering, which is
-//- independent of input transition times. When input con·
-//- ditions for triggering are met, a new cycle starts and the
-//- external capacitor is allowed to rapidly discharge and
-//- then charge again. The retriggerable feature permits
-//- output pulse widths to be extended. In fact a continuous
-//- true output can be maintained by having an input cycle
-//- time which is shorter than the output cycle time. The
-//- output pulse may then be terminated at any time by
-//- applying a low logic level to the RESET pin. Retriggering
-//- may be inhibited by either connecting the Q output to
-//- an active high input, or the Q output to an active
-//- low input.
//- Pinalias: C1,RC1,CLRQ1,B1,A1,Q1,QQ1,GND,QQ2,Q2,A2,B2,CLRQ2,RC2,C2,VCC
//- Package: DIP
//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet