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Diffstat (limited to 'src/lib/netlist/devices/nld_7497.h')
-rw-r--r--src/lib/netlist/devices/nld_7497.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/lib/netlist/devices/nld_7497.h b/src/lib/netlist/devices/nld_7497.h
index 6db9a4d3538..70ab06f6c59 100644
--- a/src/lib/netlist/devices/nld_7497.h
+++ b/src/lib/netlist/devices/nld_7497.h
@@ -22,8 +22,8 @@
*
* When the rate input is binary 0 (all rate inputs low), Z remains high [and Y low].
*
- * The unity/cascade input, when connected to the clock input, passes
- * clock frequency (inverted) to the Y output when the rate input/decoding
+ * The unity/cascade input, when connected to the clock input, passes
+ * clock frequency (inverted) to the Y output when the rate input/decoding
* gates are inhibited by the strobe.
*
* When CLR is H, states of CLK and STRB can affect Y and Z. Default are