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Diffstat (limited to 'src/devices/video/ppu2c0x_vt.cpp')
-rw-r--r--src/devices/video/ppu2c0x_vt.cpp9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/devices/video/ppu2c0x_vt.cpp b/src/devices/video/ppu2c0x_vt.cpp
index ba268bc811c..8fc25cf88cd 100644
--- a/src/devices/video/ppu2c0x_vt.cpp
+++ b/src/devices/video/ppu2c0x_vt.cpp
@@ -117,17 +117,18 @@ void ppu_vt03_device::set_new_pen(int i)
WRITE8_MEMBER(ppu_vt03_device::palette_write)
{
//logerror("pal write %d %02x\n", offset, data);
+ // why is the check pal_mask = (m_pal_mode == PAL_MODE_NEW_VG) ? 0x08 : 0x80 in set_2010_reg and 0x04 : 0x80 here?
uint8_t pal_mask = (m_pal_mode == PAL_MODE_NEW_VG) ? 0x04 : 0x80;
if (m_201x_regs[0] & pal_mask)
{
- m_newpal[offset] = data;
+ m_newpal[offset&0xff] = data;
set_new_pen(offset);
}
else
{
- if(m_pal_mode == PAL_MODE_NEW_VG)
- m_newpal[offset] = data;
+ //if(m_pal_mode == PAL_MODE_NEW_VG) // ddrdismx writes the palette before setting the register but doesn't use 'PAL_MODE_NEW_VG', Konami logo is missing if you don't allow writes to be stored for when we switch
+ m_newpal[offset&0xff] = data;
ppu2c0x_device::palette_write(space, offset, data);
}
}
@@ -184,6 +185,8 @@ void ppu_vt03_device::device_reset()
for (int i = 0;i < 0x20;i++)
set_201x_reg(i, 0x00);
+ //m_201x_regs[0] = 0x86; // alt fix for ddrdismx would be to set the default palette mode here
+
init_palette();
m_read_bg4_bg3 = 0;