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Diffstat (limited to 'src/devices/machine/z80scc.h')
-rw-r--r--src/devices/machine/z80scc.h348
1 files changed, 55 insertions, 293 deletions
diff --git a/src/devices/machine/z80scc.h b/src/devices/machine/z80scc.h
index 33729f23efb..49ec17aab43 100644
--- a/src/devices/machine/z80scc.h
+++ b/src/devices/machine/z80scc.h
@@ -90,47 +90,47 @@
// Port A callbacks
#define MCFG_Z80SCC_OUT_TXDA_CB(_devcb) \
- devcb = &z80scc_device::set_out_txda_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_txd_callback<0>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_DTRA_CB(_devcb) \
- devcb = &z80scc_device::set_out_dtra_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_dtr_callback<0>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_RTSA_CB(_devcb) \
- devcb = &z80scc_device::set_out_rtsa_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_rts_callback<0>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_WREQA_CB(_devcb) \
- devcb = &z80scc_device::set_out_wreqa_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_wreq_callback<0>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_SYNCA_CB(_devcb) \
- devcb = &z80scc_device::set_out_synca_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_sync_callback<0>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_RXDRQA_CB(_devcb) \
- devcb = &z80scc_device::set_out_rxdrqa_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_rxdrq_callback<0>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_TXDRQA_CB(_devcb) \
- devcb = &z80scc_device::set_out_txdrqa_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_txdrq_callback<0>(*device, DEVCB_##_devcb);
// Port B callbacks
#define MCFG_Z80SCC_OUT_TXDB_CB(_devcb) \
- devcb = &z80scc_device::set_out_txdb_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_txd_callback<1>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_DTRB_CB(_devcb) \
- devcb = &z80scc_device::set_out_dtrb_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_dtr_callback<1>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_RTSB_CB(_devcb) \
- devcb = &z80scc_device::set_out_rtsb_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_rts_callback<1>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_WREQB_CB(_devcb) \
- devcb = &z80scc_device::set_out_wreqb_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_wreq_callback<1>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_SYNCB_CB(_devcb) \
- devcb = &z80scc_device::set_out_syncb_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_sync_callback<1>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_RXDRQB_CB(_devcb) \
- devcb = &z80scc_device::set_out_rxdrqb_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_rxdrq_callback<1>(*device, DEVCB_##_devcb);
#define MCFG_Z80SCC_OUT_TXDRQB_CB(_devcb) \
- devcb = &z80scc_device::set_out_txdrqb_callback(*device, DEVCB_##_devcb);
+ devcb = &z80scc_device::set_out_txdrq_callback<1>(*device, DEVCB_##_devcb);
//**************************************************************************
@@ -242,7 +242,7 @@ public:
uint8_t m_rr14; // REG_RR14_WR7_OR_R10
uint8_t m_rr15; // REG_RR15_WR15_EXT_STAT
- // write registers enum
+ // write registers enum
uint8_t m_wr0; // REG_WR0_COMMAND_REGPT
uint8_t m_wr1; // REG_WR1_INT_DMA_ENABLE
uint8_t m_wr2; // REG_WR2_INT_VECTOR
@@ -264,45 +264,45 @@ public:
protected:
enum
{
- RCV_IDLE = 0,
- RCV_SEEKING = 1,
- RCV_SAMPLING = 2
+ RCV_IDLE = 0,
+ RCV_SEEKING = 1,
+ RCV_SAMPLING = 2
};
enum
{
- INT_TRANSMIT = 0,
- INT_EXTERNAL = 1,
- INT_RECEIVE = 2,
- INT_SPECIAL = 3,
+ INT_TRANSMIT = 0,
+ INT_EXTERNAL = 1,
+ INT_RECEIVE = 2,
+ INT_SPECIAL = 3,
};
enum
{
- INT_TRANSMIT_PRIO = 1,
- INT_EXTERNAL_PRIO = 0,
- INT_RECEIVE_PRIO = 2,
- INT_SPECIAL_PRIO = 0,
+ INT_TRANSMIT_PRIO = 1,
+ INT_EXTERNAL_PRIO = 0,
+ INT_RECEIVE_PRIO = 2,
+ INT_SPECIAL_PRIO = 0,
};
// Read registers
enum
{
- REG_RR0_STATUS = 0,
+ REG_RR0_STATUS = 0,
REG_RR1_SPEC_RCV_COND = 1,
REG_RR2_INTERRUPT_VECT = 2,
REG_RR3_INTERUPPT_PEND = 3,
- REG_RR4_WR4_OR_RR0 = 4,
- REG_RR5_WR5_OR_RR0 = 5,
- REG_RR6_LSB_OR_RR2 = 6,
- REG_RR7_MSB_OR_RR3 = 7,
+ REG_RR4_WR4_OR_RR0 = 4,
+ REG_RR5_WR5_OR_RR0 = 5,
+ REG_RR6_LSB_OR_RR2 = 6,
+ REG_RR7_MSB_OR_RR3 = 7,
REG_RR8_RECEIVE_DATA = 8,
- REG_RR9_WR3_OR_RR13 = 9,
+ REG_RR9_WR3_OR_RR13 = 9,
REG_RR10_MISC_STATUS = 10,
REG_RR11_WR10_OR_RR15 = 11,
REG_RR12_LO_TIME_CONST = 12,
REG_RR13_HI_TIME_CONST = 13,
- REG_RR14_WR7_OR_R10 = 14,
+ REG_RR14_WR7_OR_R10 = 14,
REG_RR15_WR15_EXT_STAT = 15
};
@@ -329,237 +329,6 @@ protected:
enum
{
- RR0_RX_CHAR_AVAILABLE = 0x01,
- RR0_ZC = 0x02,
- RR0_TX_BUFFER_EMPTY = 0x04,
- RR0_DCD = 0x08,
- RR0_SYNC_HUNT = 0x10,
- RR0_CTS = 0x20,
- RR0_TX_UNDERRUN = 0x40,
- RR0_BREAK_ABORT = 0x80
- };
-
- enum
- {
- RR1_ALL_SENT = 0x01,
- RR1_RESIDUE_CODE_MASK = 0x0e,
- RR1_PARITY_ERROR = 0x10,
- RR1_RX_OVERRUN_ERROR = 0x20,
- RR1_CRC_FRAMING_ERROR = 0x40,
- RR1_END_OF_FRAME = 0x80
- };
-
- enum
- {
- RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
- RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
- RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
- RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
- };
-
- enum
- {
- RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers
- RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels)
- RR3_CHANB_RX_IP = 0x04, // channel B return all zero
- RR3_CHANA_EXT_IP = 0x08,
- RR3_CHANA_TX_IP = 0x10,
- RR3_CHANA_RX_IP = 0x20
- };
-
- enum // Universal Bus WR0 commands for 85X30
- {
- WR0_REGISTER_MASK = 0x07,
- WR0_COMMAND_MASK = 0x38, // COMMANDS
- WR0_NULL = 0x00, // 0 0 0
- WR0_POINT_HIGH = 0x08, // 0 0 1
- WR0_RESET_EXT_STATUS = 0x10, // 0 1 0
- WR0_SEND_ABORT = 0x18, // 0 1 1
- WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
- WR0_RESET_TX_INT = 0x28, // 1 0 1
- WR0_ERROR_RESET = 0x30, // 1 1 0
- WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1
- WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET
- WR0_CRC_RESET_NULL = 0x00, // 0 0
- WR0_CRC_RESET_RX = 0x40, // 0 1
- WR0_CRC_RESET_TX = 0x80, // 1 0
- WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // 1 1
- };
-
- enum // ZBUS WR0 commands or 80X30
- {
- WR0_Z_COMMAND_MASK = 0x38, // COMMANDS
- WR0_Z_NULL_1 = 0x00, // 0 0 0
- WR0_Z_NULL_2 = 0x08, // 0 0 1
- WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0
- WR0_Z_SEND_ABORT = 0x18, // 0 1 1
- WR0_Z_ENABLE_INT_NEXT_RX= 0x20, // 1 0 0
- WR0_Z_RESET_TX_INT = 0x28, // 1 0 1
- WR0_Z_ERROR_RESET = 0x30, // 1 1 0
- WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1
- WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B
- WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0
- WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1
- };
-
- enum
- {
- WR1_EXT_INT_ENABLE = 0x01,
- WR1_TX_INT_ENABLE = 0x02,
- WR1_PARITY_IS_SPEC_COND = 0x04,
- WR1_RX_INT_MODE_MASK = 0x18,
- WR1_RX_INT_DISABLE = 0x00,
- WR1_RX_INT_FIRST = 0x08,
- WR1_RX_INT_ALL = 0x10,
- WR1_RX_INT_PARITY = 0x18,
- WR1_WREQ_ON_RX_TX = 0x20,
- WR1_WREQ_FUNCTION = 0x40,
- WR1_WREQ_ENABLE = 0x80
- };
-
- enum
- {
- WR3_RX_ENABLE = 0x01,
- WR3_SYNC_CHAR_LOAD_INHIBIT = 0x02,
- WR3_ADDRESS_SEARCH_MODE = 0x04,
- WR3_RX_CRC_ENABLE = 0x08,
- WR3_ENTER_HUNT_MODE = 0x10,
- WR3_AUTO_ENABLES = 0x20,
- WR3_RX_WORD_LENGTH_MASK = 0xc0,
- WR3_RX_WORD_LENGTH_5 = 0x00,
- WR3_RX_WORD_LENGTH_7 = 0x40,
- WR3_RX_WORD_LENGTH_6 = 0x80,
- WR3_RX_WORD_LENGTH_8 = 0xc0
- };
-
- enum
- {
- WR4_PARITY_ENABLE = 0x01,
- WR4_PARITY_EVEN = 0x02,
- WR4_STOP_BITS_MASK = 0x0c,
- WR4_STOP_BITS_1 = 0x04,
- WR4_STOP_BITS_1_5 = 0x08,
- WR4_STOP_BITS_2 = 0x0c,
- WR4_SYNC_MODE_MASK = 0x30,
- WR4_SYNC_MODE_8_BIT = 0x00,
- WR4_SYNC_MODE_16_BIT = 0x10,
- WR4_BIT4 = 0x10,
- WR4_SYNC_MODE_SDLC = 0x20,
- WR4_BIT5 = 0x20,
- WR4_SYNC_MODE_EXT = 0x30,
- WR4_CLOCK_RATE_MASK = 0xc0,
- WR4_CLOCK_RATE_X1 = 0x00,
- WR4_CLOCK_RATE_X16 = 0x40,
- WR4_CLOCK_RATE_X32 = 0x80,
- WR4_CLOCK_RATE_X64 = 0xc0
- };
-
- enum
- {
- WR5_TX_CRC_ENABLE = 0x01,
- WR5_RTS = 0x02,
- WR5_CRC16 = 0x04,
- WR5_TX_ENABLE = 0x08,
- WR5_SEND_BREAK = 0x10,
- WR5_TX_WORD_LENGTH_MASK = 0x60,
- WR5_TX_WORD_LENGTH_5 = 0x00,
- WR5_TX_WORD_LENGTH_6 = 0x40,
- WR5_TX_WORD_LENGTH_7 = 0x20,
- WR5_TX_WORD_LENGTH_8 = 0x60,
- WR5_DTR = 0x80
- };
-
-
- enum
- {
- WR7P_TX_FIFO_EMPTY = 0x04
- };
-
- enum
- {
- WR9_CMD_MASK = 0xC0,
- WR9_CMD_NORESET = 0x00,
- WR9_CMD_CHNB_RESET = 0x40,
- WR9_CMD_CHNA_RESET = 0x80,
- WR9_CMD_HW_RESET = 0xC0,
- WR9_BIT_VIS = 0x01,
- WR9_BIT_NV = 0x02,
- WR9_BIT_DLC = 0x04,
- WR9_BIT_MIE = 0x08,
- WR9_BIT_SHSL = 0x10,
- WR9_BIT_IACK = 0x20
- };
-
- enum
- {
- WR10_8_6_BIT_SYNC = 0x01,
- WR10_LOOP_MODE = 0x02,
- WR10_ABORT_FLAG_UNDERRUN = 0x04,
- WR10_MARK_FLAG_IDLE = 0x08,
- WR10_GO_ACTIVE_ON_POLL = 0x10,
- WR10_ENCODING_MASK = 0x60,
- WR10_NRZ_ENCODING = 0x00,
- WR10_NRZI_ENCODING = 0x20,
- WR10_BIT5 = 0x20,
- WR10_FM1_ENCODING = 0x40,
- WR10_BIT6 = 0x40,
- WR10_FM0_ENCODING = 0x60,
- WR10_CRC_PRESET = 0x80
- };
-
- enum
- {
- WR11_RCVCLK_TYPE = 0x80,
- WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK
- WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0
- WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1
- WR11_RCVCLK_SRC_BR = 0x40, // 1 0
- WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1
- WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK
- WR11_TRACLK_SRC_RTXC = 0x00, // 0 0
- WR11_TRACLK_SRC_TRXC = 0x08, // 0 1
- WR11_TRACLK_SRC_BR = 0x10, // 1 0
- WR11_TRACLK_SRC_DPLL = 0x18, // 1 1
- WR11_TRXC_DIRECTION = 0x04,
- WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK
- WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0
- WR11_TRXSRC_SRC_TRA = 0x01, // 0 1
- WR11_TRXSRC_SRC_BR = 0x02, // 1 0
- WR11_TRXSRC_SRC_DPLL = 0x03 // 1 1
- };
-
- enum
- {
- WR14_DPLL_CMD_MASK = 0xe0, // Command
- WR14_CMD_NULL = 0x00, // 0 0 0
- WR14_CMD_ESM = 0x20, // 0 0 1
- WR14_CMD_RMC = 0x40, // 0 1 0
- WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1
- WR14_CMD_SS_BRG = 0x80, // 1 0 0
- WR14_CMD_SS_RTXC = 0xa0, // 1 0 1
- WR14_CMD_SET_FM = 0xc0, // 1 1 0
- WR14_CMD_SET_NRZI = 0xe0, // 1 1 1
- WR14_BRG_ENABLE = 0x01,
- WR14_BRG_SOURCE = 0x02,
- WR14_DTR_REQ_FUNC = 0x04,
- WR14_AUTO_ECHO = 0x08,
- WR14_LOCAL_LOOPBACK = 0x10
- };
-
- enum
- {
- WR15_WR7PRIME = 0x01,
- WR15_ZEROCOUNT = 0x02,
- WR15_STATUS_FIFO = 0x04,
- WR15_DCD = 0x08,
- WR15_SYNC = 0x10,
- WR15_CTS = 0x20,
- WR15_TX_EOM = 0x40,
- WR15_BREAK_ABORT = 0x80
- };
-
- enum
- {
TIMER_ID_BAUD,
TIMER_ID_XTAL,
TIMER_ID_RTXC,
@@ -632,6 +401,12 @@ protected:
// SCC specifics
int m_ph; // Point high command to access regs 08-0f
uint8_t m_zc;
+private:
+ // helpers
+ void out_txd_cb(int state);
+ void out_rts_cb(int state);
+ void out_dtr_cb(int state);
+
};
@@ -645,21 +420,14 @@ public:
// construction/destruction
z80scc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- template <class Object> static devcb_base &set_out_txda_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txda_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_dtra_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_dtra_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_rtsa_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rtsa_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_wreqa_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_wreqa_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_synca_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_synca_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_txdb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txdb_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_dtrb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_dtrb_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_rtsb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rtsb_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_wreqb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_wreqb_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_syncb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_syncb_cb.set_callback(std::forward<Object>(cb)); }
+ template <unsigned N, class Object> static devcb_base &set_out_txd_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txd_cb[N].set_callback(std::forward<Object>(cb)); }
+ template <unsigned N, class Object> static devcb_base &set_out_dtr_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_dtr_cb[N].set_callback(std::forward<Object>(cb)); }
+ template <unsigned N, class Object> static devcb_base &set_out_rts_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rts_cb[N].set_callback(std::forward<Object>(cb)); }
+ template <unsigned N, class Object> static devcb_base &set_out_wreq_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_wreq_cb[N].set_callback(std::forward<Object>(cb)); }
+ template <unsigned N, class Object> static devcb_base &set_out_sync_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_sync_cb[N].set_callback(std::forward<Object>(cb)); }
+ template <unsigned N, class Object> static devcb_base &set_out_rxdrq_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rxdrq_cb[N].set_callback(std::forward<Object>(cb)); }
+ template <unsigned N, class Object> static devcb_base &set_out_txdrq_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txdrq_cb[N].set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_out_int_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_int_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_rxdrqa_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rxdrqa_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_txdrqa_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txdrqa_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_rxdrqb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rxdrqb_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> static devcb_base &set_out_txdrqb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txdrqb_cb.set_callback(std::forward<Object>(cb)); }
static void static_set_cputag(device_t &device, const char *tag)
{
@@ -727,6 +495,7 @@ protected:
z80scc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t variant);
// device-level overrides
+ virtual void device_resolve_objects() override;
virtual void device_start() override;
virtual void device_reset() override;
virtual void device_add_mconfig(machine_config &config) override;
@@ -781,23 +550,16 @@ protected:
int m_rxcb;
int m_txcb;
- devcb_write_line m_out_txda_cb;
- devcb_write_line m_out_dtra_cb;
- devcb_write_line m_out_rtsa_cb;
- devcb_write_line m_out_wreqa_cb;
- devcb_write_line m_out_synca_cb;
-
- devcb_write_line m_out_txdb_cb;
- devcb_write_line m_out_dtrb_cb;
- devcb_write_line m_out_rtsb_cb;
- devcb_write_line m_out_wreqb_cb;
- devcb_write_line m_out_syncb_cb;
+ // internal state
+ devcb_write_line m_out_txd_cb[2];
+ devcb_write_line m_out_dtr_cb[2];
+ devcb_write_line m_out_rts_cb[2];
+ devcb_write_line m_out_wreq_cb[2];
+ devcb_write_line m_out_sync_cb[2];
+ devcb_write_line m_out_rxdrq_cb[2];
+ devcb_write_line m_out_txdrq_cb[2];
devcb_write_line m_out_int_cb;
- devcb_write_line m_out_rxdrqa_cb;
- devcb_write_line m_out_txdrqa_cb;
- devcb_write_line m_out_rxdrqb_cb;
- devcb_write_line m_out_txdrqb_cb;
int m_int_state[6]; // interrupt state
int m_int_source[6]; // interrupt source