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Diffstat (limited to 'src/devices/machine/ym3802.h')
-rw-r--r--src/devices/machine/ym3802.h36
1 files changed, 18 insertions, 18 deletions
diff --git a/src/devices/machine/ym3802.h b/src/devices/machine/ym3802.h
index 19a71595060..30c9bde478b 100644
--- a/src/devices/machine/ym3802.h
+++ b/src/devices/machine/ym3802.h
@@ -27,7 +27,7 @@
#define MCFG_YM3802_TXD_HANDLER(_devcb) \
devcb = &ym3802_device::set_txd_handler(*device, DEVCB_##_devcb);
-
+
class ym3802_device : public device_t, public device_serial_interface
{
public:
@@ -40,7 +40,7 @@ public:
DECLARE_READ8_MEMBER(read);
DECLARE_WRITE8_MEMBER(write);
-
+
uint8_t vector() { return m_vector; }
protected:
@@ -55,57 +55,57 @@ private:
REG_RGR, // Register Group / System Control
REG_ISR, // Interrupt Service (read only)
REG_ICR, // Interrupt Clear (write only)
-
+
REG_IOR, // Interrupt Vector Offset Request
REG_IMR, // Interrupt Mode Control
REG_IER, // Interrupt Enable Request
REG_UNUSED1,
-
+
REG_DMR = 14, // Real Time Message Control
REG_DCR, // Real Time Message Request
REG_DSR, // FIFO IRx Data
REG_DNR, // FIFO IRx Control
-
- REG_RRR = 24, // Rx Rate
+
+ REG_RRR = 24, // Rx Rate
REG_RMR, // Rx Mode
REG_AMR, // Address Hunter Maker
REG_ADR, // Address Hunter Device
-
+
REG_RSR = 34, // FIFO Rx Buffer Status
REG_RCR, // FIFO Rx Buffer Control
REG_RDR, // FIFO Rx Data
REG_UNUSED2,
-
+
REG_TRR = 44, // Tx Rate
REG_TMR, // Tx Mode
REG_UNUSED3,
REG_UNUSED4,
-
+
REG_TSR = 54, // FIFO Tx Status
REG_TCR, // FIFO Tx Control
REG_TDR, // FIFO Tx Data
REG_UNUSED5,
-
+
REG_FSR = 64, // FSK status
REG_FCR, // FSK control
REG_CCR, // Click Counter Control
REG_CDR, // Click Counter Data (7-bit)
-
+
REG_SRR = 74, // Recording Counter current value
REG_SCR, // Sequencer Control
REG_SPR_LOW, // Playback Counter (low 8-bits)
REG_SPR_HIGH, // Playback Counter (high 7-bits)
-
+
REG_GTR_LOW = 84, // General Timer (low 8-bits)
REG_GTR_HIGH, // General Timer (high 6-bits)
REG_MTR_LOW, // MIDI Clock Timer (low 8-bits)
REG_MTR_HIGH, // MIDI Clock Timer (high 6-bits)
-
+
REG_EDR = 94, // External I/O Direction
REG_EOR, // External I/O Output Data
REG_EIR, // External I/O Input Data
REG_UNUSED7,
-
+
REG_MAX = 100
};
@@ -136,14 +136,14 @@ private:
void set_comms_mode();
void set_irq(uint8_t irq);
void reset_irq(uint8_t irq);
-
+
devcb_write_line m_irq_handler;
devcb_write_line m_txd_handler;
devcb_read_line m_rxd_handler;
emu_timer* m_clock_timer;
emu_timer* m_midi_timer;
emu_timer* m_midi_counter_timer;
-
+
std::vector<uint8_t> m_reg;
uint8_t m_wdr;
uint64_t m_prev_rate;
@@ -155,13 +155,13 @@ private:
uint8_t m_click_counter;
uint8_t m_click_counter_base;
uint8_t m_vector;
-
+
std::queue<uint8_t> m_tx_fifo;
std::queue<uint8_t> m_rx_fifo;
std::queue<uint8_t> m_itx_fifo;
std::queue<uint8_t> m_irx_fifo;
bool m_tx_busy;
-
+
uint64_t m_clkm_rate;
uint64_t m_clkf_rate;
};