diff options
Diffstat (limited to 'src/devices/machine/68340sim.h')
-rw-r--r-- | src/devices/machine/68340sim.h | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/src/devices/machine/68340sim.h b/src/devices/machine/68340sim.h index be4710934b5..d8447b999fc 100644 --- a/src/devices/machine/68340sim.h +++ b/src/devices/machine/68340sim.h @@ -22,14 +22,14 @@ public: uint8_t m_pparb; // 0xff // SIM - uint16_t m_mcr; // 0x608f - uint16_t m_syncr; // 0x3f00 - uint16_t m_avr_rsr; // 0x0000 + uint16_t m_mcr; // 0x608f + uint16_t m_syncr; // 0x3f00 + uint16_t m_avr_rsr; // 0x0000 uint16_t m_swiv_sypcr;//0x0f00 - uint16_t m_picr; // 0x000f - uint16_t m_pitr; // 0x0000 | ~MODCK pin - uint16_t m_swsr; // 0x0000 - + uint16_t m_picr; // 0x000f + uint16_t m_pitr; // 0x0000 | ~MODCK pin + uint16_t m_swsr; // 0x0000 + // Timers and counters uint8_t m_pit_counter; @@ -60,7 +60,7 @@ public: REG_AM_CS3 = 0x58, REG_BA_CS3 = 0x5c, }; - + enum { REG_MCR_FRZ1 = 0x4000, REG_MCR_FRZ0 = 0x2000, @@ -69,49 +69,49 @@ public: REG_MCR_SVREG = 0x0800, REG_MCR_ARBLV = 0x000f, }; - + enum { - REG_AVR_VEC = 0xff00, - REG_RSR_RESBITS = 0x00ff, + REG_AVR_VEC = 0xff00, + REG_RSR_RESBITS = 0x00ff, }; - + enum { - REG_SWIV_VEC = 0xff00, - REG_SYPCR_SWE = 0x0080, + REG_SWIV_VEC = 0xff00, + REG_SYPCR_SWE = 0x0080, REG_SYPCR_SWRI = 0x0040, REG_SYPCR_SWT = 0x0030, REG_SYPCR_DBFE = 0x0008, REG_SYPCR_BME = 0x0004, REG_SYPCR_BMT = 0x0003, }; - + enum { - REG_PICR_PIRQL = 0x0700, - REG_PICR_PIVEC = 0x00ff, + REG_PICR_PIRQL = 0x0700, + REG_PICR_PIVEC = 0x00ff, }; - + enum { - REG_PITR_SWP = 0x0200, - REG_PITR_PTP = 0x0100, - REG_PITR_COUNT = 0x00ff, + REG_PITR_SWP = 0x0200, + REG_PITR_PTP = 0x0100, + REG_PITR_COUNT = 0x00ff, }; - + enum { - REG_SYNCR_W = 0x8000, - REG_SYNCR_X = 0x4000, - REG_SYNCR_Y_MSK = 0x3f00, - REG_SYNCR_SLIMP = 0x0010, - REG_SYNCR_SLOCK = 0x0008, - REG_SYNCR_RSTEN = 0x0004, - REG_SYNCR_STSIM = 0x0002, - REG_SYNCR_STEXT = 0x0001, + REG_SYNCR_W = 0x8000, + REG_SYNCR_X = 0x4000, + REG_SYNCR_Y_MSK = 0x3f00, + REG_SYNCR_SLIMP = 0x0010, + REG_SYNCR_SLOCK = 0x0008, + REG_SYNCR_RSTEN = 0x0004, + REG_SYNCR_STSIM = 0x0002, + REG_SYNCR_STEXT = 0x0001, }; - + enum { CLOCK_PLL = 0x01, CLOCK_MODCK = 0x02, }; - + enum { CLOCK_MODE_EXT = 0x00, CLOCK_MODE_EXT_PLL = 0x01, |