diff options
Diffstat (limited to 'src/devices/cpu/tlcs870/tlcs870_ops_src.cpp')
-rw-r--r-- | src/devices/cpu/tlcs870/tlcs870_ops_src.cpp | 575 |
1 files changed, 522 insertions, 53 deletions
diff --git a/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp b/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp index afb1c0c9ac0..22c718a2078 100644 --- a/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp +++ b/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp @@ -29,33 +29,18 @@ // Main dispatch handlers for these -void tlcs870_device::do_e0_opcode(const uint8_t opbyte0) -{ - const uint16_t srcaddr = get_addr((opbyte0 & 0x7), READ8()); - do_e0_to_e7_opcode(opbyte0, srcaddr); -} - -void tlcs870_device::do_e1_to_e3_opcode(const uint8_t opbyte0) -{ - const uint16_t srcaddr = get_addr((opbyte0 & 0x7), 0); - do_e0_to_e7_opcode(opbyte0, srcaddr); -} - -void tlcs870_device::do_e4_opcode(const uint8_t opbyte0) +// e0 - e7 use this table +void tlcs870_device::do_srcprefixtype_opcode(const uint8_t opbyte0) { - const uint16_t srcaddr = get_addr((opbyte0 & 0x7), READ8()); - do_e0_to_e7_opcode(opbyte0, srcaddr); -} + m_cycles = get_base_srcdst_cycles(opbyte0 & 0x7); // set base number of cycles based on src prefix mode -void tlcs870_device::do_e5_to_e7_opcode(const uint8_t opbyte0) -{ - const uint16_t srcaddr = get_addr((opbyte0 & 0x7), 0); - do_e0_to_e7_opcode(opbyte0, srcaddr); -} + uint16_t srcaddr; + // (x) and (HL+d) require an immediate value + if ((opbyte0 == 0xe0) || (opbyte0 == 0xe4)) + srcaddr = get_addr((opbyte0 & 0x7), READ8()); + else + srcaddr = get_addr((opbyte0 & 0x7), 0); -// e0 - e7 use this table -void tlcs870_device::do_e0_to_e7_opcode(uint8_t opbyte0, uint16_t srcaddr) -{ const uint8_t opbyte1 = READ8(); switch (opbyte1) @@ -112,6 +97,7 @@ void tlcs870_device::do_e0_to_e7_opcode(uint8_t opbyte0, uint16_t srcaddr) void tlcs870_device::do_e0_to_e7_oprand_illegal(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { + m_cycles += 1; logerror("illegal src prefix opcode %02x %02x (src addr %04x)\n", opbyte0, opbyte1, srcaddr); } @@ -121,7 +107,21 @@ void tlcs870_device::do_e0_to_e7_oprand_illegal(const uint8_t opbyte0, const uin void tlcs870_device::do_LD_rr_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // LD rr, (src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + LD rr, (x) 1110 0000 xxxx xxxx 0001 01rr 1 - - - 5 + LD rr, (PC+A) 1110 0001 0001 01rr 1 - - - 6 + LD rr, (DE) 1110 0010 0001 01rr 1 - - - 4 + LD rr, (HL) 1110 0011 0001 01rr 1 - - - 4 + LD rr, (HL+d) 1110 0100 dddd dddd 0001 01rr 1 - - - 6 + LD rr, (HL+C) 1110 0101 0001 01rr 1 - - - 6 + LD rr, (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ? + LD rr, (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ? + + aka LD rr, (src) + */ + m_cycles += 4; + const uint16_t val = RM16(srcaddr); set_reg16(opbyte1 & 0x3, val); set_JF(); @@ -133,7 +133,21 @@ void tlcs870_device::do_LD_rr_insrc(const uint8_t opbyte0, const uint8_t opbyte1 void tlcs870_device::do_INC_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // INC (src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + INC (x) not listed, redundant encoding? ? ? ? ? ? + INC (PC+A) 1110 0001 0010 0000 C Z - - 6 + INC (DE) 1110 0010 0010 0000 C Z - - 4 + INC (HL) not listed, redundant encoding? ? ? ? ? ? + INC (HL+d) 1110 0100 dddd dddd 0010 0000 C Z - - 6 + INC (HL+C) 1110 0101 0010 0000 C Z - - 6 + INC (HL+) 1110 0110 0010 0000 C Z - - 5 + INC (-HL) 1110 0111 0010 0000 C Z - - 5 + + aka INC (src) + */ + m_cycles += 4; + uint8_t val = RM8(srcaddr); val++; @@ -153,7 +167,21 @@ void tlcs870_device::do_INC_insrc(const uint8_t opbyte0, const uint8_t opbyte1, void tlcs870_device::do_DEC_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // DEC (src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + DEC (x) not listed, redundant encoding? ? ? ? ? ? + DEC (PC+A) 1110 0001 0010 1000 C Z - - 6 + DEC (DE) 1110 0010 0010 1000 C Z - - 4 + DEC (HL) not listed, redundant encoding? ? ? ? ? ? + DEC (HL+d) 1110 0100 dddd dddd 0010 1000 C Z - - 6 + DEC (HL+C) 1110 0101 0010 1000 C Z - - 6 + DEC (HL+) 1110 0110 0010 1000 C Z - - 5 + DEC (-HL) 1110 0111 0010 1000 C Z - - 5 + + aka DEC (src) + */ + m_cycles += 4; + uint8_t val = RM8(srcaddr); val--; @@ -173,7 +201,7 @@ void tlcs870_device::do_DEC_insrc(const uint8_t opbyte0, const uint8_t opbyte1, } else { - set_ZF(); + clear_ZF(); } WM8(srcaddr, val); @@ -181,8 +209,22 @@ void tlcs870_device::do_DEC_insrc(const uint8_t opbyte0, const uint8_t opbyte1, void tlcs870_device::do_ROLD_A_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // ROLD A,(src) - // 12-bit left rotation using lower 4 bits of REG_A and content of (src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + ROLD A, (x) 1110 0000 xxxx xxxx 0000 1000 1 0 0 0 8 + ROLD A, (PC+A) not listed, invalid? ? ? ? ? ? + ROLD A, (DE) 1110 0010 0000 1000 1 0 0 0 7 + ROLD A, (HL) 1110 0011 0000 1000 1 0 0 0 7 + ROLD A, (HL+d) 1110 0100 dddd dddd 0000 1000 1 0 0 0 9 + ROLD A, (HL+C) 1110 0101 0000 1000 1 0 0 0 9 + ROLD A, (HL+) 1110 0110 0000 1000 1 0 0 0 8 + ROLD A, (-HL) 1110 0111 0000 1000 1 0 0 0 8 + + aka ROLD A,(src) + 12-bit left rotation using lower 4 bits of REG_A and content of (src) + */ + m_cycles += 7; + const uint8_t val = RM8(srcaddr); const uint8_t reg = get_reg8(REG_A); @@ -193,13 +235,27 @@ void tlcs870_device::do_ROLD_A_insrc(const uint8_t opbyte0, const uint8_t opbyte set_reg8(REG_A, tempa); WM8(srcaddr, tempval); - // TODO: flags + set_JF(); } void tlcs870_device::do_RORD_A_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // RORD A,(src) - // 12-bit right rotation using lower 4 bits of REG_A and content of (src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + RORD A, (x) 1110 0000 xxxx xxxx 0000 1001 1 0 0 0 8 + RORD A, (PC+A) not listed, invalid? ? ? ? ? ? + RORD A, (DE) 1110 0010 0000 1001 1 0 0 0 7 + RORD A, (HL) 1110 0011 0000 1001 1 0 0 0 7 + RORD A, (HL+d) 1110 0100 dddd dddd 0000 1001 1 0 0 0 9 + RORD A, (HL+C) 1110 0101 0000 1001 1 0 0 0 9 + RORD A, (HL+) 1110 0110 0000 1001 1 0 0 0 8 + RORD A, (-HL) 1110 0111 0000 1001 1 0 0 0 8 + + aka RORD A,(src) + 12-bit right rotation using lower 4 bits of REG_A and content of (src) + */ + m_cycles += 7; + const uint8_t val = RM8(srcaddr); const uint8_t reg = get_reg8(REG_A); @@ -210,15 +266,28 @@ void tlcs870_device::do_RORD_A_insrc(const uint8_t opbyte0, const uint8_t opbyte set_reg8(REG_A, tempa); WM8(srcaddr, tempval); - // TODO: flags + set_JF(); } void tlcs870_device::do_LD_inx_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // LD (x),(src) - // invalid if (src) is also (x) ? (not specified) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + LD (x), (x) not listed, invalid? or redundant? ? ? ? ? ? + LD (x), (PC+A) 1110 0001 0010 0110 xxxx xxxx 1 U - - 7 + LD (x), (DE) 1110 0010 0010 0110 xxxx xxxx 1 U - - 5 + LD (x), (HL) 1110 0011 0010 0110 xxxx xxxx 1 U - - 5 + LD (x), (HL+d) 1110 0100 dddd dddd 0010 0110 xxxx xxxx 1 U - - 7 + LD (x), (HL+C) 1110 0101 0010 0110 xxxx xxxx 1 U - - 7 + LD (x), (HL+) not listed, invalid? ? ? ? ? ? + LD (x), (-HL) not listed, invalid? ? ? ? ? ? + + aka LD (x),(src) + */ + m_cycles += 5; + const uint16_t x = READ8(); // get address x const uint8_t val = RM8(srcaddr); WM8(x, val); @@ -229,11 +298,23 @@ void tlcs870_device::do_LD_inx_insrc(const uint8_t opbyte0, const uint8_t opbyte void tlcs870_device::do_LD_inHL_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // LD (HL),(src) - const uint8_t val = RM8(srcaddr); + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + LD (HL), (x) 1110 0000 xxxx xxxx 0010 0111 1 Z - - 5 + LD (HL), (PC+A) 1110 0001 0010 0111 1 Z - - 6 + LD (HL), (DE) 1110 0010 0010 0111 1 Z - - 4 + LD (HL), (HL) 1110 0011 0010 0111 1 Z - - 4 + LD (HL), (HL+d) 1110 0100 dddd dddd 0010 0111 1 Z - - 6 + LD (HL), (HL+C) 1110 0101 0010 0111 1 Z - - 6 + LD (HL), (HL+) not listed, invalid? ? ? ? ? ? + LD (HL), (-HL) not listed, invalid? ? ? ? ? ? + + aka LD (HL),(src) + */ + m_cycles += 4; + const uint8_t val = RM8(srcaddr); const uint16_t dstaddr = get_reg16(REG_HL); - WM8(dstaddr, val); set_JF(); @@ -244,7 +325,21 @@ void tlcs870_device::do_LD_inHL_insrc(const uint8_t opbyte0, const uint8_t opbyt void tlcs870_device::do_LD_r_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // LD r, (src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + LD r, (x) 1110 0000 xxxx xxxx 0101 1rrr 1 Z - - 4 + LD r, (PC+A) 1110 0001 0101 1rrr 1 Z - - 5 + LD r, (DE) 1110 0010 0101 1rrr 1 Z - - 3 + LD r, (HL) 1110 0011 0101 1rrr 1 Z - - 3 + LD r, (HL+d) 1110 0100 dddd dddd 0101 1rrr 1 Z - - 5 + LD r, (HL+C) 1110 0101 0101 1rrr 1 Z - - 5 + LD r, (HL+) 1110 0110 0101 1rrr 1 Z - - 4 (invalid if r is H or L) + LD r, (-HL) 1110 0111 0101 1rrr 1 Z - - 4 + + aka LD r, (src) + */ + m_cycles += 3; + const uint8_t val = RM8(srcaddr); set_reg8(opbyte1 & 0x7, val); @@ -257,7 +352,21 @@ void tlcs870_device::do_LD_r_insrc(const uint8_t opbyte0, const uint8_t opbyte1, void tlcs870_device::do_MCMP_insrc_n(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // MCMP (src), n + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + MCMP (x), n 1110 0000 xxxx xxxx 0010 1111 nnnn nnnn Z Z C H 6 + MCMP (PC+A), n 1110 0001 0010 1111 nnnn nnnn Z Z C H 7 + MCMP (DE), n 1110 0010 0010 1111 nnnn nnnn Z Z C H 5 + MCMP (HL), n 1110 0011 0010 1111 nnnn nnnn Z Z C H 5 + MCMP (HL+d), n 1110 0100 dddd dddd 0010 1111 nnnn nnnn Z Z C H 7 + MCMP (HL+C), n 1110 0101 0010 1111 nnnn nnnn Z Z C H 7 + MCMP (HL+), n 1110 0110 0010 1111 nnnn nnnn Z Z C H 6 + MCMP (-HL), n 1110 0111 0010 1111 nnnn nnnn Z Z C H 6 + + aka MCMP (src), n + */ + m_cycles += 5; + const uint8_t n = READ8(); const uint8_t val = RM8(srcaddr); @@ -292,7 +401,21 @@ void tlcs870_device::do_MCMP_insrc_n(const uint8_t opbyte0, const uint8_t opbyte void tlcs870_device::do_XCH_r_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // XCH r,(src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + XCH r, (x) 1110 0000 xxxx xxxx 1010 1rrr 1 Z - - 5 + XCH r, (PC+A) 1110 0001 1010 1rrr 1 Z - - 6 + XCH r, (DE) 1110 0010 1010 1rrr 1 Z - - 4 + XCH r, (HL) 1110 0011 1010 1rrr 1 Z - - 4 + XCH r, (HL+d) 1110 0100 dddd dddd 1010 1rrr 1 Z - - 6 + XCH r, (HL+C) 1110 0101 1010 1rrr 1 Z - - 6 + XCH r, (HL+) 1110 0110 1010 1rrr 1 Z - - 5 (invalid if r is H or L) + XCH r, (-HL) 1110 0111 1010 1rrr 1 Z - - 5 + + aka XCH r,(src) + */ + m_cycles += 4; + const uint8_t val = RM8(srcaddr); const uint8_t temp = get_reg8(opbyte1 & 0x7); @@ -318,7 +441,84 @@ void tlcs870_device::do_XCH_r_insrc(const uint8_t opbyte0, const uint8_t opbyte1 void tlcs870_device::do_ALUOP_insrc_inHL(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // (ALU OP) (src), (HL) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + ADDC (x), (HL) 1110 0000 xxxx xxxx 0110 0000 C Z C H 7 + ADDC (PC+A), (HL) 1110 0001 0110 0000 C Z C H 8 + ADDC (DE), (HL) 1110 0010 0110 0000 C Z C H 6 + ADDC (HL), (HL) 1110 0011 0110 0000 C Z C H 6 + ADDC (HL+d), (HL) 1110 0100 dddd dddd 0110 0000 C Z C H 8 + ADDC (HL+C), (HL) 1110 0101 0110 0000 C Z C H 8 + ADDC (HL+), (HL) not listed, invalid? ? ? ? ? ? + ADDC (-HL), (HL) not listed, invalid? ? ? ? ? ? + + ADD (x), (HL) 1110 0000 xxxx xxxx 0110 0001 C Z C H 7 + ADD (PC+A), (HL) 1110 0001 0110 0001 C Z C H 8 + ADD (DE), (HL) 1110 0010 0110 0001 C Z C H 6 + ADD (HL), (HL) 1110 0011 0110 0001 C Z C H 6 + ADD (HL+d), (HL) 1110 0100 dddd dddd 0110 0001 C Z C H 8 + ADD (HL+C), (HL) 1110 0101 0110 0001 C Z C H 8 + ADD (HL+), (HL) not listed, invalid? ? ? ? ? ? + ADD (-HL), (HL) not listed, invalid? ? ? ? ? ? + + SUBB (x), (HL) 1110 0000 xxxx xxxx 0110 0010 C Z C H 7 + SUBB (PC+A), (HL) 1110 0001 0110 0010 C Z C H 8 + SUBB (DE), (HL) 1110 0010 0110 0010 C Z C H 6 + SUBB (HL), (HL) 1110 0011 0110 0010 C Z C H 6 + SUBB (HL+d), (HL) 1110 0100 dddd dddd 0110 0010 C Z C H 8 + SUBB (HL+C), (HL) 1110 0101 0110 0010 C Z C H 8 + SUBB (HL+), (HL) not listed, invalid? ? ? ? ? ? + SUBB (-HL), (HL) not listed, invalid? ? ? ? ? ? + + SUB (x), (HL) 1110 0000 xxxx xxxx 0110 0011 C Z C H 7 + SUB (PC+A), (HL) 1110 0001 0110 0011 C Z C H 8 + SUB (DE), (HL) 1110 0010 0110 0011 C Z C H 6 + SUB (HL), (HL) 1110 0011 0110 0011 C Z C H 6 + SUB (HL+d), (HL) 1110 0100 dddd dddd 0110 0011 C Z C H 8 + SUB (HL+C), (HL) 1110 0101 0110 0011 C Z C H 8 + SUB (HL+), (HL) not listed, invalid? ? ? ? ? ? + SUB (-HL), (HL) not listed, invalid? ? ? ? ? ? + + AND (x), (HL) 1110 0000 xxxx xxxx 0110 0100 Z Z - - 7 + AND (PC+A), (HL) 1110 0001 0110 0100 Z Z - - 8 + AND (DE), (HL) 1110 0010 0110 0100 Z Z - - 6 + AND (HL), (HL) 1110 0011 0110 0100 Z Z - - 6 + AND (HL+d), (HL) 1110 0100 dddd dddd 0110 0100 Z Z - - 8 + AND (HL+C), (HL) 1110 0101 0110 0100 Z Z - - 8 + AND (HL+), (HL) not listed, invalid? ? ? ? ? ? + AND (-HL), (HL) not listed, invalid? ? ? ? ? ? + + XOR (x), (HL) 1110 0000 xxxx xxxx 0110 0101 Z Z - - 7 + XOR (PC+A), (HL) 1110 0001 0110 0101 Z Z - - 8 + XOR (DE), (HL) 1110 0010 0110 0101 Z Z - - 6 + XOR (HL), (HL) 1110 0011 0110 0101 Z Z - - 6 + XOR (HL+d), (HL) 1110 0100 dddd dddd 0110 0101 Z Z - - 8 + XOR (HL+C), (HL) 1110 0101 0110 0101 Z Z - - 8 + XOR (HL+), (HL) not listed, invalid? ? ? ? ? ? + XOR (-HL), (HL) not listed, invalid? ? ? ? ? ? + + OR (x), (HL) 1110 0000 xxxx xxxx 0110 0110 Z Z - - 7 + OR (PC+A), (HL) 1110 0001 0110 0110 Z Z - - 8 + OR (DE), (HL) 1110 0010 0110 0110 Z Z - - 6 + OR (HL), (HL) 1110 0011 0110 0110 Z Z - - 6 + OR (HL+d), (HL) 1110 0100 dddd dddd 0110 0110 Z Z - - 8 + OR (HL+C), (HL) 1110 0101 0110 0110 Z Z - - 8 + OR (HL+), (HL) not listed, invalid? ? ? ? ? ? + OR (-HL), (HL) not listed, invalid? ? ? ? ? ? + + CMP (x), (HL) 1110 0000 xxxx xxxx 0110 0111 Z Z C H 6 + CMP (PC+A), (HL) 1110 0001 0110 0111 Z Z C H 7 + CMP (DE), (HL) 1110 0010 0110 0111 Z Z C H 5 + CMP (HL), (HL) 1110 0011 0110 0111 Z Z C H 5 + CMP (HL+d), (HL) 1110 0100 dddd dddd 0110 0111 Z Z C H 7 + CMP (HL+C), (HL) 1110 0101 0110 0111 Z Z C H 7 + CMP (HL+), (HL) not listed, invalid? ? ? ? ? ? + CMP (-HL), (HL) not listed, invalid? ? ? ? ? ? + + aka (ALU OP) (src), (HL) + */ + m_cycles += 6; + const int aluop = (opbyte1 & 0x7); const uint8_t val = RM8(srcaddr); @@ -328,13 +528,91 @@ void tlcs870_device::do_ALUOP_insrc_inHL(const uint8_t opbyte0, const uint8_t op if (aluop != 0x07) // CMP doesn't write back { + m_cycles -= 1; // one less for CMP here? WM8(srcaddr, result); } } void tlcs870_device::do_ALUOP_insrc_n(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // (ALU OP) (src), n + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + ADDC (x), n 1110 0000 xxxx xxxx 0111 0000 nnnn nnnn C Z C H 6 + ADDC (PC+A), n 1110 0001 0111 0000 nnnn nnnn C Z C H 7 + ADDC (DE), n 1110 0010 0111 0000 nnnn nnnn C Z C H 5 + ADDC (HL), n 1110 0011 0111 0000 nnnn nnnn C Z C H 5 + ADDC (HL+d), n 1110 0100 dddd dddd 0111 0000 nnnn nnnn C Z C H 7 + ADDC (HL+C), n 1110 0101 0111 0000 nnnn nnnn C Z C H 7 + ADDC (HL+), n 1110 0110 0111 0000 nnnn nnnn C Z C H 6 + ADDC (-HL), n 1110 0111 0111 0000 nnnn nnnn C Z C H 6 + + ADD (x), n 1110 0000 xxxx xxxx 0111 0001 nnnn nnnn C Z C H 6 + ADD (PC+A), n 1110 0001 0111 0001 nnnn nnnn C Z C H 7 + ADD (DE), n 1110 0010 0111 0001 nnnn nnnn C Z C H 5 + ADD (HL), n 1110 0011 0111 0001 nnnn nnnn C Z C H 5 + ADD (HL+d), n 1110 0100 dddd dddd 0111 0001 nnnn nnnn C Z C H 7 + ADD (HL+C), n 1110 0101 0111 0001 nnnn nnnn C Z C H 7 + ADD (HL+), n 1110 0110 0111 0001 nnnn nnnn C Z C H 6 + ADD (-HL), n 1110 0111 0111 0001 nnnn nnnn C Z C H 6 + + SUBB (x), n 1110 0000 xxxx xxxx 0111 0010 nnnn nnnn C Z C H 6 + SUBB (PC+A), n 1110 0001 0111 0010 nnnn nnnn C Z C H 7 + SUBB (DE), n 1110 0010 0111 0010 nnnn nnnn C Z C H 5 + SUBB (HL), n 1110 0011 0111 0010 nnnn nnnn C Z C H 5 + SUBB (HL+d), n 1110 0100 dddd dddd 0111 0010 nnnn nnnn C Z C H 7 + SUBB (HL+C), n 1110 0101 0111 0010 nnnn nnnn C Z C H 7 + SUBB (HL+), n 1110 0110 0111 0010 nnnn nnnn C Z C H 6 + SUBB (-HL), n 1110 0111 0111 0010 nnnn nnnn C Z C H 6 + + SUB (x), n 1110 0000 xxxx xxxx 0111 0011 nnnn nnnn C Z C H 6 + SUB (PC+A), n 1110 0001 0111 0011 nnnn nnnn C Z C H 7 + SUB (DE), n 1110 0010 0111 0011 nnnn nnnn C Z C H 5 + SUB (HL), n 1110 0011 0111 0011 nnnn nnnn C Z C H 5 + SUB (HL+d), n 1110 0100 dddd dddd 0111 0011 nnnn nnnn C Z C H 7 + SUB (HL+C), n 1110 0101 0111 0011 nnnn nnnn C Z C H 7 + SUB (HL+), n 1110 0110 0111 0011 nnnn nnnn C Z C H 6 + SUB (-HL), n 1110 0111 0111 0011 nnnn nnnn C Z C H 6 + + AND (x), n 1110 0000 xxxx xxxx 0111 0100 nnnn nnnn Z Z - - 6 + AND (PC+A), n 1110 0001 0111 0100 nnnn nnnn Z Z - - 7 + AND (DE), n 1110 0010 0111 0100 nnnn nnnn Z Z - - 5 + AND (HL), n 1110 0011 0111 0100 nnnn nnnn Z Z - - 5 + AND (HL+d), n 1110 0100 dddd dddd 0111 0100 nnnn nnnn Z Z - - 7 + AND (HL+C), n 1110 0101 0111 0100 nnnn nnnn Z Z - - 7 + AND (HL+), n 1110 0110 0111 0100 nnnn nnnn Z Z - - 6 + AND (-HL), n 1110 0111 0111 0100 nnnn nnnn Z Z - - 6 + + XOR (x), n 1110 0000 xxxx xxxx 0111 0101 nnnn nnnn Z Z - - 6 + XOR (PC+A), n 1110 0001 0111 0101 nnnn nnnn Z Z - - 7 + XOR (DE), n 1110 0010 0111 0101 nnnn nnnn Z Z - - 5 + XOR (HL), n 1110 0011 0111 0101 nnnn nnnn Z Z - - 5 + XOR (HL+d), n 1110 0100 dddd dddd 0111 0101 nnnn nnnn Z Z - - 7 + XOR (HL+C), n 1110 0101 0111 0101 nnnn nnnn Z Z - - 7 + XOR (HL+), n 1110 0110 0111 0101 nnnn nnnn Z Z - - 6 + XOR (-HL), n 1110 0111 0111 0101 nnnn nnnn Z Z - - 6 + + OR (x), n 1110 0000 xxxx xxxx 0111 0110 nnnn nnnn Z Z - - 6 + OR (PC+A), n 1110 0001 0111 0110 nnnn nnnn Z Z - - 7 + OR (DE), n 1110 0010 0111 0110 nnnn nnnn Z Z - - 5 + OR (HL), n 1110 0011 0111 0110 nnnn nnnn Z Z - - 5 + OR (HL+d), n 1110 0100 dddd dddd 0111 0110 nnnn nnnn Z Z - - 7 + OR (HL+C), n 1110 0101 0111 0110 nnnn nnnn Z Z - - 7 + OR (HL+), n 1110 0110 0111 0110 nnnn nnnn Z Z - - 6 + OR (-HL), n 1110 0111 0111 0110 nnnn nnnn Z Z - - 6 + + CMP (x), n 1110 0000 xxxx xxxx 0111 0111 nnnn nnnn Z Z C H 5 + CMP (PC+A), n 1110 0001 0111 0111 nnnn nnnn Z Z C H 6 + CMP (DE), n 1110 0010 0111 0111 nnnn nnnn Z Z C H 4 + CMP (HL), n 1110 0011 0111 0111 nnnn nnnn Z Z C H 4 + CMP (HL+d), n 1110 0100 dddd dddd 0111 0111 nnnn nnnn Z Z C H 6 + CMP (HL+C), n 1110 0101 0111 0111 nnnn nnnn Z Z C H 6 + CMP (HL+), n 1110 0110 0111 0111 nnnn nnnn Z Z C H 5 + CMP (-HL), n 1110 0111 0111 0111 nnnn nnnn Z Z C H 5 + + aka (ALU OP) (src), n + */ + m_cycles += 5; + const uint8_t n = READ8(); const int aluop = (opbyte1 & 0x7); @@ -344,13 +622,91 @@ void tlcs870_device::do_ALUOP_insrc_n(const uint8_t opbyte0, const uint8_t opbyt if (aluop != 0x07) // CMP doesn't write back { + m_cycles -= 1; // one less for CMP here? WM8(srcaddr, result); } } void tlcs870_device::do_ALUOP_A_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // (ALU OP) A, (src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + ADDC A, (x) 1110 0000 xxxx xxxx 0111 1000 C Z C H 4 + ADDC A, (PC+A) 1110 0001 0111 1000 C Z C H 5 + ADDC A, (DE) 1110 0010 0111 1000 C Z C H 3 + ADDC A, (HL) 1110 0011 0111 1000 C Z C H 3 + ADDC A, (HL+d) 1110 0100 dddd dddd 0111 1000 C Z C H 5 + ADDC A, (HL+C) 1110 0101 0111 1000 C Z C H 5 + ADDC A, (HL+) 1110 0110 0111 1000 C Z C H 4 + ADDC A, (-HL) 1110 0111 0111 1000 C Z C H 4 + + ADD A, (x) 1110 0000 xxxx xxxx 0111 1001 C Z C H 4 + ADD A, (PC+A) 1110 0001 0111 1001 C Z C H 5 + ADD A, (DE) 1110 0010 0111 1001 C Z C H 3 + ADD A, (HL) 1110 0011 0111 1001 C Z C H 3 + ADD A, (HL+d) 1110 0100 dddd dddd 0111 1001 C Z C H 5 + ADD A, (HL+C) 1110 0101 0111 1001 C Z C H 5 + ADD A, (HL+) 1110 0110 0111 1001 C Z C H 4 + ADD A, (-HL) 1110 0111 0111 1001 C Z C H 4 + + SUBB A, (x) 1110 0000 xxxx xxxx 0111 1010 C Z C H 4 + SUBB A, (PC+A) 1110 0001 0111 1010 C Z C H 5 + SUBB A, (DE) 1110 0010 0111 1010 C Z C H 3 + SUBB A, (HL) 1110 0011 0111 1010 C Z C H 3 + SUBB A, (HL+d) 1110 0100 dddd dddd 0111 1010 C Z C H 5 + SUBB A, (HL+C) 1110 0101 0111 1010 C Z C H 5 + SUBB A, (HL+) 1110 0110 0111 1010 C Z C H 4 + SUBB A, (-HL) 1110 0111 0111 1010 C Z C H 4 + + SUB A, (x) 1110 0000 xxxx xxxx 0111 1011 C Z C H 4 + SUB A, (PC+A) 1110 0001 0111 1011 C Z C H 5 + SUB A, (DE) 1110 0010 0111 1011 C Z C H 3 + SUB A, (HL) 1110 0011 0111 1011 C Z C H 3 + SUB A, (HL+d) 1110 0100 dddd dddd 0111 1011 C Z C H 5 + SUB A, (HL+C) 1110 0101 0111 1011 C Z C H 5 + SUB A, (HL+) 1110 0110 0111 1011 C Z C H 4 + SUB A, (-HL) 1110 0111 0111 1011 C Z C H 4 + + AND A, (x) 1110 0000 xxxx xxxx 0111 1100 Z Z - - 4 + AND A, (PC+A) 1110 0001 0111 1100 Z Z - - 5 + AND A, (DE) 1110 0010 0111 1100 Z Z - - 3 + AND A, (HL) 1110 0011 0111 1100 Z Z - - 3 + AND A, (HL+d) 1110 0100 dddd dddd 0111 1100 Z Z - - 5 + AND A, (HL+C) 1110 0101 0111 1100 Z Z - - 5 + AND A, (HL+) 1110 0110 0111 1100 Z Z - - 4 + AND A, (-HL) 1110 0111 0111 1100 Z Z - - 4 + + XOR A, (x) 1110 0000 xxxx xxxx 0111 1101 Z Z - - 4 + XOR A, (PC+A) 1110 0001 0111 1101 Z Z - - 5 + XOR A, (DE) 1110 0010 0111 1101 Z Z - - 3 + XOR A, (HL) 1110 0011 0111 1101 Z Z - - 3 + XOR A, (HL+d) 1110 0100 dddd dddd 0111 1101 Z Z - - 5 + XOR A, (HL+C) 1110 0101 0111 1101 Z Z - - 5 + XOR A, (HL+) 1110 0110 0111 1101 Z Z - - 4 + XOR A, (-HL) 1110 0111 0111 1101 Z Z - - 4 + + OR A, (x) 1110 0000 xxxx xxxx 0111 1110 Z Z - - 4 + OR A, (PC+A) 1110 0001 0111 1110 Z Z - - 5 + OR A, (DE) 1110 0010 0111 1110 Z Z - - 3 + OR A, (HL) 1110 0011 0111 1110 Z Z - - 3 + OR A, (HL+d) 1110 0100 dddd dddd 0111 1110 Z Z - - 5 + OR A, (HL+C) 1110 0101 0111 1110 Z Z - - 5 + OR A, (HL+) 1110 0110 0111 1110 Z Z - - 4 + OR A, (-HL) 1110 0111 0111 1110 Z Z - - 4 + + CMP A, (x) 1110 0000 xxxx xxxx 0111 1111 Z Z C H 4 + CMP A, (PC+A) 1110 0001 0111 1111 Z Z C H 5 + CMP A, (DE) 1110 0010 0111 1111 Z Z C H 3 + CMP A, (HL) 1110 0011 0111 1111 Z Z C H 3 + CMP A, (HL+d) 1110 0100 dddd dddd 0111 1111 Z Z C H 5 + CMP A, (HL+C) 1110 0101 0111 1111 Z Z C H 5 + CMP A, (HL+) 1110 0110 0111 1111 Z Z C H 4 + CMP A, (-HL) 1110 0111 0111 1111 Z Z C H 4 + + aka (ALU OP) A, (src) + */ + m_cycles += 3; + const int aluop = (opbyte1 & 0x7); const uint8_t val = RM8(srcaddr); @@ -358,6 +714,7 @@ void tlcs870_device::do_ALUOP_A_insrc(const uint8_t opbyte0, const uint8_t opbyt if (aluop != 0x07) // CMP doesn't write back { + // NOT one less for CMP here? set_reg8(REG_A, result); } } @@ -368,7 +725,21 @@ void tlcs870_device::do_ALUOP_A_insrc(const uint8_t opbyte0, const uint8_t opbyt void tlcs870_device::do_CALL_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // CALL (src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + CALL (x) 1110 0000 xxxx xxxx 1111 1100 - - - - 9 + CALL (PC+A) 1110 0001 1111 1100 - - - - 10 + CALL (DE) 1110 0010 1111 1100 - - - - 8 + CALL (HL) 1110 0011 1111 1100 - - - - 8 + CALL (HL+d) 1110 0100 dddd dddd 1111 1100 - - - - 10 + CALL (HL+C) 1110 0101 1111 1100 - - - - 10 + CALL (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ? + CALL (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ? + + aka CALL (src) + */ + m_cycles += 8; + const uint16_t val = RM16(srcaddr); WM16(m_sp.d - 1, m_addr); @@ -381,7 +752,21 @@ void tlcs870_device::do_CALL_insrc(const uint8_t opbyte0, const uint8_t opbyte1, void tlcs870_device::do_JP_insrc(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // JP (src) + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + JP (x) 1110 0000 xxxx xxxx 1111 1110 1 - - - 6 + JP (PC+A) 1110 0001 1111 1110 1 - - - 7 + JP (DE) 1110 0010 1111 1110 1 - - - 5 + JP (HL) 1110 0011 1111 1110 1 - - - 5 + JP (HL+d) 1110 0100 dddd dddd 1111 1110 1 - - - 7 + JP (HL+C) 1110 0101 1111 1110 1 - - - 7 + JP (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ? + JP (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ? + + aka JP (src) + */ + m_cycles += 5; + const uint16_t val = RM16(srcaddr); m_addr = val; set_JF(); @@ -393,7 +778,21 @@ void tlcs870_device::do_JP_insrc(const uint8_t opbyte0, const uint8_t opbyte1, c void tlcs870_device::do_XOR_CF_insrcbit(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // XOR CF,(src).b + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + XOR CF, (x).b 1110 0000 xxxx xxxx 1101 0bbb ~C - * - 4 + XOR CF, (PC+A).b 1110 0001 1101 0bbb ~C - * - 5 + XOR CF, (DE).b 1110 0010 1101 0bbb ~C - * - 3 + XOR CF, (HL).b 1110 0011 1101 0bbb ~C - * - 3 + XOR CF, (HL+d).b 1110 0100 dddd dddd 1101 0bbb ~C - * - 5 + XOR CF, (HL+C).b 1110 0101 1101 0bbb ~C - * - 5 + XOR CF, (HL+).b 1110 0110 1101 0bbb ~C - * - 4 + XOR CF, (-HL).b 1110 0111 1101 0bbb ~C - * - 4 + + aka XOR CF,(src).b + */ + m_cycles += 3; + const uint8_t val = RM8(srcaddr); const uint8_t bitpos = opbyte1 & 0x7; @@ -434,7 +833,21 @@ void tlcs870_device::do_XOR_CF_insrcbit(const uint8_t opbyte0, const uint8_t opb void tlcs870_device::do_LD_insrcbit_CF(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // LD (src).b,CF + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + LD (x).b, CF 1110 0000 xxxx xxxx 1100 1bbb 1 - - - 5 + LD (PC+A).b, CF 1110 0001 1100 1bbb 1 - - - 6 + LD (DE).b, CF 1110 0010 1100 1bbb 1 - - - 4 + LD (HL).b, CF 1110 0011 1100 1bbb 1 - - - 4 + LD (HL+d).b, CF 1110 0100 dddd dddd 1100 1bbb 1 - - - 6 + LD (HL+C).b, CF 1110 0101 1100 1bbb 1 - - - 6 + LD (HL+).b, CF 1110 0110 1100 1bbb 1 - - - 5 + LD (-HL).b, CF 1110 0111 1100 1bbb 1 - - - 5 + + aka LD (src).b,CF + */ + m_cycles += 4; + uint8_t val = RM8(srcaddr); const uint8_t bitpos = opbyte1 & 0x7; @@ -457,7 +870,21 @@ void tlcs870_device::do_LD_insrcbit_CF(const uint8_t opbyte0, const uint8_t opby void tlcs870_device::do_CPL_insrcbit(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // CPL (src).b + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + CPL (x).b 1110 0000 xxxx xxxx 1100 0bbb Z * - - 5 + CPL (PC+A).b 1110 0001 1100 0bbb Z * - - 6 + CPL (DE).b 1110 0010 1100 0bbb Z * - - 4 + CPL (HL).b 1110 0011 1100 0bbb Z * - - 4 + CPL (HL+d).b 1110 0100 dddd dddd 1100 0bbb Z * - - 6 + CPL (HL+C).b 1110 0101 1100 0bbb Z * - - 6 + CPL (HL+).b 1110 0110 1100 0bbb Z * - - 5 + CPL (-HL).b 1110 0111 1100 0bbb Z * - - 5 + + aka CPL (src).b + */ + m_cycles += 4; + uint8_t val = RM8(srcaddr); const uint8_t bitpos = opbyte1 & 0x7; @@ -485,7 +912,21 @@ void tlcs870_device::do_CPL_insrcbit(const uint8_t opbyte0, const uint8_t opbyte void tlcs870_device::do_LD_CF_insrcbit(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // LD CF,(src).b aka TEST (src).b + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + LD CF, (x).b 1110 0000 xxxx xxxx 1101 1bbb ~C - * - 4 + LD CF, (PC+A).b 1110 0001 1101 1bbb ~C - * - 5 + LD CF, (DE).b 1110 0010 1101 1bbb ~C - * - 3 + LD CF, (HL).b 1110 0011 1101 1bbb ~C - * - 3 + LD CF, (HL+d).b 1110 0100 dddd dddd 1101 1bbb ~C - * - 5 + LD CF, (HL+C).b 1110 0101 1101 1bbb ~C - * - 5 + LD CF, (HL+).b 1110 0110 1101 1bbb ~C - * - 4 + LD CF, (-HL).b 1110 0111 1101 1bbb ~C - * - 4 + + aka LD CF,(src).b or TEST (src).b + */ + m_cycles += 3; + const uint8_t val = RM8(srcaddr); const uint8_t bitpos = opbyte1 & 0x7; @@ -500,7 +941,21 @@ void tlcs870_device::do_LD_CF_insrcbit(const uint8_t opbyte0, const uint8_t opby void tlcs870_device::do_SET_insrcbit(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // SET (src).b + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + SET (x).b 1110 0000 xxxx xxxx 0100 0bbb Z * - - 5 + SET (PC+A).b 1110 0001 0100 0bbb Z * - - 6 + SET (DE).b 1110 0010 0100 0bbb Z * - - 4 + SET (HL).b 1110 0011 0100 0bbb Z * - - 4 + SET (HL+d).b 1110 0100 dddd dddd 0100 0bbb Z * - - 6 + SET (HL+C).b 1110 0101 0100 0bbb Z * - - 6 + SET (HL+).b 1110 0110 0100 0bbb Z * - - 5 + SET (-HL).b 1110 0111 0100 0bbb Z * - - 5 + + aka SET (src).b + */ + m_cycles += 4; + uint8_t val = RM8(srcaddr); const uint8_t bitpos = opbyte1 & 0x7; @@ -524,7 +979,21 @@ void tlcs870_device::do_SET_insrcbit(const uint8_t opbyte0, const uint8_t opbyte void tlcs870_device::do_CLR_insrcbit(const uint8_t opbyte0, const uint8_t opbyte1, const uint16_t srcaddr) { - // CLR (src).b + /* + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + CLR (x).b 1110 0000 xxxx xxxx 0100 1bbb Z * - - 5 + CLR (PC+A).b 1110 0001 0100 1bbb Z * - - 6 + CLR (DE).b 1110 0010 0100 1bbb Z * - - 4 + CLR (HL).b 1110 0011 0100 1bbb Z * - - 4 + CLR (HL+d).b 1110 0100 dddd dddd 0100 1bbb Z * - - 6 + CLR (HL+C).b 1110 0101 0100 1bbb Z * - - 6 + CLR (HL+).b 1110 0110 0100 1bbb Z * - - 5 + CLR (-HL).b 1110 0111 0100 1bbb Z * - - 5 + + aka CLR (src).b + */ + m_cycles += 4; + uint8_t val = RM8(srcaddr); const uint8_t bitpos = opbyte1 & 0x7; |