diff options
Diffstat (limited to 'src/devices/cpu/sh/sh7604_bus.cpp')
-rw-r--r-- | src/devices/cpu/sh/sh7604_bus.cpp | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/devices/cpu/sh/sh7604_bus.cpp b/src/devices/cpu/sh/sh7604_bus.cpp index 6175fd9a5b2..a4b61bddae6 100644 --- a/src/devices/cpu/sh/sh7604_bus.cpp +++ b/src/devices/cpu/sh/sh7604_bus.cpp @@ -30,12 +30,12 @@ DEFINE_DEVICE_TYPE(SH7604_BUS, sh7604_bus_device, "sh7604bus", "SH7604 BUS Contr // LIVE DEVICE //************************************************************************** -READ16_MEMBER(sh7604_bus_device::bus_control_1_r) +uint16_t sh7604_bus_device::bus_control_1_r() { return (m_bcr1 & 0x1ff7) | (m_is_slave == true ? 0x8000 : 0); } -WRITE16_MEMBER(sh7604_bus_device::bus_control_1_w) +void sh7604_bus_device::bus_control_1_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_bcr1); if(m_bcr1 & 0x1000) // ENDIAN @@ -44,26 +44,26 @@ WRITE16_MEMBER(sh7604_bus_device::bus_control_1_w) throw emu_fatalerror("%s: enabled partial space share mode\n", tag()); } -READ16_MEMBER(sh7604_bus_device::bus_control_2_r) { return m_bcr2 & 0x00fc; } -WRITE16_MEMBER(sh7604_bus_device::bus_control_2_w) +uint16_t sh7604_bus_device::bus_control_2_r() { return m_bcr2 & 0x00fc; } +void sh7604_bus_device::bus_control_2_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_bcr2); if(m_bcr2 != 0x00fc) throw emu_fatalerror("%s: unexpected bus size register set %04x\n", tag(),data); } -READ16_MEMBER(sh7604_bus_device::wait_control_r) { return m_wcr; } -WRITE16_MEMBER(sh7604_bus_device::wait_control_w) { COMBINE_DATA(&m_wcr); } +uint16_t sh7604_bus_device::wait_control_r() { return m_wcr; } +void sh7604_bus_device::wait_control_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_wcr); } -READ16_MEMBER(sh7604_bus_device::memory_control_r) { return m_mcr & 0xfefc; } -WRITE16_MEMBER(sh7604_bus_device::memory_control_w) { COMBINE_DATA(&m_mcr); } +uint16_t sh7604_bus_device::memory_control_r() { return m_mcr & 0xfefc; } +void sh7604_bus_device::memory_control_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_mcr); } -READ16_MEMBER(sh7604_bus_device::refresh_timer_status_r) +uint16_t sh7604_bus_device::refresh_timer_status_r() { return m_rtcsr & 0x00f8; } -WRITE16_MEMBER(sh7604_bus_device::refresh_timer_control_w) +void sh7604_bus_device::refresh_timer_control_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_rtcsr); @@ -71,24 +71,24 @@ WRITE16_MEMBER(sh7604_bus_device::refresh_timer_control_w) throw emu_fatalerror("%s: enabled timer irq register with clock setting = %02x\n",tag(),data & 0x38); } -READ16_MEMBER(sh7604_bus_device::refresh_timer_counter_r) +uint16_t sh7604_bus_device::refresh_timer_counter_r() { throw emu_fatalerror("%s: reading timer counter!\n",tag()); return 0; } -WRITE16_MEMBER(sh7604_bus_device::refresh_timer_counter_w) +void sh7604_bus_device::refresh_timer_counter_w(offs_t offset, uint16_t data, uint16_t mem_mask) { throw emu_fatalerror("%s: writing timer counter %04x\n",tag(),data); //COMBINE_DATA(&m_rtcnt); } -READ16_MEMBER(sh7604_bus_device::refresh_timer_constant_r) +uint16_t sh7604_bus_device::refresh_timer_constant_r() { return m_rtcor & 0xff; } -WRITE16_MEMBER(sh7604_bus_device::refresh_timer_constant_w) +void sh7604_bus_device::refresh_timer_constant_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_rtcor); } @@ -142,13 +142,13 @@ void sh7604_bus_device::device_reset() // READ/WRITE HANDLERS //************************************************************************** -READ32_MEMBER( sh7604_bus_device::read ) +uint32_t sh7604_bus_device::read(address_space &space, offs_t offset) { // 16 bit access only, TODO return space.read_word(offset) & 0xffff; } -WRITE32_MEMBER( sh7604_bus_device::write ) +void sh7604_bus_device::write(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask) { // TODO: 8 bit access is invalid // if accessing bits 16-31, one must write ID = 0xa55a |