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Diffstat (limited to 'src/devices/cpu/sh/sh4comn.h')
-rw-r--r--src/devices/cpu/sh/sh4comn.h108
1 files changed, 4 insertions, 104 deletions
diff --git a/src/devices/cpu/sh/sh4comn.h b/src/devices/cpu/sh/sh4comn.h
index 230207652d6..ded2e5645f1 100644
--- a/src/devices/cpu/sh/sh4comn.h
+++ b/src/devices/cpu/sh/sh4comn.h
@@ -13,24 +13,10 @@
#ifndef __SH4COMN_H__
#define __SH4COMN_H__
-//#define USE_SH4DRC
-
-/* speed up delay loops, bail out of tight loops */
-#define BUSY_LOOP_HACKS 0
+#include "sh.h"
#define VERBOSE 0
-#ifdef USE_SH4DRC
-#include "cpu/drcfe.h"
-#include "cpu/drcuml.h"
-#include "cpu/drcumlsh.h"
-
-class sh4_frontend;
-#endif
-
-#define CPU_TYPE_SH3 (2)
-#define CPU_TYPE_SH4 (3)
-
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
#define EXPPRI(pl,po,p,n) (((4-(pl)) << 24) | ((15-(po)) << 16) | ((p) << 8) | (255-(n)))
@@ -50,74 +36,6 @@ class sh4_frontend;
#define FP_XFS2(r) *( (float *)(m_xf+((r) ^ m_fpu_pr)) )
#endif
-
-#ifdef USE_SH4DRC
-struct sh4_state
-{
- int icount;
-
- int pcfsel; // last pcflush entry set
- int maxpcfsel; // highest valid pcflush entry
- uint32_t pcflushes[16]; // pcflush entries
-
- drc_cache * cache; /* pointer to the DRC code cache */
- drcuml_state * drcuml; /* DRC UML generator state */
- sh4_frontend * drcfe; /* pointer to the DRC front-end class */
- uint32_t drcoptions; /* configurable DRC options */
-
- /* internal stuff */
- uint8_t cache_dirty; /* true if we need to flush the cache */
-
- /* parameters for subroutines */
- uint64_t numcycles; /* return value from gettotalcycles */
- uint32_t arg0; /* print_debug argument 1 */
- uint32_t arg1; /* print_debug argument 2 */
- uint32_t irq; /* irq we're taking */
-
- /* register mappings */
- uml::parameter regmap[16]; /* parameter to register mappings for all 16 integer registers */
-
- uml::code_handle * entry; /* entry point */
- uml::code_handle * read8; /* read byte */
- uml::code_handle * write8; /* write byte */
- uml::code_handle * read16; /* read half */
- uml::code_handle * write16; /* write half */
- uml::code_handle * read32; /* read word */
- uml::code_handle * write32; /* write word */
-
- uml::code_handle * interrupt; /* interrupt */
- uml::code_handle * nocode; /* nocode */
- uml::code_handle * out_of_cycles; /* out of cycles exception handler */
-
- uint32_t prefadr;
- uint32_t target;
-};
-#endif
-
-#ifdef USE_SH4DRC
-class sh4_frontend : public drc_frontend
-{
-public:
- sh4_frontend(sh4_state &state, uint32_t window_start, uint32_t window_end, uint32_t max_sequence);
-
-protected:
- virtual bool describe(opcode_desc &desc, const opcode_desc *prev);
-
-private:
- bool describe_group_0(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode);
- bool describe_group_2(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode);
- bool describe_group_3(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode);
- bool describe_group_4(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode);
- bool describe_group_6(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode);
- bool describe_group_8(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode);
- bool describe_group_12(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode);
- bool describe_group_15(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode);
-
- sh4_state &m_context;
-};
-#endif
-
-
enum
{
ICF = 0x00800000,
@@ -126,21 +44,15 @@ enum
OVF = 0x00020000
};
-/* Bits in SR */
-#define T 0x00000001
-#define S 0x00000002
-#define I 0x000000f0
-#define Q 0x00000100
-#define M 0x00000200
#define FD 0x00008000
#define BL 0x10000000
#define sRB 0x20000000
#define MD 0x40000000
/* 29 bits */
-#define AM 0x1fffffff
+#define SH34_AM 0x1fffffff
-#define FLAGS (MD|sRB|BL|FD|M|Q|I|S|T)
+#define SH34_FLAGS (MD|sRB|BL|FD|SH_M|SH_Q|SH_I|SH_S|SH_T)
/* Bits in FPSCR */
#define RM 0x00000003
@@ -149,20 +61,9 @@ enum
#define SZ 0x00100000
#define FR 0x00200000
-#define Rn ((opcode>>8)&15)
-#define Rm ((opcode>>4)&15)
-
#define REGFLAG_R(n) (1 << (n))
-#define REGFLAG_FR(n) (1 << (n))
-#define REGFLAG_XR(n) (1 << (n))
-/* register flags 1 */
-#define REGFLAG_PR (1 << 0)
-#define REGFLAG_MACL (1 << 1)
-#define REGFLAG_MACH (1 << 2)
-#define REGFLAG_GBR (1 << 3)
-#define REGFLAG_VBR (1 << 4)
-#define REGFLAG_SR (1 << 5)
+/* additional register flags 1 */
#define REGFLAG_SGR (1 << 6)
#define REGFLAG_FPUL (1 << 7)
#define REGFLAG_FPSCR (1 << 8)
@@ -170,5 +71,4 @@ enum
#define REGFLAG_SSR (1 << 10)
#define REGFLAG_SPC (1 << 11)
-
#endif /* __SH4COMN_H__ */