diff options
Diffstat (limited to 'src/devices/cpu/rx01/rx01.cpp')
-rw-r--r-- | src/devices/cpu/rx01/rx01.cpp | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/src/devices/cpu/rx01/rx01.cpp b/src/devices/cpu/rx01/rx01.cpp index 2447e241162..055c9d28617 100644 --- a/src/devices/cpu/rx01/rx01.cpp +++ b/src/devices/cpu/rx01/rx01.cpp @@ -7,7 +7,7 @@ This TTL disk control processor executes its custom instruction set at the rather brisk rate of 200 ns per machine cycle. However, it has no ALU or general-purpose data bus, so most of its operations amount to - simple manipulations of an assortment of synchronous counters, shift + simple manipulations of an assortment of synchronous up counters, shift registers and flip-flops. The instruction memory is organized as a series of 256-byte "fields" @@ -148,6 +148,18 @@ bool rx01_cpu_device::sep_data() return false; } +bool rx01_cpu_device::missing_clk() +{ + // TODO + return false; +} + +bool rx01_cpu_device::drv_sel_trk0() +{ + // TODO + return false; +} + bool rx01_cpu_device::test_condition() { switch (m_mb & 074) @@ -172,14 +184,22 @@ bool rx01_cpu_device::test_condition() // 16th stage of CRC generator return BIT(m_crc, 0); + case 034: + // Track zero of selected drive on head + return (m_flags & FF_IOB0) && (m_flags && FF_IOB3) && drv_sel_trk0(); + case 054: - // Separated data equals MSB of shift register + // Separated data equals shift register MSB return BIT(m_sr, 7) == sep_data(); case 060: // Sector buffer address overflow return m_bar == 07777; + case 064: + // Missing clock equals shift register MSB + return BIT(m_sr, 7) == missing_clk(); + case 074: // Flag state equals one return (m_flags & FF_FLAG) != 0; |