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Diffstat (limited to 'src/devices/cpu/powerpc/ppccom.cpp')
-rw-r--r--src/devices/cpu/powerpc/ppccom.cpp49
1 files changed, 49 insertions, 0 deletions
diff --git a/src/devices/cpu/powerpc/ppccom.cpp b/src/devices/cpu/powerpc/ppccom.cpp
index 50881d922a4..4a8a071f903 100644
--- a/src/devices/cpu/powerpc/ppccom.cpp
+++ b/src/devices/cpu/powerpc/ppccom.cpp
@@ -1162,7 +1162,10 @@ void ppc_device::device_reset()
/* initialize the 602 HID0 register */
if (m_flavor == PPC_MODEL_602)
+ {
+ m_core->spr[SPR602_ESASRR] = 0;
m_core->spr[SPR603_HID0] = 1;
+ }
/* time base starts here */
m_tb_zero_cycles = total_cycles();
@@ -1326,6 +1329,15 @@ uint32_t ppc_device::ppccom_translate_address_internal(int intention, offs_t &ad
}
}
+#if 1
+ /* 602-specific Protection-Only mode */
+ if (m_flavor == PPC_MODEL_602 && m_core->spr[SPR603_HID0] & 0x00000080)
+ {
+ // TODO
+ return 0x001;
+ }
+#endif
+
/* look up the segment register */
segreg = m_core->sr[address >> 28];
if (transtype == TRANSLATE_FETCH && (segreg & 0x10000000))
@@ -1508,6 +1520,9 @@ void ppc_device::ppccom_execute_tlbl()
vtlb_entry flags;
int entrynum;
+ if (m_flavor == PPC_MODEL_602) // TODO
+ return;
+
/* determine entry number; we use machine().rand() for associativity */
entrynum = ((address >> 12) & 0x1f) | (machine().rand() & 0x20) | (isitlb ? 0x40 : 0);
@@ -1589,6 +1604,23 @@ void ppc_device::ppccom_execute_mfspr()
}
}
+ /* handle 602 SPRs */
+ if (m_flavor == PPC_MODEL_602)
+ { // TODO: Which are read/write only?
+ switch (m_core->param0)
+ {
+ case SPR602_TCR:
+ case SPR602_IBR:
+ case SPR602_ESASRR:
+ case SPR602_SEBR:
+ case SPR602_SER:
+ case SPR602_SP:
+ case SPR602_LT:
+ m_core->param1 = m_core->spr[m_core->param0];
+ return;
+ }
+ }
+
/* handle 603 SPRs */
if (m_cap & PPCCAP_603_MMU)
{
@@ -1715,6 +1747,23 @@ void ppc_device::ppccom_execute_mtspr()
}
}
+ /* handle 602 SPRs */
+ if (m_flavor == PPC_MODEL_602)
+ {
+ switch (m_core->param0)
+ { // TODO: Which are read/write only?
+ case SPR602_TCR:
+ case SPR602_IBR:
+ case SPR602_ESASRR:
+ case SPR602_SEBR:
+ case SPR602_SER:
+ case SPR602_SP:
+ case SPR602_LT:
+ m_core->spr[m_core->param0] = m_core->param1;
+ return;
+ }
+ }
+
/* handle 603 SPRs */
if (m_cap & PPCCAP_603_MMU)
{