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Diffstat (limited to 'src/devices/cpu/mips/mips3.h')
-rw-r--r--src/devices/cpu/mips/mips3.h164
1 files changed, 96 insertions, 68 deletions
diff --git a/src/devices/cpu/mips/mips3.h b/src/devices/cpu/mips/mips3.h
index 6c192b5436c..1b4c5a77f7e 100644
--- a/src/devices/cpu/mips/mips3.h
+++ b/src/devices/cpu/mips/mips3.h
@@ -42,6 +42,7 @@ DECLARE_DEVICE_TYPE(QED5271BE, qed5271be_device)
DECLARE_DEVICE_TYPE(QED5271LE, qed5271le_device)
DECLARE_DEVICE_TYPE(RM7000BE, rm7000be_device)
DECLARE_DEVICE_TYPE(RM7000LE, rm7000le_device)
+DECLARE_DEVICE_TYPE(R5900LE, r5900le_device)
/***************************************************************************
@@ -260,6 +261,7 @@ protected:
MIPS3_TYPE_R5000,
MIPS3_TYPE_VR5500,
MIPS3_TYPE_QED5271,
+ MIPS3_TYPE_R5900,
MIPS3_TYPE_RM7000
};
@@ -309,73 +311,79 @@ private:
struct internal_mips3_state
{
/* core registers */
- uint32_t pc;
- int icount;
- uint64_t r[35];
+ uint32_t pc;
+ int icount;
+ uint64_t r[35];
- /* COP registers */
- uint64_t cpr[3][32];
- uint64_t ccr[3][32];
- uint32_t llbit;
+ /* upper 64 bits of 128-bit GPRs (R5900 only) */
+ uint64_t rh[35];
- uint32_t mode; /* current global mode */
+ /* COP registers */
+ uint64_t cpr[3][32];
+ uint64_t ccr[3][32];
+ uint32_t llbit;
- /* parameters for subroutines */
- uint64_t numcycles; /* return value from gettotalcycles */
- const char * format; /* format string for print_debug */
- uint32_t arg0; /* print_debug argument 1 */
- uint32_t arg1; /* print_debug argument 2 */
+ /* VU0 registers (R5900 only) */
+ float vfr[32][4];
+ uint32_t vcr[32];
- uint64_t count_zero_time;
- uint32_t compare_armed;
- uint32_t jmpdest; /* destination jump target */
+ uint32_t mode; /* current global mode */
+ /* parameters for subroutines */
+ uint64_t numcycles; /* return value from gettotalcycles */
+ const char * format; /* format string for print_debug */
+ uint32_t arg0; /* print_debug argument 1 */
+ uint32_t arg1; /* print_debug argument 2 */
+
+ uint64_t count_zero_time;
+ uint32_t compare_armed;
+ uint32_t jmpdest; /* destination jump target */
};
address_space_config m_program_config;
- mips3_flavor m_flavor;
+ mips3_flavor m_flavor;
/* core state */
internal_mips3_state *m_core;
/* internal stuff */
- uint32_t m_ppc;
- uint32_t m_nextpc;
- uint32_t m_pcbase;
- uint8_t m_cf[4][8];
- bool m_delayslot;
- int m_op;
- int m_interrupt_cycles;
- uint32_t m_ll_value;
- uint64_t m_lld_value;
- uint32_t m_badcop_value;
+ uint32_t m_ppc;
+ uint32_t m_nextpc;
+ uint32_t m_pcbase;
+ uint8_t m_cf[4][8];
+ bool m_delayslot;
+ int m_op;
+ int m_interrupt_cycles;
+ uint32_t m_ll_value;
+ uint64_t m_lld_value;
+ uint32_t m_badcop_value;
/* endian-dependent load/store */
typedef void (mips3_device::*loadstore_func)(uint32_t op);
- loadstore_func m_lwl;
- loadstore_func m_lwr;
- loadstore_func m_swl;
- loadstore_func m_swr;
- loadstore_func m_ldl;
- loadstore_func m_ldr;
- loadstore_func m_sdl;
- loadstore_func m_sdr;
-
- address_space *m_program;
+ loadstore_func m_lwl;
+ loadstore_func m_lwr;
+ loadstore_func m_swl;
+ loadstore_func m_swr;
+ loadstore_func m_ldl;
+ loadstore_func m_ldr;
+ loadstore_func m_sdl;
+ loadstore_func m_sdr;
+
+ address_space * m_program;
std::function<u32 (offs_t)> m_pr32;
std::function<const void * (offs_t)> m_prptr;
- uint32_t c_system_clock;
- uint32_t m_cpu_clock;
+ uint32_t c_system_clock;
+ uint32_t m_cpu_clock;
emu_timer * m_compare_int_timer;
/* derived info based on flavor */
- uint32_t m_pfnmask;
- uint8_t m_tlbentries;
+ uint32_t m_pfnmask;
+ uint8_t m_tlbentries;
/* memory accesses */
- bool m_bigendian;
- uint32_t m_byte_xor;
- uint32_t m_word_xor;
+ bool m_bigendian;
+ uint32_t m_byte_xor;
+ uint32_t m_word_xor;
data_accessors m_memory;
/* cache memory */
@@ -386,35 +394,35 @@ private:
mips3_tlb_entry m_tlb[MIPS3_MAX_TLB_ENTRIES];
/* fast RAM */
- uint32_t m_fastram_select;
+ uint32_t m_fastram_select;
struct
{
- offs_t start; /* start of the RAM block */
- offs_t end; /* end of the RAM block */
- bool readonly; /* true if read-only */
- void * base; /* base in memory where the RAM lives */
- uint8_t * offset_base8; /* base in memory where the RAM lives, 8-bit pointer, with the start offset pre-applied */
- uint16_t * offset_base16; /* base in memory where the RAM lives, 16-bit pointer, with the start offset pre-applied */
- uint32_t * offset_base32; /* base in memory where the RAM lives, 32-bit pointer, with the start offset pre-applied */
- } m_fastram[MIPS3_MAX_FASTRAM];
+ offs_t start; /* start of the RAM block */
+ offs_t end; /* end of the RAM block */
+ bool readonly; /* true if read-only */
+ void * base; /* base in memory where the RAM lives */
+ uint8_t * offset_base8; /* base in memory where the RAM lives, 8-bit pointer, with the start offset pre-applied */
+ uint16_t * offset_base16; /* base in memory where the RAM lives, 16-bit pointer, with the start offset pre-applied */
+ uint32_t * offset_base32; /* base in memory where the RAM lives, 32-bit pointer, with the start offset pre-applied */
+ } m_fastram[MIPS3_MAX_FASTRAM];
- uint32_t m_debugger_temp;
+ uint32_t m_debugger_temp;
/* core state */
- drc_cache m_cache; /* pointer to the DRC code cache */
- std::unique_ptr<drcuml_state> m_drcuml; /* DRC UML generator state */
- std::unique_ptr<mips3_frontend> m_drcfe; /* pointer to the DRC front-end state */
- uint32_t m_drcoptions; /* configurable DRC options */
+ drc_cache m_cache; /* pointer to the DRC code cache */
+ std::unique_ptr<drcuml_state> m_drcuml;/* DRC UML generator state */
+ std::unique_ptr<mips3_frontend> m_drcfe; /* pointer to the DRC front-end state */
+ uint32_t m_drcoptions; /* configurable DRC options */
/* internal stuff */
- uint8_t m_cache_dirty; /* true if we need to flush the cache */
+ uint8_t m_cache_dirty; /* true if we need to flush the cache */
/* tables */
- uint8_t m_fpmode[4]; /* FPU mode table */
+ uint8_t m_fpmode[4]; /* FPU mode table */
/* register mappings */
- uml::parameter m_regmap[34]; /* parameter to register mappings for all 32 integer registers */
- uml::parameter m_regmaplo[34]; /* parameter to register mappings for all 32 integer registers */
+ uml::parameter m_regmap[34]; /* parameter to register mappings for all 32 integer registers */
+ uml::parameter m_regmaplo[34]; /* parameter to register mappings for all 32 integer registers */
/* subroutines */
uml::code_handle * m_entry; /* entry point */
@@ -437,14 +445,14 @@ private:
uml::code_handle * m_exception_norecover[18/*EXCEPTION_COUNT*/]; /* array of no-recover exception handlers */
/* hotspots */
- uint32_t m_hotspot_select;
+ uint32_t m_hotspot_select;
struct
{
- offs_t pc; /* PC to consider */
- uint32_t opcode; /* required opcode at that PC */
- uint32_t cycles; /* number of cycles to eat when hit */
- } m_hotspot[MIPS3_MAX_HOTSPOTS];
- bool m_isdrc;
+ offs_t pc; /* PC to consider */
+ uint32_t opcode; /* required opcode at that PC */
+ uint32_t cycles; /* number of cycles to eat when hit */
+ } m_hotspot[MIPS3_MAX_HOTSPOTS];
+ bool m_isdrc;
void generate_exception(int exception, int backup);
@@ -503,6 +511,9 @@ private:
void handle_special(uint32_t op);
void handle_regimm(uint32_t op);
+ virtual void handle_extra_special(uint32_t op);
+ virtual void handle_extra_regimm(uint32_t op);
+ virtual void handle_idt(uint32_t op);
void lwl_be(uint32_t op);
void lwr_be(uint32_t op);
@@ -722,6 +733,23 @@ public:
{ }
};
+class r5900le_device : public mips3_device
+{
+public:
+ // construction/destruction
+ r5900le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : mips3_device(mconfig, R5900LE, tag, owner, clock, MIPS3_TYPE_R5900, ENDIANNESS_LITTLE)
+ { }
+
+protected:
+ // device_disasm_interface overrides
+ virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
+
+ void handle_extra_special(uint32_t op) override;
+ void handle_extra_regimm(uint32_t op) override;
+ void handle_idt(uint32_t op) override;
+};
+
class qed5271be_device : public mips3_device
{
public: