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Diffstat (limited to 'src/devices/cpu/mb86235/mb86235.cpp')
-rw-r--r--src/devices/cpu/mb86235/mb86235.cpp16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/devices/cpu/mb86235/mb86235.cpp b/src/devices/cpu/mb86235/mb86235.cpp
index eb1baa4565e..f61c7c4fd14 100644
--- a/src/devices/cpu/mb86235/mb86235.cpp
+++ b/src/devices/cpu/mb86235/mb86235.cpp
@@ -11,7 +11,7 @@
* - move post-opcodes outside of the execute_op() function, like increment_prp()
* (needed if opcode uses fifo in/out);
* - rewrite fifo hookups, remove them from the actual opcodes.
- * - use a phase system for the execution, like do_alu() being separated
+ * - use a phase system for the execution, like do_alu() being separated
* from control();
* - illegal delay slots unsupported, and no idea about what is supposed to happen;
* - externalize PDR / DDR (error LED flags on Model 2);
@@ -59,17 +59,17 @@ void mb86235_device::execute_run()
run_drc();
#else
uint64_t opcode;
- while(m_core->icount > 0)
+ while(m_core->icount > 0)
{
uint32_t curpc;
-
+
curpc = check_previous_op_stall() ? m_core->cur_fifo_state.pc : m_core->pc;
debugger_instruction_hook(this, curpc);
opcode = m_direct->read_qword(curpc);
-
+
m_core->ppc = curpc;
-
+
if(m_core->delay_slot == true)
{
m_core->pc = m_core->delay_pc;
@@ -77,9 +77,9 @@ void mb86235_device::execute_run()
}
else
handle_single_step_execution();
-
+
execute_op(opcode >> 32, opcode & 0xffffffff);
-
+
m_core->icount--;
}
@@ -228,7 +228,7 @@ void mb86235_device::device_reset()
#if ENABLE_DRC
flush_cache();
#endif
-
+
m_core->pc = 0;
m_core->delay_pc = 0;
m_core->ppc = 0;