diff options
Diffstat (limited to 'src/devices/cpu/m68000/m68kmake.py')
-rwxr-xr-x | src/devices/cpu/m68000/m68kmake.py | 47 |
1 files changed, 24 insertions, 23 deletions
diff --git a/src/devices/cpu/m68000/m68kmake.py b/src/devices/cpu/m68000/m68kmake.py index 0966be2b1d7..7810fc96044 100755 --- a/src/devices/cpu/m68000/m68kmake.py +++ b/src/devices/cpu/m68000/m68kmake.py @@ -9,15 +9,16 @@ import sys import copy CPU_000 = 0 -CPU_010 = 1 -CPU_020 = 2 -CPU_030 = 3 -CPU_040 = 4 -CPU_FSCPU32 = 5 -CPU_COLDFIRE = 6 -CPU_COUNT = 7 +CPU_070 = 1 +CPU_010 = 2 +CPU_020 = 3 +CPU_030 = 4 +CPU_040 = 5 +CPU_FSCPU32 = 6 +CPU_COLDFIRE = 7 +CPU_COUNT = 8 -cpu_names = '01234fc' +cpu_names = '071234fc' cc_table_up = [ "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ", "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" ] cc_table_dn = [ "t", "f", "hi", "ls", "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", "ge", "lt", "gt", "le" ] @@ -31,19 +32,19 @@ cc_table_dn = [ "t", "f", "hi", "ls", "cc", "cs", "ne", "eq", "vc", "vs", "pl", # # 000 010 020 030 040 FSCPU32 Coldfire ea_cycle_table = { - 'none' : [[ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0]], - 'ai' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], - 'pi' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], - 'pi7' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], - 'pd' : [[ 0, 6, 10], [ 0, 6, 10], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]], - 'pd7' : [[ 0, 6, 10], [ 0, 6, 10], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]], - 'di' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]], - 'ix' : [[ 0, 10, 14], [ 0, 10, 14], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 0, 0]], - 'aw' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], - 'al' : [[ 0, 12, 16], [ 0, 12, 16], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], - 'pcdi' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]], - 'pcix' : [[ 0, 10, 14], [ 0, 10, 14], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 0, 0]], - 'i' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 2, 4], [ 0, 2, 4], [ 0, 2, 4], [ 0, 2, 4], [ 0, 0, 0]], + 'none' : [[ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0], [ 0, 0, 0]], + 'ai' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], + 'pi' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], + 'pi7' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], + 'pd' : [[ 0, 6, 10], [ 0, 6, 10], [ 0, 6, 10], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]], + 'pd7' : [[ 0, 6, 10], [ 0, 6, 10], [ 0, 6, 10], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]], + 'di' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 8, 12], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]], + 'ix' : [[ 0, 10, 14], [ 0, 10, 14], [ 0, 10, 14], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 0, 0]], + 'aw' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 8, 12], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], + 'al' : [[ 0, 12, 16], [ 0, 12, 16], [ 0, 12, 16], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 4, 4], [ 0, 0, 0]], + 'pcdi' : [[ 0, 8, 12], [ 0, 8, 12], [ 0, 8, 12], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 5, 5], [ 0, 0, 0]], + 'pcix' : [[ 0, 10, 14], [ 0, 10, 14], [ 0, 10, 14], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 7, 7], [ 0, 0, 0]], + 'i' : [[ 0, 4, 8], [ 0, 4, 8], [ 0, 4, 8], [ 0, 2, 4], [ 0, 2, 4], [ 0, 2, 4], [ 0, 2, 4], [ 0, 0, 0]], } jmp_jsr_cycle_table = { 'none': 0, 'ai': 4, 'pi': 0, 'pi7': 0, 'pd': 0, 'pd7': 0, 'di': 6, 'ix': 10, 'aw': 6, 'al': 8, 'pcdi': 6, 'pcix': 10, 'i': 0 } @@ -184,7 +185,7 @@ class OpcodeHandler: self.cycles[i] = op.cycles[i] + moves_cycle_table[ea_mode][size_order] elif i == CPU_010 and op.name == 'clr': self.cycles[i] = op.cycles[i] + clr_cycle_table[ea_mode][size_order] - elif i == CPU_000 and (ea_mode == 'i' or ea_mode == 'none') and op.size == 'l' and ((op.cycles[i] == 6 and (op.name == 'add' or op.name == 'and' or op.name == 'or' or op.name == 'sub')) or op.name == 'adda' or op.name == 'suba'): + elif (i == CPU_000 or i == CPU_070) and (ea_mode == 'i' or ea_mode == 'none') and op.size == 'l' and ((op.cycles[i] == 6 and (op.name == 'add' or op.name == 'and' or op.name == 'or' or op.name == 'sub')) or op.name == 'adda' or op.name == 'suba'): self.cycles[i] = op.cycles[i] + ea_cycle_table[ea_mode][i][size_order] + 2 elif i < CPU_020 and (op.name == 'jmp' or op.name == 'jsr'): self.cycles[i] = op.cycles[i] + jmp_jsr_cycle_table[ea_mode] @@ -267,7 +268,7 @@ class Info: for id in order: oh = self.opcode_handlers[id] f.write("\t&m68000_base_device::%s,\n" % oh.function_name) - if oh.function_name == 'm68k_op_illegal_0': + if oh.function_name == 'x4afc_illegal_' + cpu_names: illegal_id = nid nid += 1 f.write("};\n\n") |