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Diffstat (limited to 'src/devices/cpu/m68000/m68k_in.lst')
-rw-r--r--src/devices/cpu/m68000/m68k_in.lst2853
1 files changed, 590 insertions, 2263 deletions
diff --git a/src/devices/cpu/m68000/m68k_in.lst b/src/devices/cpu/m68000/m68k_in.lst
index 3ad215a23ed..e3b43abe77e 100644
--- a/src/devices/cpu/m68000/m68k_in.lst
+++ b/src/devices/cpu/m68000/m68k_in.lst
@@ -1,728 +1,82 @@
-// license:BSD-3-Clause
-// copyright-holders:Karl Stenerud
-/*
- * TODO:
- * - fix callm
- * - fix chk
- * - How does CHK2(byte/word) on address register determine if it's a signed or unsigned compare?
- */
-
-/* ======================================================================== */
-/* ========================= LICENSING & COPYRIGHT ======================== */
-/* ======================================================================== */
-/*
- * MUSASHI
- * Version 4.90
- *
- * A portable Motorola M68xxx processor emulation engine.
- * Copyright Karl Stenerud. All rights reserved.
- *
- */
-
-/* Special thanks to Bart Trzynadlowski for his insight into the
- * undocumented features of this chip:
- *
- * http://dynarec.com/~bart/files/68knotes.txt
- */
-
-
-/* Input file for m68kmake
- * -----------------------
- *
- * All sections begin with 80 X's in a row followed by an end-of-line
- * sequence.
- * After this, m68kmake will expect to find one of the following section
- * identifiers:
- * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
- * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
- * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
- * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
- * M68KMAKE_TABLE_BODY - the table itself
- * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
- * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
- * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
- *
- * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
- * M68KMAKE_TABLE_BODY must be second last in the file.
- *
- * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
- * primitives themselves. Each opcode handler begins with:
- * M68KMAKE_OP(A, B, C, D)
- *
- * where A is the opcode handler name, B is the size of the operation,
- * C denotes any special processing mode, and D denotes a specific
- * addressing mode.
- * For C and D where nothing is specified, use "."
- *
- * Example:
- * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
- * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
- * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
- *
- * All opcode handler primitives end with a closing curly brace "}" at column 1
- *
- * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
- * and do not put a closing curly brace at column 1 unless it is
- * marking the end of the handler!
- *
- * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
- * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
- * opcode handlers to handle variations in the opcode handler.
- * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
- * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
- * be interpreted on instructions where the corresponding table entry
- * specifies multiple effective addressing modes.
- * Example:
- * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
- *
- * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
- * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
- * 68000, 6 cycles for 68010, and 4 cycles for 68020.
- */
-
-XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-M68KMAKE_TABLE
-/*
-The following table is arranged as follows:
-
-name: Opcode mnemonic
-
-size: Operation size
-
-spec proc: Special processing mode:
- .: normal
- s: static operand
- r: register operand
- rr: register to register
- mm: memory to memory
- er: effective address to register
- re: register to effective address
- dd: data register to data register
- da: data register to address register
- aa: address register to address register
- cr: control register to register
- rc: register to control register
- toc: to condition code register
- tos: to status register
- tou: to user stack pointer
- frc: from condition code register
- frs: from status register
- fru: from user stack pointer
- * for move.x, the special processing mode is a specific
- destination effective addressing mode.
-
-spec ea: Specific effective addressing mode:
- .: normal
- i: immediate
- d: data register
- a: address register
- ai: address register indirect
- pi: address register indirect with postincrement
- pd: address register indirect with predecrement
- di: address register indirect with displacement
- ix: address register indirect with index
- aw: absolute word address
- al: absolute long address
- pcdi: program counter relative with displacement
- pcix: program counter relative with index
- a7: register specified in instruction is A7
- ax7: register field X of instruction is A7
- ay7: register field Y of instruction is A7
- axy7: register fields X and Y of instruction are A7
-
-bit pattern: Pattern to recognize this opcode. "." means don't care.
-
-allowed ea: List of allowed addressing modes:
- .: not present
- A: address register indirect
- +: ARI (address register indirect) with postincrement
- -: ARI with predecrement
- D: ARI with displacement
- X: ARI with index
- W: absolute word address
- L: absolute long address
- d: program counter indirect with displacement
- x: program counter indirect with index
- I: immediate
-mode: CPU operating mode for each cpu type. U = user or supervisor,
- S = supervisor only, "." = opcode not present.
-
-cpu cycles: Base number of cycles required to execute this opcode on the
- specified CPU type.
- Use "." if CPU does not have this opcode.
-*/
-
-
- spec spec allowed ea mode 3 C cpu cycles
-name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 2 F 000 010 020 030 040 340 CLF comments
-====== ==== ==== ==== ================ ========== = = = = = = = === === === === === === === ==========
-M68KMAKE_TABLE_START
-1010 0 . . 1010............ .......... U U U U U U U 4 4 4 4 4 4 4
-1111 0 . . 1111............ .......... U U U U U U U 4 4 4 4 4 4 4
-040fpu0 32 . . 11110010........ .......... . . U U U U . . . 0 0 0 0 .
-040fpu1 32 . . 11110011........ .......... . . U U U U . . . 0 0 0 0 .
-abcd 8 rr . 1100...100000... .......... U U U U U U U 6 6 4 4 4 4 4
-abcd 8 mm ax7 1100111100001... .......... U U U U U U U 18 18 16 16 16 16 16
-abcd 8 mm ay7 1100...100001111 .......... U U U U U U U 18 18 16 16 16 16 16
-abcd 8 mm axy7 1100111100001111 .......... U U U U U U U 18 18 16 16 16 16 16
-abcd 8 mm . 1100...100001... .......... U U U U U U U 18 18 16 16 16 16 16
-add 8 er d 1101...000000... .......... U U U U U U U 4 4 2 2 2 2 2
-add 8 er . 1101...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-add 16 er d 1101...001000... .......... U U U U U U U 4 4 2 2 2 2 2
-add 16 er a 1101...001001... .......... U U U U U U U 4 4 2 2 2 2 2
-add 16 er . 1101...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-add 32 er d 1101...010000... .......... U U U U U U U 6 6 2 2 2 2 2
-add 32 er a 1101...010001... .......... U U U U U U U 6 6 2 2 2 2 2
-add 32 er . 1101...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2
-add 8 re . 1101...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-add 16 re . 1101...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-add 32 re . 1101...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-adda 16 . d 1101...011000... .......... U U U U U U U 8 8 2 2 2 2 2
-adda 16 . a 1101...011001... .......... U U U U U U U 8 8 2 2 2 2 2
-adda 16 . . 1101...011...... A+-DXWLdxI U U U U U U U 8 8 2 2 2 2 2
-adda 32 . d 1101...111000... .......... U U U U U U U 6 6 2 2 2 2 2
-adda 32 . a 1101...111001... .......... U U U U U U U 6 6 2 2 2 2 2
-adda 32 . . 1101...111...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2
-addi 8 . d 0000011000000... .......... U U U U U U U 8 8 2 2 2 2 2
-addi 8 . . 0000011000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-addi 16 . d 0000011001000... .......... U U U U U U U 8 8 2 2 2 2 2
-addi 16 . . 0000011001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-addi 32 . d 0000011010000... .......... U U U U U U U 16 14 2 2 2 2 2
-addi 32 . . 0000011010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4
-addq 8 . d 0101...000000... .......... U U U U U U U 4 4 2 2 2 2 2
-addq 8 . . 0101...000...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-addq 16 . d 0101...001000... .......... U U U U U U U 4 4 2 2 2 2 2
-addq 16 . a 0101...001001... .......... U U U U U U U 4 4 2 2 2 2 2
-addq 16 . . 0101...001...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-addq 32 . d 0101...010000... .......... U U U U U U U 8 8 2 2 2 2 2
-addq 32 . a 0101...010001... .......... U U U U U U U 8 8 2 2 2 2 2
-addq 32 . . 0101...010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-addx 8 rr . 1101...100000... .......... U U U U U U U 4 4 2 2 2 2 2
-addx 16 rr . 1101...101000... .......... U U U U U U U 4 4 2 2 2 2 2
-addx 32 rr . 1101...110000... .......... U U U U U U U 8 6 2 2 2 2 2
-addx 8 mm ax7 1101111100001... .......... U U U U U U U 18 18 12 12 12 12 12
-addx 8 mm ay7 1101...100001111 .......... U U U U U U U 18 18 12 12 12 12 12
-addx 8 mm axy7 1101111100001111 .......... U U U U U U U 18 18 12 12 12 12 12
-addx 8 mm . 1101...100001... .......... U U U U U U U 18 18 12 12 12 12 12
-addx 16 mm . 1101...101001... .......... U U U U U U U 18 18 12 12 12 12 12
-addx 32 mm . 1101...110001... .......... U U U U U U U 30 30 12 12 12 12 12
-and 8 er d 1100...000000... .......... U U U U U U U 4 4 2 2 2 2 2
-and 8 er . 1100...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-and 16 er d 1100...001000... .......... U U U U U U U 4 4 2 2 2 2 2
-and 16 er . 1100...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-and 32 er d 1100...010000... .......... U U U U U U U 6 6 2 2 2 2 2
-and 32 er . 1100...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2
-and 8 re . 1100...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-and 16 re . 1100...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-and 32 re . 1100...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-andi 8 toc . 0000001000111100 .......... U U U U U U U 20 16 12 12 12 12 12
-andi 16 tos . 0000001001111100 .......... S S S S S S S 20 16 12 12 12 12 12
-andi 8 . d 0000001000000... .......... U U U U U U U 8 8 2 2 2 2 2
-andi 8 . . 0000001000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-andi 16 . d 0000001001000... .......... U U U U U U U 8 8 2 2 2 2 2
-andi 16 . . 0000001001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-andi 32 . d 0000001010000... .......... U U U U U U U 14 14 2 2 2 2 2
-andi 32 . . 0000001010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4
-asr 8 s . 1110...000000... .......... U U U U U U U 6 6 6 6 6 6 6
-asr 16 s . 1110...001000... .......... U U U U U U U 6 6 6 6 6 6 6
-asr 32 s . 1110...010000... .......... U U U U U U U 8 8 6 6 6 6 6
-asr 8 r . 1110...000100... .......... U U U U U U U 6 6 6 6 6 6 6
-asr 16 r . 1110...001100... .......... U U U U U U U 6 6 6 6 6 6 6
-asr 32 r . 1110...010100... .......... U U U U U U U 8 8 6 6 6 6 6
-asr 16 . . 1110000011...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5
-asl 8 s . 1110...100000... .......... U U U U U U U 6 6 8 8 8 8 8
-asl 16 s . 1110...101000... .......... U U U U U U U 6 6 8 8 8 8 8
-asl 32 s . 1110...110000... .......... U U U U U U U 8 8 8 8 8 8 8
-asl 8 r . 1110...100100... .......... U U U U U U U 6 6 8 8 8 8 8
-asl 16 r . 1110...101100... .......... U U U U U U U 6 6 8 8 8 8 8
-asl 32 r . 1110...110100... .......... U U U U U U U 8 8 8 8 8 8 8
-asl 16 . . 1110000111...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6
-bcc 8 . . 0110............ .......... U U U U U U U 10 10 6 6 6 6 6
-bcc 16 . . 0110....00000000 .......... U U U U U U U 10 10 6 6 6 6 6
-bcc 32 . . 0110....11111111 .......... U U U U U U U 10 10 6 6 6 6 6
-bchg 8 r . 0000...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-bchg 32 r d 0000...101000... .......... U U U U U U U 8 8 4 4 4 4 4
-bchg 8 s . 0000100001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-bchg 32 s d 0000100001000... .......... U U U U U U U 12 12 4 4 4 4 4
-bclr 8 r . 0000...110...... A+-DXWL... U U U U U U U 8 10 4 4 4 4 4
-bclr 32 r d 0000...110000... .......... U U U U U U U 10 10 4 4 4 4 4
-bclr 8 s . 0000100010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-bclr 32 s d 0000100010000... .......... U U U U U U U 14 14 4 4 4 4 4
-bfchg 32 . d 1110101011000... .......... . . U U U U U . . 12 12 12 12 12 timing not quite correct
-bfchg 32 . . 1110101011...... A..DXWL... . . U U U U U . . 20 20 20 20 20
-bfclr 32 . d 1110110011000... .......... . . U U U U U . . 12 12 12 12 12
-bfclr 32 . . 1110110011...... A..DXWL... . . U U U U U . . 20 20 20 20 20
-bfexts 32 . d 1110101111000... .......... . . U U U U U . . 8 8 8 8 8
-bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U U U . . 15 15 15 15 15
-bfextu 32 . d 1110100111000... .......... . . U U U U U . . 8 8 8 8 8
-bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U U U . . 15 15 15 15 15
-bfffo 32 . d 1110110111000... .......... . . U U U U U . . 18 18 18 18 18
-bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U U U . . 28 28 28 28 28
-bfins 32 . d 1110111111000... .......... . . U U U U U . . 10 10 10 10 10
-bfins 32 . . 1110111111...... A..DXWL... . . U U U U U . . 17 17 17 17 17
-bfset 32 . d 1110111011000... .......... . . U U U U U . . 12 12 12 12 12
-bfset 32 . . 1110111011...... A..DXWL... . . U U U U U . . 20 20 20 20 20
-bftst 32 . d 1110100011000... .......... . . U U U U U . . 6 6 6 6 6
-bftst 32 . . 1110100011...... A..DXWLdx. . . U U U U U . . 13 13 13 13 13
-bkpt 0 . . 0100100001001... .......... . U U U U U U . 10 10 10 10 10 10
-bra 8 . . 01100000........ .......... U U U U U U U 10 10 10 10 10 10 10
-bra 16 . . 0110000000000000 .......... U U U U U U U 10 10 10 10 10 10 10
-bra 32 . . 0110000011111111 .......... U U U U U U U 10 10 10 10 10 10 10
-bset 32 r d 0000...111000... .......... U U U U U U U 8 8 4 4 4 4 4
-bset 8 r . 0000...111...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-bset 8 s . 0000100011...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-bset 32 s d 0000100011000... .......... U U U U U U U 12 12 4 4 4 4 4
-bsr 8 . . 01100001........ .......... U U U U U U U 18 18 7 7 7 7 7
-bsr 16 . . 0110000100000000 .......... U U U U U U U 18 18 7 7 7 7 7
-bsr 32 . . 0110000111111111 .......... U U U U U U U 18 18 7 7 7 7 7
-btst 8 r . 0000...100...... A+-DXWLdxI U U U U U U U 4 4 4 4 4 4 4
-btst 32 r d 0000...100000... .......... U U U U U U U 6 6 4 4 4 4 4
-btst 8 s . 0000100000...... A+-DXWLdx. U U U U U U U 8 8 4 4 4 4 4
-btst 32 s d 0000100000000... .......... U U U U U U U 10 10 4 4 4 4 4
-callm 32 . . 0000011011...... A..DXWLdx. . . U U U U U . . 60 60 60 60 60 not properly emulated
-cas 8 . . 0000101011...... A+-DXWL... . . U U U U U . . 12 12 12 12 12
-cas 16 . . 0000110011...... A+-DXWL... . . U U U U U . . 12 12 12 12 12
-cas 32 . . 0000111011...... A+-DXWL... . . U U U U U . . 12 12 12 12 12
-cas2 16 . . 0000110011111100 .......... . . U U U U U . . 12 12 12 12 12
-cas2 32 . . 0000111011111100 .......... . . U U U U U . . 12 12 12 12 12
-chk 16 . d 0100...110000... .......... U U U U U U U 10 8 8 8 8 8 8
-chk 16 . . 0100...110...... A+-DXWLdxI U U U U U U U 10 8 8 8 8 8 8
-chk 32 . d 0100...100000... .......... . . U U U U U . . 8 8 8 8 8
-chk 32 . . 0100...100...... A+-DXWLdxI . . U U U U U . . 8 8 8 8 8
-chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U U U . . 23 23 23 23 23
-chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U U U . . 23 23 23 23 23
-chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U U U . . 18 18 18 18 18
-chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U U U . . 23 23 23 23 23
-chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U U U . . 23 23 23 23 23
-chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U U U . . 18 18 18 18 18
-chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U U U . . 23 23 23 23 23
-chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U U U . . 23 23 23 23 23
-chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U U U . . 18 18 18 18 18
-clr 8 . d 0100001000000... .......... U U U U U U U 4 4 2 2 2 2 2
-clr 8 . . 0100001000...... A+-DXWL... U U U U U U U 8 4 4 4 4 4 4
-clr 16 . d 0100001001000... .......... U U U U U U U 4 4 2 2 2 2 2
-clr 16 . . 0100001001...... A+-DXWL... U U U U U U U 8 4 4 4 4 4 4
-clr 32 . d 0100001010000... .......... U U U U U U U 6 6 2 2 2 2 2
-clr 32 . . 0100001010...... A+-DXWL... U U U U U U U 12 6 4 4 4 4 4
-cmp 8 . d 1011...000000... .......... U U U U U U U 4 4 2 2 2 2 2
-cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-cmp 16 . d 1011...001000... .......... U U U U U U U 4 4 2 2 2 2 2
-cmp 16 . a 1011...001001... .......... U U U U U U U 4 4 2 2 2 2 2
-cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-cmp 32 . d 1011...010000... .......... U U U U U U U 6 6 2 2 2 2 2
-cmp 32 . a 1011...010001... .......... U U U U U U U 6 6 2 2 2 2 2
-cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2
-cmpa 16 . d 1011...011000... .......... U U U U U U U 6 6 4 4 4 4 4
-cmpa 16 . a 1011...011001... .......... U U U U U U U 6 6 4 4 4 4 4
-cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U U U 6 6 4 4 4 4 4
-cmpa 32 . d 1011...111000... .......... U U U U U U U 6 6 4 4 4 4 4
-cmpa 32 . a 1011...111001... .......... U U U U U U U 6 6 4 4 4 4 4
-cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U U U 6 6 4 4 4 4 4
-cmpi 8 . d 0000110000000... .......... U U U U U U U 8 8 2 2 2 2 2
-cmpi 8 . . 0000110000...... A+-DXWL... U U U U U U U 8 8 2 2 2 2 2
-cmpi 8 . pcdi 0000110000111010 .......... . . U U U U U . . 7 7 7 7 7
-cmpi 8 . pcix 0000110000111011 .......... . . U U U U U . . 9 9 9 9 9
-cmpi 16 . d 0000110001000... .......... U U U U U U U 8 8 2 2 2 2 2
-cmpi 16 . . 0000110001...... A+-DXWL... U U U U U U U 8 8 2 2 2 2 2
-cmpi 16 . pcdi 0000110001111010 .......... . . U U U U U . . 7 7 7 7 7
-cmpi 16 . pcix 0000110001111011 .......... . . U U U U U . . 9 9 9 9 9
-cmpi 32 . d 0000110010000... .......... U U U U U U U 14 12 2 2 2 2 2
-cmpi 32 . . 0000110010...... A+-DXWL... U U U U U U U 12 12 2 2 2 2 2
-cmpi 32 . pcdi 0000110010111010 .......... . . U U U U U . . 7 7 7 7 7
-cmpi 32 . pcix 0000110010111011 .......... . . U U U U U . . 9 9 9 9 9
-cmpm 8 . ax7 1011111100001... .......... U U U U U U U 12 12 9 9 9 9 9
-cmpm 8 . ay7 1011...100001111 .......... U U U U U U U 12 12 9 9 9 9 9
-cmpm 8 . axy7 1011111100001111 .......... U U U U U U U 12 12 9 9 9 9 9
-cmpm 8 . . 1011...100001... .......... U U U U U U U 12 12 9 9 9 9 9
-cmpm 16 . . 1011...101001... .......... U U U U U U U 12 12 9 9 9 9 9
-cmpm 32 . . 1011...110001... .......... U U U U U U U 20 20 9 9 9 9 9
-cinv 32 . . 11110100..0..... .......... . . . . U . . . . . . 16 . . 040 only
-cpush 32 . . 11110100..1..... .......... . . . . U . . . . . . 16 . . 040 only
-cpbcc 32 . . 1111...01....... .......... . . U U . . U . . 4 4 . . . cpXXX only for 020/030, not on 040!
-cpdbcc 32 . . 1111...001001... .......... . . U U . . U . . 4 4 . . .
-cpgen 32 . . 1111...000...... .......... . . U U . . U . . 4 4 . . .
-cpscc 32 . . 1111...001...... .......... . . U U . . U . . 4 4 . . .
-cptrapcc 32 . . 1111...001111... .......... . . U U . . U . . 4 4 . . .
-ftrapcc 32 . . 1111001001111... .......... . . U U . . U . . 4 4 . . .
-dbt 16 . . 0101000011001... .......... U U U U U U U 12 12 6 6 6 6 6
-dbf 16 . . 0101000111001... .......... U U U U U U U 12 12 6 4 4 4 4
-dbcc 16 . . 0101....11001... .......... U U U U U U U 12 12 6 6 6 6 6
-divs 16 . d 1000...111000... .......... U U U U U U U 158 122 56 56 56 56 56
-divs 16 . . 1000...111...... A+-DXWLdxI U U U U U U U 158 122 56 56 56 56 56
-divu 16 . d 1000...011000... .......... U U U U U U U 140 108 44 44 44 44 44
-divu 16 . . 1000...011...... A+-DXWLdxI U U U U U U U 140 108 44 44 44 44 44
-divl 32 . d 0100110001000... .......... . . U U U U U . . 84 84 84 84 84
-divl 32 . . 0100110001...... A+-DXWLdxI . . U U U U U . . 84 84 84 84 84
-eor 8 . d 1011...100000... .......... U U U U U U U 4 4 2 2 2 2 2
-eor 8 . . 1011...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-eor 16 . d 1011...101000... .......... U U U U U U U 4 4 2 2 2 2 2
-eor 16 . . 1011...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-eor 32 . d 1011...110000... .......... U U U U U U U 8 6 2 2 2 2 2
-eor 32 . . 1011...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-eori 8 toc . 0000101000111100 .......... U U U U U U U 20 16 12 12 12 12 12
-eori 16 tos . 0000101001111100 .......... S S S S S S S 20 16 12 12 12 12 12
-eori 8 . d 0000101000000... .......... U U U U U U U 8 8 2 2 2 2 2
-eori 8 . . 0000101000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-eori 16 . d 0000101001000... .......... U U U U U U U 8 8 2 2 2 2 2
-eori 16 . . 0000101001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-eori 32 . d 0000101010000... .......... U U U U U U U 16 14 2 2 2 2 2
-eori 32 . . 0000101010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4
-exg 32 dd . 1100...101000... .......... U U U U U U U 6 6 2 2 2 2 2
-exg 32 aa . 1100...101001... .......... U U U U U U U 6 6 2 2 2 2 2
-exg 32 da . 1100...110001... .......... U U U U U U U 6 6 2 2 2 2 2
-ext 16 . . 0100100010000... .......... U U U U U U U 4 4 4 4 4 4 4
-ext 32 . . 0100100011000... .......... U U U U U U U 4 4 4 4 4 4 4
-extb 32 . . 0100100111000... .......... . . U U U U U . . 4 4 4 4 4
-illegal 0 . . 0100101011111100 .......... U U U U U U U 4 4 4 4 4 4 4
-jmp 32 . . 0100111011...... A..DXWLdx. U U U U U U U 4 4 0 0 0 0 0
-jsr 32 . . 0100111010...... A..DXWLdx. U U U U U U U 12 12 0 0 0 0 0
-lea 32 . . 0100...111...... A..DXWLdx. U U U U U U U 0 0 2 2 2 2 2
-link 16 . a7 0100111001010111 .......... U U U U U U U 16 16 5 5 5 5 5
-link 16 . . 0100111001010... .......... U U U U U U U 16 16 5 5 5 5 5
-link 32 . a7 0100100000001111 .......... . . U U U U U . . 6 6 6 6 6
-link 32 . . 0100100000001... .......... . . U U U U U . . 6 6 6 6 6
-lsr 8 s . 1110...000001... .......... U U U U U U U 6 6 4 4 4 4 4
-lsr 16 s . 1110...001001... .......... U U U U U U U 6 6 4 4 4 4 4
-lsr 32 s . 1110...010001... .......... U U U U U U U 8 8 4 4 4 4 4
-lsr 8 r . 1110...000101... .......... U U U U U U U 6 6 6 6 6 6 6
-lsr 16 r . 1110...001101... .......... U U U U U U U 6 6 6 6 6 6 6
-lsr 32 r . 1110...010101... .......... U U U U U U U 8 8 6 6 6 6 6
-lsr 16 . . 1110001011...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5
-lsl 8 s . 1110...100001... .......... U U U U U U U 6 6 4 4 4 4 4
-lsl 16 s . 1110...101001... .......... U U U U U U U 6 6 4 4 4 4 4
-lsl 32 s . 1110...110001... .......... U U U U U U U 8 8 4 4 4 4 4
-lsl 8 r . 1110...100101... .......... U U U U U U U 6 6 6 6 6 6 6
-lsl 16 r . 1110...101101... .......... U U U U U U U 6 6 6 6 6 6 6
-lsl 32 r . 1110...110101... .......... U U U U U U U 8 8 6 6 6 6 6
-lsl 16 . . 1110001111...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5
-move 8 d d 0001...000000... .......... U U U U U U U 4 4 2 2 2 2 2
-move 8 d . 0001...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-move 8 ai d 0001...010000... .......... U U U U U U U 8 8 4 4 4 4 4
-move 8 ai . 0001...010...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4
-move 8 pi d 0001...011000... .......... U U U U U U U 8 8 4 4 4 4 4
-move 8 pi . 0001...011...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4
-move 8 pi7 d 0001111011000... .......... U U U U U U U 8 8 4 4 4 4 4
-move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4
-move 8 pd d 0001...100000... .......... U U U U U U U 8 8 5 5 5 5 5
-move 8 pd . 0001...100...... A+-DXWLdxI U U U U U U U 8 8 5 5 5 5 5
-move 8 pd7 d 0001111100000... .......... U U U U U U U 8 8 5 5 5 5 5
-move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U U U 8 8 5 5 5 5 5
-move 8 di d 0001...101000... .......... U U U U U U U 12 12 5 5 5 5 5
-move 8 di . 0001...101...... A+-DXWLdxI U U U U U U U 12 12 5 5 5 5 5
-move 8 ix d 0001...110000... .......... U U U U U U U 14 14 7 7 7 7 7
-move 8 ix . 0001...110...... A+-DXWLdxI U U U U U U U 14 14 7 7 7 7 7
-move 8 aw d 0001000111000... .......... U U U U U U U 12 12 4 4 4 4 4
-move 8 aw . 0001000111...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4
-move 8 al d 0001001111000... .......... U U U U U U U 16 16 6 6 6 6 6
-move 8 al . 0001001111...... A+-DXWLdxI U U U U U U U 16 16 6 6 6 6 6
-move 16 d d 0011...000000... .......... U U U U U U U 4 4 2 2 2 2 2
-move 16 d a 0011...000001... .......... U U U U U U U 4 4 2 2 2 2 2
-move 16 d . 0011...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-move 16 ai d 0011...010000... .......... U U U U U U U 8 8 4 4 4 4 4
-move 16 ai a 0011...010001... .......... U U U U U U U 8 8 4 4 4 4 4
-move 16 ai . 0011...010...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4
-move 16 pi d 0011...011000... .......... U U U U U U U 8 8 4 4 4 4 4
-move 16 pi a 0011...011001... .......... U U U U U U U 8 8 4 4 4 4 4
-move 16 pi . 0011...011...... A+-DXWLdxI U U U U U U U 8 8 4 4 4 4 4
-move 16 pd d 0011...100000... .......... U U U U U U U 8 8 5 5 5 5 5
-move 16 pd a 0011...100001... .......... U U U U U U U 8 8 5 5 5 5 5
-move 16 pd . 0011...100...... A+-DXWLdxI U U U U U U U 8 8 5 5 5 5 5
-move 16 di d 0011...101000... .......... U U U U U U U 12 12 5 5 5 5 5
-move 16 di a 0011...101001... .......... U U U U U U U 12 12 5 5 5 5 5
-move 16 di . 0011...101...... A+-DXWLdxI U U U U U U U 12 12 5 5 5 5 5
-move 16 ix d 0011...110000... .......... U U U U U U U 14 14 7 7 7 7 7
-move 16 ix a 0011...110001... .......... U U U U U U U 14 14 7 7 7 7 7
-move 16 ix . 0011...110...... A+-DXWLdxI U U U U U U U 14 14 7 7 7 7 7
-move 16 aw d 0011000111000... .......... U U U U U U U 12 12 4 4 4 4 4
-move 16 aw a 0011000111001... .......... U U U U U U U 12 12 4 4 4 4 4
-move 16 aw . 0011000111...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4
-move 16 al d 0011001111000... .......... U U U U U U U 16 16 6 6 6 6 6
-move 16 al a 0011001111001... .......... U U U U U U U 16 16 6 6 6 6 6
-move 16 al . 0011001111...... A+-DXWLdxI U U U U U U U 16 16 6 6 6 6 6
-move 32 d d 0010...000000... .......... U U U U U U U 4 4 2 2 2 2 2
-move 32 d a 0010...000001... .......... U U U U U U U 4 4 2 2 2 2 2
-move 32 d . 0010...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-move 32 ai d 0010...010000... .......... U U U U U U U 12 12 4 4 4 4 4
-move 32 ai a 0010...010001... .......... U U U U U U U 12 12 4 4 4 4 4
-move 32 ai . 0010...010...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4
-move 32 pi d 0010...011000... .......... U U U U U U U 12 12 4 4 4 4 4
-move 32 pi a 0010...011001... .......... U U U U U U U 12 12 4 4 4 4 4
-move 32 pi . 0010...011...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4
-move 32 pd d 0010...100000... .......... U U U U U U U 12 14 5 5 5 5 5
-move 32 pd a 0010...100001... .......... U U U U U U U 12 14 5 5 5 5 5
-move 32 pd . 0010...100...... A+-DXWLdxI U U U U U U U 12 14 5 5 5 5 5
-move 32 di d 0010...101000... .......... U U U U U U U 16 16 5 5 5 5 5
-move 32 di a 0010...101001... .......... U U U U U U U 16 16 5 5 5 5 5
-move 32 di . 0010...101...... A+-DXWLdxI U U U U U U U 16 16 5 5 5 5 5
-move 32 ix d 0010...110000... .......... U U U U U U U 18 18 7 7 7 7 7
-move 32 ix a 0010...110001... .......... U U U U U U U 18 18 7 7 7 7 7
-move 32 ix . 0010...110...... A+-DXWLdxI U U U U U U U 18 18 7 7 7 7 7
-move 32 aw d 0010000111000... .......... U U U U U U U 16 16 4 4 4 4 4
-move 32 aw a 0010000111001... .......... U U U U U U U 16 16 4 4 4 4 4
-move 32 aw . 0010000111...... A+-DXWLdxI U U U U U U U 16 16 4 4 4 4 4
-move 32 al d 0010001111000... .......... U U U U U U U 20 20 6 6 6 6 6
-move 32 al a 0010001111001... .......... U U U U U U U 20 20 6 6 6 6 6
-move 32 al . 0010001111...... A+-DXWLdxI U U U U U U U 20 20 6 6 6 6 6
-movea 16 . d 0011...001000... .......... U U U U U U U 4 4 2 2 2 2 2
-movea 16 . a 0011...001001... .......... U U U U U U U 4 4 2 2 2 2 2
-movea 16 . . 0011...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-movea 32 . d 0010...001000... .......... U U U U U U U 4 4 2 2 2 2 2
-movea 32 . a 0010...001001... .......... U U U U U U U 4 4 2 2 2 2 2
-movea 32 . . 0010...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-move 16 frc d 0100001011000... .......... . U U U U U U . 4 4 4 4 4 4
-move 16 frc . 0100001011...... A+-DXWL... . U U U U U U . 8 4 4 4 4 4
-move 16 toc d 0100010011000... .......... U U U U U U U 12 12 4 4 4 4 4
-move 16 toc . 0100010011...... A+-DXWLdxI U U U U U U U 12 12 4 4 4 4 4
-move 16 frs d 0100000011000... .......... U S S S S S S 6 4 8 8 8 8 8 U only for 000
-move 16 frs . 0100000011...... A+-DXWL... U S S S S S S 8 8 8 8 8 8 8 U only for 000
-move 16 tos d 0100011011000... .......... S S S S S S S 12 12 8 8 8 8 8
-move 16 tos . 0100011011...... A+-DXWLdxI S S S S S S S 12 12 8 8 8 8 8
-move 32 fru . 0100111001101... .......... S S S S S S S 4 6 2 2 2 2 2
-move 32 tou . 0100111001100... .......... S S S S S S S 4 6 2 2 2 2 2
-movec 32 cr . 0100111001111010 .......... . S S S S S S . 12 6 6 6 6 6
-movec 32 rc . 0100111001111011 .......... . S S S S S S . 10 12 12 12 12 12
-movem 16 re pd 0100100010100... .......... U U U U U U U 8 8 4 4 4 4 4
-movem 16 re . 0100100010...... A..DXWL... U U U U U U U 8 8 4 4 4 4 4
-movem 32 re pd 0100100011100... .......... U U U U U U U 8 8 4 4 4 4 4
-movem 32 re . 0100100011...... A..DXWL... U U U U U U U 8 8 4 4 4 4 4
-movem 16 er pi 0100110010011... .......... U U U U U U U 12 12 8 8 8 8 8
-movem 16 er pcdi 0100110010111010 .......... U U U U U U U 16 16 9 9 9 9 9
-movem 16 er pcix 0100110010111011 .......... U U U U U U U 18 18 11 11 11 11 11
-movem 16 er . 0100110010...... A..DXWL... U U U U U U U 12 12 8 8 8 8 8
-movem 32 er pi 0100110011011... .......... U U U U U U U 12 12 8 8 8 8 8
-movem 32 er pcdi 0100110011111010 .......... U U U U U U U 16 16 9 9 9 9 9
-movem 32 er pcix 0100110011111011 .......... U U U U U U U 18 18 11 11 11 11 11
-movem 32 er . 0100110011...... A..DXWL... U U U U U U U 12 12 8 8 8 8 8
-movep 16 er . 0000...100001... .......... U U U U U U U 16 16 12 12 12 12 12
-movep 32 er . 0000...101001... .......... U U U U U U U 24 24 18 18 18 18 18
-movep 16 re . 0000...110001... .......... U U U U U U U 16 16 11 11 11 11 11
-movep 32 re . 0000...111001... .......... U U U U U U U 24 24 17 17 17 17 17
-moveq 32 . . 0111...0........ .......... U U U U U U U 4 4 2 2 2 2 2
-moves 8 . . 0000111000...... A+-DXWL... . S S S S S S . 14 5 5 5 5 5
-moves 16 . . 0000111001...... A+-DXWL... . S S S S S S . 14 5 5 5 5 5
-moves 32 . . 0000111010...... A+-DXWL... . S S S S S S . 16 5 5 5 5 5
-move16 32 . . 1111011000100... .......... . . . . U U . . . . . 4 4 4 TODO: correct timing
-muls 16 . d 1100...111000... .......... U U U U U U U 54 32 27 27 27 27 27
-muls 16 . . 1100...111...... A+-DXWLdxI U U U U U U U 54 32 27 27 27 27 27
-mulu 16 . d 1100...011000... .......... U U U U U U U 54 30 27 27 27 27 27
-mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U U U 54 30 27 27 27 27 27
-mull 32 . d 0100110000000... .......... . . U U U U U . . 43 43 43 43 43
-mull 32 . . 0100110000...... A+-DXWLdxI . . U U U U U . . 43 43 43 43 43
-nbcd 8 . d 0100100000000... .......... U U U U U U U 6 6 6 6 6 6 6
-nbcd 8 . . 0100100000...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6
-neg 8 . d 0100010000000... .......... U U U U U U U 4 4 2 2 2 2 2
-neg 8 . . 0100010000...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-neg 16 . d 0100010001000... .......... U U U U U U U 4 4 2 2 2 2 2
-neg 16 . . 0100010001...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-neg 32 . d 0100010010000... .......... U U U U U U U 6 6 2 2 2 2 2
-neg 32 . . 0100010010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-negx 8 . d 0100000000000... .......... U U U U U U U 4 4 2 2 2 2 2
-negx 8 . . 0100000000...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-negx 16 . d 0100000001000... .......... U U U U U U U 4 4 2 2 2 2 2
-negx 16 . . 0100000001...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-negx 32 . d 0100000010000... .......... U U U U U U U 6 6 2 2 2 2 2
-negx 32 . . 0100000010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-nop 0 . . 0100111001110001 .......... U U U U U U U 4 4 2 2 2 2 2
-not 8 . d 0100011000000... .......... U U U U U U U 4 4 2 2 2 2 2
-not 8 . . 0100011000...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-not 16 . d 0100011001000... .......... U U U U U U U 4 4 2 2 2 2 2
-not 16 . . 0100011001...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-not 32 . d 0100011010000... .......... U U U U U U U 6 6 2 2 2 2 2
-not 32 . . 0100011010...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-or 8 er d 1000...000000... .......... U U U U U U U 4 4 2 2 2 2 2
-or 8 er . 1000...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-or 16 er d 1000...001000... .......... U U U U U U U 4 4 2 2 2 2 2
-or 16 er . 1000...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-or 32 er d 1000...010000... .......... U U U U U U U 6 6 2 2 2 2 2
-or 32 er . 1000...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2
-or 8 re . 1000...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-or 16 re . 1000...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-or 32 re . 1000...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-ori 8 toc . 0000000000111100 .......... U U U U U U U 20 16 12 12 12 12 12
-ori 16 tos . 0000000001111100 .......... S S S S S S S 20 16 12 12 12 12 12
-ori 8 . d 0000000000000... .......... U U U U U U U 8 8 2 2 2 2 2
-ori 8 . . 0000000000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-ori 16 . d 0000000001000... .......... U U U U U U U 8 8 2 2 2 2 2
-ori 16 . . 0000000001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-ori 32 . d 0000000010000... .......... U U U U U U U 16 14 2 2 2 2 2
-ori 32 . . 0000000010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4
-pack 16 rr . 1000...101000... .......... . . U U U U U . . 6 6 6 6 6
-pack 16 mm ax7 1000111101001... .......... . . U U U U U . . 13 13 13 13 13
-pack 16 mm ay7 1000...101001111 .......... . . U U U U U . . 13 13 13 13 13
-pack 16 mm axy7 1000111101001111 .......... . . U U U U U . . 13 13 13 13 13
-pack 16 mm . 1000...101001... .......... . . U U U U U . . 13 13 13 13 13
-pea 32 . . 0100100001...... A..DXWLdx. U U U U U U U 6 6 5 5 5 5 5
-pflusha 32 . . 1111010100011... .......... . . . . S S . . . . . 4 4 4 TODO: correct timing
-pflushan 32 . . 1111010100010... .......... . . . . S S . . . . . 4 4 4 TODO: correct timing
-pmmu 32 . . 1111000......... .......... . . S S S S S . . 8 8 8 8 8
-ptest 32 . . 1111010101.01... .......... . . . . S . . . . . . 8 . .
-reset 0 . . 0100111001110000 .......... S S S S S S S 0 0 0 0 0 0 0
-ror 8 s . 1110...000011... .......... U U U U U U U 6 6 8 8 8 8 8
-ror 16 s . 1110...001011... .......... U U U U U U U 6 6 8 8 8 8 8
-ror 32 s . 1110...010011... .......... U U U U U U U 8 8 8 8 8 8 8
-ror 8 r . 1110...000111... .......... U U U U U U U 6 6 8 8 8 8 8
-ror 16 r . 1110...001111... .......... U U U U U U U 6 6 8 8 8 8 8
-ror 32 r . 1110...010111... .......... U U U U U U U 8 8 8 8 8 8 8
-ror 16 . . 1110011011...... A+-DXWL... U U U U U U U 8 8 7 7 7 7 7
-rol 8 s . 1110...100011... .......... U U U U U U U 6 6 8 8 8 8 8
-rol 16 s . 1110...101011... .......... U U U U U U U 6 6 8 8 8 8 8
-rol 32 s . 1110...110011... .......... U U U U U U U 8 8 8 8 8 8 8
-rol 8 r . 1110...100111... .......... U U U U U U U 6 6 8 8 8 8 8
-rol 16 r . 1110...101111... .......... U U U U U U U 6 6 8 8 8 8 8
-rol 32 r . 1110...110111... .......... U U U U U U U 8 8 8 8 8 8 8
-rol 16 . . 1110011111...... A+-DXWL... U U U U U U U 8 8 7 7 7 7 7
-roxr 8 s . 1110...000010... .......... U U U U U U U 6 6 12 12 12 12 12
-roxr 16 s . 1110...001010... .......... U U U U U U U 6 6 12 12 12 12 12
-roxr 32 s . 1110...010010... .......... U U U U U U U 8 8 12 12 12 12 12
-roxr 8 r . 1110...000110... .......... U U U U U U U 6 6 12 12 12 12 12
-roxr 16 r . 1110...001110... .......... U U U U U U U 6 6 12 12 12 12 12
-roxr 32 r . 1110...010110... .......... U U U U U U U 8 8 12 12 12 12 12
-roxr 16 . . 1110010011...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5
-roxl 8 s . 1110...100010... .......... U U U U U U U 6 6 12 12 12 12 12
-roxl 16 s . 1110...101010... .......... U U U U U U U 6 6 12 12 12 12 12
-roxl 32 s . 1110...110010... .......... U U U U U U U 8 8 12 12 12 12 12
-roxl 8 r . 1110...100110... .......... U U U U U U U 6 6 12 12 12 12 12
-roxl 16 r . 1110...101110... .......... U U U U U U U 6 6 12 12 12 12 12
-roxl 32 r . 1110...110110... .......... U U U U U U U 8 8 12 12 12 12 12
-roxl 16 . . 1110010111...... A+-DXWL... U U U U U U U 8 8 5 5 5 5 5
-rtd 32 . . 0100111001110100 .......... . U U U U U U . 16 10 10 10 10 10
-rte 32 . . 0100111001110011 .......... S S S S S S S 20 24 20 20 20 20 20 bus fault not emulated
-rtm 32 . . 000001101100.... .......... . . U U U U U . . 19 19 19 19 19 not properly emulated
-rtr 32 . . 0100111001110111 .......... U U U U U U U 20 20 14 14 14 14 14
-rts 32 . . 0100111001110101 .......... U U U U U U U 16 16 10 10 10 10 10
-sbcd 8 rr . 1000...100000... .......... U U U U U U U 6 6 4 4 4 4 4
-sbcd 8 mm ax7 1000111100001... .......... U U U U U U U 18 18 16 16 16 16 16
-sbcd 8 mm ay7 1000...100001111 .......... U U U U U U U 18 18 16 16 16 16 16
-sbcd 8 mm axy7 1000111100001111 .......... U U U U U U U 18 18 16 16 16 16 16
-sbcd 8 mm . 1000...100001... .......... U U U U U U U 18 18 16 16 16 16 16
-st 8 . d 0101000011000... .......... U U U U U U U 6 4 4 4 4 4 4
-st 8 . . 0101000011...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6
-sf 8 . d 0101000111000... .......... U U U U U U U 4 4 4 4 4 4 4
-sf 8 . . 0101000111...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6
-scc 8 . d 0101....11000... .......... U U U U U U U 4 4 4 4 4 4 4
-scc 8 . . 0101....11...... A+-DXWL... U U U U U U U 8 8 6 6 6 6 6
-stop 0 . . 0100111001110010 .......... S S S S S S S 4 4 8 8 8 8 8
-sub 8 er d 1001...000000... .......... U U U U U U U 4 4 2 2 2 2 2
-sub 8 er . 1001...000...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-sub 16 er d 1001...001000... .......... U U U U U U U 4 4 2 2 2 2 2
-sub 16 er a 1001...001001... .......... U U U U U U U 4 4 2 2 2 2 2
-sub 16 er . 1001...001...... A+-DXWLdxI U U U U U U U 4 4 2 2 2 2 2
-sub 32 er d 1001...010000... .......... U U U U U U U 6 6 2 2 2 2 2
-sub 32 er a 1001...010001... .......... U U U U U U U 6 6 2 2 2 2 2
-sub 32 er . 1001...010...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2
-sub 8 re . 1001...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-sub 16 re . 1001...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-sub 32 re . 1001...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-suba 16 . d 1001...011000... .......... U U U U U U U 8 8 2 2 2 2 2
-suba 16 . a 1001...011001... .......... U U U U U U U 8 8 2 2 2 2 2
-suba 16 . . 1001...011...... A+-DXWLdxI U U U U U U U 8 8 2 2 2 2 2
-suba 32 . d 1001...111000... .......... U U U U U U U 6 6 2 2 2 2 2
-suba 32 . a 1001...111001... .......... U U U U U U U 6 6 2 2 2 2 2
-suba 32 . . 1001...111...... A+-DXWLdxI U U U U U U U 6 6 2 2 2 2 2
-subi 8 . d 0000010000000... .......... U U U U U U U 8 8 2 2 2 2 2
-subi 8 . . 0000010000...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-subi 16 . d 0000010001000... .......... U U U U U U U 8 8 2 2 2 2 2
-subi 16 . . 0000010001...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-subi 32 . d 0000010010000... .......... U U U U U U U 16 14 2 2 2 2 2
-subi 32 . . 0000010010...... A+-DXWL... U U U U U U U 20 20 4 4 4 4 4
-subq 8 . d 0101...100000... .......... U U U U U U U 4 4 2 2 2 2 2
-subq 8 . . 0101...100...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-subq 16 . d 0101...101000... .......... U U U U U U U 4 4 2 2 2 2 2
-subq 16 . a 0101...101001... .......... U U U U U U U 8 4 2 2 2 2 2
-subq 16 . . 0101...101...... A+-DXWL... U U U U U U U 8 8 4 4 4 4 4
-subq 32 . d 0101...110000... .......... U U U U U U U 8 8 2 2 2 2 2
-subq 32 . a 0101...110001... .......... U U U U U U U 8 8 2 2 2 2 2
-subq 32 . . 0101...110...... A+-DXWL... U U U U U U U 12 12 4 4 4 4 4
-subx 8 rr . 1001...100000... .......... U U U U U U U 4 4 2 2 2 2 2
-subx 16 rr . 1001...101000... .......... U U U U U U U 4 4 2 2 2 2 2
-subx 32 rr . 1001...110000... .......... U U U U U U U 8 6 2 2 2 2 2
-subx 8 mm ax7 1001111100001... .......... U U U U U U U 18 18 12 12 12 12 12
-subx 8 mm ay7 1001...100001111 .......... U U U U U U U 18 18 12 12 12 12 12
-subx 8 mm axy7 1001111100001111 .......... U U U U U U U 18 18 12 12 12 12 12
-subx 8 mm . 1001...100001... .......... U U U U U U U 18 18 12 12 12 12 12
-subx 16 mm . 1001...101001... .......... U U U U U U U 18 18 12 12 12 12 12
-subx 32 mm . 1001...110001... .......... U U U U U U U 30 30 12 12 12 12 12
-swap 32 . . 0100100001000... .......... U U U U U U U 4 4 4 4 4 4 4
-tas 8 . d 0100101011000... .......... U U U U U U U 4 4 4 4 4 4 4
-tas 8 . . 0100101011...... A+-DXWL... U U U U U U U 14 14 12 12 12 12 12
-trap 0 . . 010011100100.... .......... U U U U U U U 4 4 4 4 4 4 4
-trapt 0 . . 0101000011111100 .......... . . U U U U U . . 4 4 4 4 4
-trapt 16 . . 0101000011111010 .......... . . U U U U U . . 6 6 6 6 6
-trapt 32 . . 0101000011111011 .......... . . U U U U U . . 8 8 8 8 8
-trapf 0 . . 0101000111111100 .......... . . U U U U U . . 4 4 4 4 4
-trapf 16 . . 0101000111111010 .......... . . U U U U U . . 6 6 6 6 6
-trapf 32 . . 0101000111111011 .......... . . U U U U U . . 8 8 8 8 8
-trapcc 0 . . 0101....11111100 .......... . . U U U U U . . 4 4 4 4 4
-trapcc 16 . . 0101....11111010 .......... . . U U U U U . . 6 6 6 6 6
-trapcc 32 . . 0101....11111011 .......... . . U U U U U . . 8 8 8 8 8
-trapv 0 . . 0100111001110110 .......... U U U U U U U 4 4 4 4 4 4 4
-tst 8 . d 0100101000000... .......... U U U U U U U 4 4 2 2 2 2 2
-tst 8 . . 0100101000...... A+-DXWL... U U U U U U U 4 4 2 2 2 2 2
-tst 8 . pcdi 0100101000111010 .......... . . U U U U U . . 7 7 7 7 7
-tst 8 . pcix 0100101000111011 .......... . . U U U U U . . 9 9 9 9 9
-tst 8 . i 0100101000111100 .......... . . U U U U U . . 6 6 6 6 6
-tst 16 . d 0100101001000... .......... U U U U U U U 4 4 2 2 2 2 2
-tst 16 . a 0100101001001... .......... . . U U U U U . . 2 2 2 2 2
-tst 16 . . 0100101001...... A+-DXWL... U U U U U U U 4 4 2 2 2 2 2
-tst 16 . pcdi 0100101001111010 .......... . . U U U U U . . 7 7 7 7 7
-tst 16 . pcix 0100101001111011 .......... . . U U U U U . . 9 9 9 9 9
-tst 16 . i 0100101001111100 .......... . . U U U U U . . 6 6 6 6 6
-tst 32 . d 0100101010000... .......... U U U U U U U 4 4 2 2 2 2 2
-tst 32 . a 0100101010001... .......... . . U U U U U . . 2 2 2 2 2
-tst 32 . . 0100101010...... A+-DXWL... U U U U U U U 4 4 2 2 2 2 2
-tst 32 . pcdi 0100101010111010 .......... . . U U U U U . . 7 7 7 7 7
-tst 32 . pcix 0100101010111011 .......... . . U U U U U . . 9 9 9 9 9
-tst 32 . i 0100101010111100 .......... . . U U U U U . . 6 6 6 6 6
-unlk 32 . a7 0100111001011111 .......... U U U U U U U 12 12 6 6 6 6 6
-unlk 32 . . 0100111001011... .......... U U U U U U U 12 12 6 6 6 6 6
-unpk 16 rr . 1000...110000... .......... . . U U U U U . . 8 8 8 8 8
-unpk 16 mm ax7 1000111110001... .......... . . U U U U U . . 13 13 13 13 13
-unpk 16 mm ay7 1000...110001111 .......... . . U U U U U . . 13 13 13 13 13
-unpk 16 mm axy7 1000111110001111 .......... . . U U U U U . . 13 13 13 13 13
-unpk 16 mm . 1000...110001... .......... . . U U U U U . . 13 13 13 13 13
-
-
-
-XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-M68KMAKE_OPCODE_HANDLER
-
-M68KMAKE_OP(1010, 0, ., .)
-{
+# Opcode handlers
+#
+# One-line header followed by indented code
+#
+# Header:
+# - Base value to match for the opcode
+# - Base mask to use in matching
+# - Name of the opcode
+# - Size of the opcode b/w/l/. (. for unsized)
+# - Derivations to generate
+# - CPU coverage, cycles and priviledge level
+#
+
+# The derivations are the addressing-mode variants to generate (with
+# value/mask/cycles adjusted accordingly):
+# A: (an)
+# +: (an)+
+# -: -(an)
+# D: d(an)
+# X: d(an, ix)
+# W: adr.w
+# L: adr.l
+# d: d(pc)
+# x: d(pc, ix)
+# I: #val
+#
+# Opcodes with names ending in 'cc' are automatically derived on the
+# different possible condition codes.
+#
+# CPU coverage is a series of blocks with structure (cpu codes):base cycles[p]
+# CPU codes are:
+# 0: 68000/68008
+# 1: 68010
+# 2: 68020
+# 3: 68030
+# 4: 68040
+# f: fcpu
+# c: coldfire
+#
+# A suffix of 'p' indicates the instruction is priviledged for these
+# particular CPU variants.
+#
+# The body is C++ code with automatic substitutions:
+# M68KMAKE_CC: condition code test
+# M68KMAKE_NOT_CC: inverted condition code test
+# M68KMAKE_GET_EA_AY_8: compute the effective address for the current addressing mode knowing the size is byte
+# M68KMAKE_GET_EA_AY_16: compute the effective address for the current addressing mode knowing the size is word
+# M68KMAKE_GET_EA_AY_32: compute the effective address for the current addressing mode knowing the size is long
+# M68KMAKE_GET_OPER_AY_8: retrieve the source value for the current addressing mode knowing the size is byte
+# M68KMAKE_GET_OPER_AY_16: retrieve the source value for the current addressing mode knowing the size is word
+# M68KMAKE_GET_OPER_AY_32: retrieve the source value for the current addressing mode knowing the size is long
+
+a000 f000 1010 . . 01234fc:4
m68ki_exception_1010();
-}
-M68KMAKE_OP(1111, 0, ., .)
-{
+f000 f000 1111 . . 01234fc:4
m68ki_exception_1111();
-}
-M68KMAKE_OP(040fpu0, 32, ., .)
-{
+f200 ff00 040fpu0 l . 234f:0
if(m_has_fpu)
{
m68040_fpu_op0();
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(040fpu1, 32, ., .)
-{
+f300 ff00 040fpu1 l . 234f:0
if(m_has_fpu)
{
m68040_fpu_op1();
return;
}
m68ki_exception_1111();
-}
-
-M68KMAKE_OP(abcd, 8, rr, .)
-{
+c100 f1f8 abcd b . 01:6 234fc:4
uint32_t* r_dst = &DX();
uint32_t src = DY();
uint32_t dst = *r_dst;
@@ -745,11 +99,9 @@ M68KMAKE_OP(abcd, 8, rr, .)
m_not_z_flag |= res;
*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
-}
-M68KMAKE_OP(abcd, 8, mm, ax7)
-{
+cf08 fff8 abcd b . 01:18 234fc:16
uint32_t src = OPER_AY_PD_8();
uint32_t ea = EA_A7_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -772,11 +124,9 @@ M68KMAKE_OP(abcd, 8, mm, ax7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(abcd, 8, mm, ay7)
-{
+c10f f1ff abcd b . 01:18 234fc:16
uint32_t src = OPER_A7_PD_8();
uint32_t ea = EA_AX_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -799,11 +149,9 @@ M68KMAKE_OP(abcd, 8, mm, ay7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(abcd, 8, mm, axy7)
-{
+cf0f ffff abcd b . 01:18 234fc:16
uint32_t src = OPER_A7_PD_8();
uint32_t ea = EA_A7_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -826,11 +174,9 @@ M68KMAKE_OP(abcd, 8, mm, axy7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(abcd, 8, mm, .)
-{
+c108 f1f8 abcd b . 01:18 234fc:16
uint32_t src = OPER_AY_PD_8();
uint32_t ea = EA_AX_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -853,11 +199,9 @@ M68KMAKE_OP(abcd, 8, mm, .)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(add, 8, er, d)
-{
+d000 f1f8 add b . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_8(DY());
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -869,11 +213,9 @@ M68KMAKE_OP(add, 8, er, d)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
*r_dst = MASK_OUT_BELOW_8(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(add, 8, er, .)
-{
+d000 f1c0 add b A+-DXWLdxI 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = M68KMAKE_GET_OPER_AY_8;
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -885,11 +227,9 @@ M68KMAKE_OP(add, 8, er, .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
*r_dst = MASK_OUT_BELOW_8(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(add, 16, er, d)
-{
+d040 f1f8 add w . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_16(DY());
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -901,11 +241,9 @@ M68KMAKE_OP(add, 16, er, d)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(add, 16, er, a)
-{
+d048 f1f8 add w . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_16(AY());
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -917,11 +255,9 @@ M68KMAKE_OP(add, 16, er, a)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(add, 16, er, .)
-{
+d040 f1c0 add w A+-DXWLdxI 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = M68KMAKE_GET_OPER_AY_16;
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -933,11 +269,9 @@ M68KMAKE_OP(add, 16, er, .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(add, 32, er, d)
-{
+d080 f1f8 add l . 01:6 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = DY();
uint32_t dst = *r_dst;
@@ -949,11 +283,9 @@ M68KMAKE_OP(add, 32, er, d)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(add, 32, er, a)
-{
+d088 f1f8 add l . 01:6 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = AY();
uint32_t dst = *r_dst;
@@ -965,11 +297,9 @@ M68KMAKE_OP(add, 32, er, a)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(add, 32, er, .)
-{
+d080 f1c0 add l A+-DXWLdxI 01:6 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = M68KMAKE_GET_OPER_AY_32;
uint32_t dst = *r_dst;
@@ -981,11 +311,9 @@ M68KMAKE_OP(add, 32, er, .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(add, 8, re, .)
-{
+d100 f1c0 add b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = MASK_OUT_ABOVE_8(DX());
uint32_t dst = m68ki_read_8(ea);
@@ -997,11 +325,9 @@ M68KMAKE_OP(add, 8, re, .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m68ki_write_8(ea, m_not_z_flag);
-}
-M68KMAKE_OP(add, 16, re, .)
-{
+d140 f1c0 add w A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = MASK_OUT_ABOVE_16(DX());
uint32_t dst = m68ki_read_16(ea);
@@ -1013,11 +339,9 @@ M68KMAKE_OP(add, 16, re, .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m68ki_write_16(ea, m_not_z_flag);
-}
-M68KMAKE_OP(add, 32, re, .)
-{
+d180 f1c0 add l A+-DXWL 01:12 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t src = DX();
uint32_t dst = m68ki_read_32(ea);
@@ -1029,61 +353,47 @@ M68KMAKE_OP(add, 32, re, .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m68ki_write_32(ea, m_not_z_flag);
-}
-M68KMAKE_OP(adda, 16, ., d)
-{
+d0c0 f1f8 adda w . 01:8 234fc:2
uint32_t* r_dst = &AX();
*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY()));
-}
-M68KMAKE_OP(adda, 16, ., a)
-{
+d0c8 f1f8 adda w . 01:8 234fc:2
uint32_t* r_dst = &AX();
*r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY()));
-}
-M68KMAKE_OP(adda, 16, ., .)
-{
+d0c0 f1c0 adda w A+-DXWLdxI 01:8 234fc:2
uint32_t* r_dst = &AX();
uint32_t src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
-}
-M68KMAKE_OP(adda, 32, ., d)
-{
+d1c0 f1f8 adda l . 01:6 234fc:2
uint32_t* r_dst = &AX();
*r_dst = MASK_OUT_ABOVE_32(*r_dst + DY());
-}
-M68KMAKE_OP(adda, 32, ., a)
-{
+d1c8 f1f8 adda l . 01:6 234fc:2
uint32_t* r_dst = &AX();
*r_dst = MASK_OUT_ABOVE_32(*r_dst + AY());
-}
-M68KMAKE_OP(adda, 32, ., .)
-{
+d1c0 f1c0 adda l A+-DXWLdxI 01:6 234fc:2
uint32_t* r_dst = &AX();
uint32_t src = M68KMAKE_GET_OPER_AY_32;
*r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
-}
-M68KMAKE_OP(addi, 8, ., d)
-{
+0600 fff8 addi b . 01:8 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = OPER_I_8();
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -1095,11 +405,9 @@ M68KMAKE_OP(addi, 8, ., d)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
*r_dst = MASK_OUT_BELOW_8(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(addi, 8, ., .)
-{
+0600 ffc0 addi b A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_8();
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t dst = m68ki_read_8(ea);
@@ -1111,11 +419,9 @@ M68KMAKE_OP(addi, 8, ., .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m68ki_write_8(ea, m_not_z_flag);
-}
-M68KMAKE_OP(addi, 16, ., d)
-{
+0640 fff8 addi w . 01:8 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = OPER_I_16();
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -1127,11 +433,9 @@ M68KMAKE_OP(addi, 16, ., d)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(addi, 16, ., .)
-{
+0640 ffc0 addi w A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_16();
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t dst = m68ki_read_16(ea);
@@ -1143,11 +447,9 @@ M68KMAKE_OP(addi, 16, ., .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m68ki_write_16(ea, m_not_z_flag);
-}
-M68KMAKE_OP(addi, 32, ., d)
-{
+0680 fff8 addi l . 0:16 1:14 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = OPER_I_32();
uint32_t dst = *r_dst;
@@ -1159,11 +461,9 @@ M68KMAKE_OP(addi, 32, ., d)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(addi, 32, ., .)
-{
+0680 ffc0 addi l A+-DXWL 01:20 234fc:4
uint32_t src = OPER_I_32();
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t dst = m68ki_read_32(ea);
@@ -1175,11 +475,9 @@ M68KMAKE_OP(addi, 32, ., .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m68ki_write_32(ea, m_not_z_flag);
-}
-M68KMAKE_OP(addq, 8, ., d)
-{
+5000 f1f8 addq b . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -1191,11 +489,9 @@ M68KMAKE_OP(addq, 8, ., d)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
*r_dst = MASK_OUT_BELOW_8(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(addq, 8, ., .)
-{
+5000 f1c0 addq b A+-DXWL 01:8 234fc:4
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t dst = m68ki_read_8(ea);
@@ -1207,11 +503,9 @@ M68KMAKE_OP(addq, 8, ., .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m68ki_write_8(ea, m_not_z_flag);
-}
-M68KMAKE_OP(addq, 16, ., d)
-{
+5040 f1f8 addq w . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -1223,19 +517,15 @@ M68KMAKE_OP(addq, 16, ., d)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(addq, 16, ., a)
-{
+5048 f1f8 addq w . 01:4 234fc:2
uint32_t* r_dst = &AY();
*r_dst = MASK_OUT_ABOVE_32(*r_dst + (((m_ir >> 9) - 1) & 7) + 1);
-}
-M68KMAKE_OP(addq, 16, ., .)
-{
+5040 f1c0 addq w A+-DXWL 01:8 234fc:4
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t dst = m68ki_read_16(ea);
@@ -1247,11 +537,9 @@ M68KMAKE_OP(addq, 16, ., .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m68ki_write_16(ea, m_not_z_flag);
-}
-M68KMAKE_OP(addq, 32, ., d)
-{
+5080 f1f8 addq l . 01:8 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t dst = *r_dst;
@@ -1263,19 +551,15 @@ M68KMAKE_OP(addq, 32, ., d)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(addq, 32, ., a)
-{
+5088 f1f8 addq l . 01:8 234fc:2
uint32_t* r_dst = &AY();
*r_dst = MASK_OUT_ABOVE_32(*r_dst + (((m_ir >> 9) - 1) & 7) + 1);
-}
-M68KMAKE_OP(addq, 32, ., .)
-{
+5080 f1c0 addq l A+-DXWL 01:12 234fc:4
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t dst = m68ki_read_32(ea);
@@ -1288,11 +572,9 @@ M68KMAKE_OP(addq, 32, ., .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m68ki_write_32(ea, m_not_z_flag);
-}
-M68KMAKE_OP(addx, 8, rr, .)
-{
+d100 f1f8 addx b . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_8(DY());
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -1306,11 +588,9 @@ M68KMAKE_OP(addx, 8, rr, .)
m_not_z_flag |= res;
*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
-}
-M68KMAKE_OP(addx, 16, rr, .)
-{
+d140 f1f8 addx w . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_16(DY());
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -1324,11 +604,9 @@ M68KMAKE_OP(addx, 16, rr, .)
m_not_z_flag |= res;
*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
-}
-M68KMAKE_OP(addx, 32, rr, .)
-{
+d180 f1f8 addx l . 0:8 1:6 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = DY();
uint32_t dst = *r_dst;
@@ -1342,11 +620,9 @@ M68KMAKE_OP(addx, 32, rr, .)
m_not_z_flag |= res;
*r_dst = res;
-}
-M68KMAKE_OP(addx, 8, mm, ax7)
-{
+df08 fff8 addx b . 01:18 234fc:12
uint32_t src = OPER_AY_PD_8();
uint32_t ea = EA_A7_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -1360,11 +636,9 @@ M68KMAKE_OP(addx, 8, mm, ax7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(addx, 8, mm, ay7)
-{
+d10f f1ff addx b . 01:18 234fc:12
uint32_t src = OPER_A7_PD_8();
uint32_t ea = EA_AX_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -1378,11 +652,9 @@ M68KMAKE_OP(addx, 8, mm, ay7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(addx, 8, mm, axy7)
-{
+df0f ffff addx b . 01:18 234fc:12
uint32_t src = OPER_A7_PD_8();
uint32_t ea = EA_A7_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -1396,11 +668,9 @@ M68KMAKE_OP(addx, 8, mm, axy7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(addx, 8, mm, .)
-{
+d108 f1f8 addx b . 01:18 234fc:12
uint32_t src = OPER_AY_PD_8();
uint32_t ea = EA_AX_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -1414,11 +684,9 @@ M68KMAKE_OP(addx, 8, mm, .)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(addx, 16, mm, .)
-{
+d148 f1f8 addx w . 01:18 234fc:12
uint32_t src = OPER_AY_PD_16();
uint32_t ea = EA_AX_PD_16();
uint32_t dst = m68ki_read_16(ea);
@@ -1432,11 +700,9 @@ M68KMAKE_OP(addx, 16, mm, .)
m_not_z_flag |= res;
m68ki_write_16(ea, res);
-}
-M68KMAKE_OP(addx, 32, mm, .)
-{
+d188 f1f8 addx l . 01:30 234fc:12
uint32_t src = OPER_AY_PD_32();
uint32_t ea = EA_AX_PD_32();
uint32_t dst = m68ki_read_32(ea);
@@ -1450,71 +716,57 @@ M68KMAKE_OP(addx, 32, mm, .)
m_not_z_flag |= res;
m68ki_write_32(ea, res);
-}
-M68KMAKE_OP(and, 8, er, d)
-{
+c000 f1f8 and b . 01:4 234fc:2
m_not_z_flag = MASK_OUT_ABOVE_8(DX() &= (DY() | 0xffffff00));
m_n_flag = NFLAG_8(m_not_z_flag);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(and, 8, er, .)
-{
+c000 f1c0 and b A+-DXWLdxI 01:4 234fc:2
m_not_z_flag = MASK_OUT_ABOVE_8(DX() &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
m_n_flag = NFLAG_8(m_not_z_flag);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(and, 16, er, d)
-{
+c040 f1f8 and w . 01:4 234fc:2
m_not_z_flag = MASK_OUT_ABOVE_16(DX() &= (DY() | 0xffff0000));
m_n_flag = NFLAG_16(m_not_z_flag);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(and, 16, er, .)
-{
+c040 f1c0 and w A+-DXWLdxI 01:4 234fc:2
m_not_z_flag = MASK_OUT_ABOVE_16(DX() &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
m_n_flag = NFLAG_16(m_not_z_flag);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(and, 32, er, d)
-{
+c080 f1f8 and l . 01:6 234fc:2
m_not_z_flag = DX() &= DY();
m_n_flag = NFLAG_32(m_not_z_flag);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(and, 32, er, .)
-{
+c080 f1c0 and l A+-DXWLdxI 01:6 234fc:2
m_not_z_flag = DX() &= M68KMAKE_GET_OPER_AY_32;
m_n_flag = NFLAG_32(m_not_z_flag);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(and, 8, re, .)
-{
+c100 f1c0 and b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t res = DX() & m68ki_read_8(ea);
@@ -1524,11 +776,9 @@ M68KMAKE_OP(and, 8, re, .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m68ki_write_8(ea, m_not_z_flag);
-}
-M68KMAKE_OP(and, 16, re, .)
-{
+c140 f1c0 and w A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t res = DX() & m68ki_read_16(ea);
@@ -1538,11 +788,9 @@ M68KMAKE_OP(and, 16, re, .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m68ki_write_16(ea, m_not_z_flag);
-}
-M68KMAKE_OP(and, 32, re, .)
-{
+c180 f1c0 and l A+-DXWL 01:12 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t res = DX() & m68ki_read_32(ea);
@@ -1552,21 +800,17 @@ M68KMAKE_OP(and, 32, re, .)
m_v_flag = VFLAG_CLEAR;
m68ki_write_32(ea, res);
-}
-M68KMAKE_OP(andi, 8, ., d)
-{
+0200 fff8 andi b . 01:8 234fc:2
m_not_z_flag = MASK_OUT_ABOVE_8(DY() &= (OPER_I_8() | 0xffffff00));
m_n_flag = NFLAG_8(m_not_z_flag);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(andi, 8, ., .)
-{
+0200 ffc0 andi b A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_8();
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t res = src & m68ki_read_8(ea);
@@ -1577,21 +821,17 @@ M68KMAKE_OP(andi, 8, ., .)
m_v_flag = VFLAG_CLEAR;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(andi, 16, ., d)
-{
+0240 fff8 andi w . 01:8 234fc:2
m_not_z_flag = MASK_OUT_ABOVE_16(DY() &= (OPER_I_16() | 0xffff0000));
m_n_flag = NFLAG_16(m_not_z_flag);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(andi, 16, ., .)
-{
+0240 ffc0 andi w A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_16();
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t res = src & m68ki_read_16(ea);
@@ -1602,21 +842,17 @@ M68KMAKE_OP(andi, 16, ., .)
m_v_flag = VFLAG_CLEAR;
m68ki_write_16(ea, res);
-}
-M68KMAKE_OP(andi, 32, ., d)
-{
+0280 fff8 andi l . 01:14 234fc:2
m_not_z_flag = DY() &= (OPER_I_32());
m_n_flag = NFLAG_32(m_not_z_flag);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(andi, 32, ., .)
-{
+0280 ffc0 andi l A+-DXWL 01:20 234fc:4
uint32_t src = OPER_I_32();
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t res = src & m68ki_read_32(ea);
@@ -1627,17 +863,13 @@ M68KMAKE_OP(andi, 32, ., .)
m_v_flag = VFLAG_CLEAR;
m68ki_write_32(ea, res);
-}
-M68KMAKE_OP(andi, 8, toc, .)
-{
+023c ffff andi w . 0:20 1:16 234fc:12
m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8());
-}
-M68KMAKE_OP(andi, 16, tos, .)
-{
+027c ffff andi w . 0:20p 1:16p 234fc:12p
if(m_s_flag)
{
uint32_t src = OPER_I_16();
@@ -1646,11 +878,9 @@ M68KMAKE_OP(andi, 16, tos, .)
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(asr, 8, s, .)
-{
+e000 f1f8 asr b . 01234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -1668,11 +898,9 @@ M68KMAKE_OP(asr, 8, s, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_x_flag = m_c_flag = src << (9-shift);
-}
-M68KMAKE_OP(asr, 16, s, .)
-{
+e040 f1f8 asr w . 01234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -1690,11 +918,9 @@ M68KMAKE_OP(asr, 16, s, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_x_flag = m_c_flag = src << (9-shift);
-}
-M68KMAKE_OP(asr, 32, s, .)
-{
+e080 f1f8 asr l . 01:8 234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = *r_dst;
@@ -1712,11 +938,9 @@ M68KMAKE_OP(asr, 32, s, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_x_flag = m_c_flag = src << (9-shift);
-}
-M68KMAKE_OP(asr, 8, r, .)
-{
+e020 f1f8 asr b . 01234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -1764,11 +988,9 @@ M68KMAKE_OP(asr, 8, r, .)
m_n_flag = NFLAG_8(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(asr, 16, r, .)
-{
+e060 f1f8 asr w . 01234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -1816,11 +1038,9 @@ M68KMAKE_OP(asr, 16, r, .)
m_n_flag = NFLAG_16(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(asr, 32, r, .)
-{
+e0a0 f1f8 asr l . 01:8 234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = *r_dst;
@@ -1868,11 +1088,9 @@ M68KMAKE_OP(asr, 32, r, .)
m_n_flag = NFLAG_32(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(asr, 16, ., .)
-{
+e0c0 ffc0 asr w A+-DXWL 01:8 234fc:5
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = src >> 1;
@@ -1886,11 +1104,9 @@ M68KMAKE_OP(asr, 16, ., .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = m_x_flag = src << 8;
-}
-M68KMAKE_OP(asl, 8, s, .)
-{
+e100 f1f8 asl b . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -1906,11 +1122,9 @@ M68KMAKE_OP(asl, 8, s, .)
m_not_z_flag = res;
src &= m68ki_shift_8_table[shift + 1];
m_v_flag = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
-}
-M68KMAKE_OP(asl, 16, s, .)
-{
+e140 f1f8 asl w . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -1926,11 +1140,9 @@ M68KMAKE_OP(asl, 16, s, .)
m_x_flag = m_c_flag = src >> (8-shift);
src &= m68ki_shift_16_table[shift + 1];
m_v_flag = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
-}
-M68KMAKE_OP(asl, 32, s, .)
-{
+e180 f1f8 asl l . 01234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = *r_dst;
@@ -1946,11 +1158,9 @@ M68KMAKE_OP(asl, 32, s, .)
m_x_flag = m_c_flag = src >> (24-shift);
src &= m68ki_shift_32_table[shift + 1];
m_v_flag = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
-}
-M68KMAKE_OP(asl, 8, r, .)
-{
+e120 f1f8 asl b . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -1983,11 +1193,9 @@ M68KMAKE_OP(asl, 8, r, .)
m_n_flag = NFLAG_8(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(asl, 16, r, .)
-{
+e160 f1f8 asl w . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -2020,11 +1228,9 @@ M68KMAKE_OP(asl, 16, r, .)
m_n_flag = NFLAG_16(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(asl, 32, r, .)
-{
+e1a0 f1f8 asl l . 01234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = *r_dst;
@@ -2057,11 +1263,9 @@ M68KMAKE_OP(asl, 32, r, .)
m_n_flag = NFLAG_32(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(asl, 16, ., .)
-{
+e1c0 ffc0 asl w A+-DXWL 01:8 234fc:6
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = MASK_OUT_ABOVE_16(src << 1);
@@ -2073,11 +1277,9 @@ M68KMAKE_OP(asl, 16, ., .)
m_x_flag = m_c_flag = src >> 7;
src &= 0xc000;
m_v_flag = (!(src == 0 || src == 0xc000))<<7;
-}
-M68KMAKE_OP(bcc, 8, ., .)
-{
+6000 f000 bcc b . 01:10 234fc:6
if(M68KMAKE_CC)
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
@@ -2085,11 +1287,9 @@ M68KMAKE_OP(bcc, 8, ., .)
return;
}
m_icount -= m_cyc_bcc_notake_b;
-}
-M68KMAKE_OP(bcc, 16, ., .)
-{
+6000 f0ff bcc w . 01:10 234fc:6
if(M68KMAKE_CC)
{
uint32_t offset = OPER_I_16();
@@ -2100,11 +1300,9 @@ M68KMAKE_OP(bcc, 16, ., .)
}
m_pc += 2;
m_icount -= m_cyc_bcc_notake_w;
-}
-M68KMAKE_OP(bcc, 32, ., .)
-{
+60ff f0ff bcc l . 01:10 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
if(M68KMAKE_CC)
@@ -2128,95 +1326,77 @@ M68KMAKE_OP(bcc, 32, ., .)
}
m_icount -= m_cyc_bcc_notake_b;
}
-}
-M68KMAKE_OP(bchg, 32, r, d)
-{
+0140 f1f8 bchg l . 01:8 234fc:4
uint32_t* r_dst = &DY();
uint32_t mask = 1 << (DX() & 0x1f);
m_not_z_flag = *r_dst & mask;
*r_dst ^= mask;
-}
-M68KMAKE_OP(bchg, 8, r, .)
-{
+0140 f1c0 bchg b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = m68ki_read_8(ea);
uint32_t mask = 1 << (DX() & 7);
m_not_z_flag = src & mask;
m68ki_write_8(ea, src ^ mask);
-}
-M68KMAKE_OP(bchg, 32, s, d)
-{
+0840 fff8 bchg l . 01:12 234fc:4
uint32_t* r_dst = &DY();
uint32_t mask = 1 << (OPER_I_8() & 0x1f);
m_not_z_flag = *r_dst & mask;
*r_dst ^= mask;
-}
-M68KMAKE_OP(bchg, 8, s, .)
-{
+0840 ffc0 bchg b A+-DXWL 01:12 234fc:4
uint32_t mask = 1 << (OPER_I_8() & 7);
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = m68ki_read_8(ea);
m_not_z_flag = src & mask;
m68ki_write_8(ea, src ^ mask);
-}
-M68KMAKE_OP(bclr, 32, r, d)
-{
+0180 f1f8 bclr l . 01:10 234fc:4
uint32_t* r_dst = &DY();
uint32_t mask = 1 << (DX() & 0x1f);
m_not_z_flag = *r_dst & mask;
*r_dst &= ~mask;
-}
-M68KMAKE_OP(bclr, 8, r, .)
-{
+0180 f1c0 bclr b A+-DXWL 0:8 1:10 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = m68ki_read_8(ea);
uint32_t mask = 1 << (DX() & 7);
m_not_z_flag = src & mask;
m68ki_write_8(ea, src & ~mask);
-}
-M68KMAKE_OP(bclr, 32, s, d)
-{
+0880 fff8 bclr l . 01:14 234fc:4
uint32_t* r_dst = &DY();
uint32_t mask = 1 << (OPER_I_8() & 0x1f);
m_not_z_flag = *r_dst & mask;
*r_dst &= ~mask;
-}
-M68KMAKE_OP(bclr, 8, s, .)
-{
+0880 ffc0 bclr b A+-DXWL 01:12 234fc:4
uint32_t mask = 1 << (OPER_I_8() & 7);
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = m68ki_read_8(ea);
m_not_z_flag = src & mask;
m68ki_write_8(ea, src & ~mask);
-}
-M68KMAKE_OP(bfchg, 32, ., d)
-{
+eac0 fff8 bfchg l . 234fc:12
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2247,11 +1427,9 @@ M68KMAKE_OP(bfchg, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfchg, 32, ., .)
-{
+eac0 ffc0 bfchg l ADXWL 234fc:20
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2301,11 +1479,9 @@ M68KMAKE_OP(bfchg, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfclr, 32, ., d)
-{
+ecc0 fff8 bfclr l . 234fc:12
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2338,11 +1514,9 @@ M68KMAKE_OP(bfclr, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfclr, 32, ., .)
-{
+ecc0 ffc0 bfclr l ADXWL 234fc:20
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2392,11 +1566,9 @@ M68KMAKE_OP(bfclr, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfexts, 32, ., d)
-{
+ebc0 fff8 bfexts l . 234fc:8
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2426,11 +1598,9 @@ M68KMAKE_OP(bfexts, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfexts, 32, ., .)
-{
+ebc0 ffc0 bfexts l ADXWLdx 234fc:15
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2478,11 +1648,9 @@ M68KMAKE_OP(bfexts, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfextu, 32, ., d)
-{
+e9c0 fff8 bfextu l . 234fc:8
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2512,11 +1680,9 @@ M68KMAKE_OP(bfextu, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfextu, 32, ., .)
-{
+e9c0 ffc0 bfextu l ADXWLdx 234fc:15
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2563,11 +1729,9 @@ M68KMAKE_OP(bfextu, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfffo, 32, ., d)
-{
+edc0 fff8 bfffo l . 234fc:18
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2601,11 +1765,9 @@ M68KMAKE_OP(bfffo, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfffo, 32, ., .)
-{
+edc0 ffc0 bfffo l ADXWLdx 234fc:28
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2653,11 +1815,9 @@ M68KMAKE_OP(bfffo, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfins, 32, ., d)
-{
+efc0 fff8 bfins l . 234fc:10
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2695,11 +1855,9 @@ M68KMAKE_OP(bfins, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfins, 32, ., .)
-{
+efc0 ffc0 bfins l ADXWL 234fc:17
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2771,11 +1929,9 @@ M68KMAKE_OP(bfins, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfset, 32, ., d)
-{
+eec0 fff8 bfset l . 234fc:12
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2808,11 +1964,9 @@ M68KMAKE_OP(bfset, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bfset, 32, ., .)
-{
+eec0 ffc0 bfset l ADXWL 234fc:20
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2861,11 +2015,9 @@ M68KMAKE_OP(bfset, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bftst, 32, ., d)
-{
+e8c0 fff8 bftst l . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2896,11 +2048,9 @@ M68KMAKE_OP(bftst, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bftst, 32, ., .)
-{
+e8c0 ffc0 bftst l ADXWLdx 234fc:13
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -2947,11 +2097,9 @@ M68KMAKE_OP(bftst, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bkpt, 0, ., .)
-{
+4848 fff8 bkpt . . 1234fc:10
if(CPU_TYPE_IS_EC020_PLUS())
{
(void)m_cpu_space->read_word((m_ir & 7) << 2, 0xffff);
@@ -2961,31 +2109,25 @@ M68KMAKE_OP(bkpt, 0, ., .)
(void)m_cpu_space->read_word(0x000000, 0xffff);
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(bra, 8, ., .)
-{
+6000 ff00 bra b . 01234fc:10
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_branch_8(MASK_OUT_ABOVE_8(m_ir));
if(m_pc == m_ppc && m_icount > 0)
m_icount = 0;
-}
-M68KMAKE_OP(bra, 16, ., .)
-{
+6000 ffff bra w . 01234fc:10
uint32_t offset = OPER_I_16();
m_pc -= 2;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_branch_16(offset);
if(m_pc == m_ppc && m_icount > 0)
m_icount = 0;
-}
-M68KMAKE_OP(bra, 32, ., .)
-{
+60ff ffff bra l . 01234fc:10
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t offset = OPER_I_32();
@@ -3003,71 +2145,57 @@ M68KMAKE_OP(bra, 32, ., .)
if(m_pc == m_ppc && m_icount > 0)
m_icount = 0;
}
-}
-M68KMAKE_OP(bset, 32, r, d)
-{
+01c0 f1f8 bset l . 01:8 234fc:4
uint32_t* r_dst = &DY();
uint32_t mask = 1 << (DX() & 0x1f);
m_not_z_flag = *r_dst & mask;
*r_dst |= mask;
-}
-M68KMAKE_OP(bset, 8, r, .)
-{
+01c0 f1c0 bset b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = m68ki_read_8(ea);
uint32_t mask = 1 << (DX() & 7);
m_not_z_flag = src & mask;
m68ki_write_8(ea, src | mask);
-}
-M68KMAKE_OP(bset, 32, s, d)
-{
+08c0 fff8 bset l . 01:12 234fc:4
uint32_t* r_dst = &DY();
uint32_t mask = 1 << (OPER_I_8() & 0x1f);
m_not_z_flag = *r_dst & mask;
*r_dst |= mask;
-}
-M68KMAKE_OP(bset, 8, s, .)
-{
+08c0 ffc0 bset b A+-DXWL 01:12 234fc:4
uint32_t mask = 1 << (OPER_I_8() & 7);
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = m68ki_read_8(ea);
m_not_z_flag = src & mask;
m68ki_write_8(ea, src | mask);
-}
-M68KMAKE_OP(bsr, 8, ., .)
-{
+6100 ff00 bsr b . 01:18 234fc:7
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_push_32(m_pc);
m68ki_branch_8(MASK_OUT_ABOVE_8(m_ir));
-}
-M68KMAKE_OP(bsr, 16, ., .)
-{
+6100 ffff bsr w . 01:18 234fc:7
uint32_t offset = OPER_I_16();
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_push_32(m_pc);
m_pc -= 2;
m68ki_branch_16(offset);
-}
-M68KMAKE_OP(bsr, 32, ., .)
-{
+61ff ffff bsr l . 01:18 234fc:7
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t offset = OPER_I_32();
@@ -3083,37 +2211,27 @@ M68KMAKE_OP(bsr, 32, ., .)
m68ki_push_32(m_pc);
m68ki_branch_8(MASK_OUT_ABOVE_8(m_ir));
}
-}
-M68KMAKE_OP(btst, 32, r, d)
-{
+0100 f1f8 btst l . 01:6 234fc:4
m_not_z_flag = DY() & (1 << (DX() & 0x1f));
-}
-M68KMAKE_OP(btst, 8, r, .)
-{
+0100 f1c0 btst b A+-DXWLdxI 01234fc:4
m_not_z_flag = M68KMAKE_GET_OPER_AY_8 & (1 << (DX() & 7));
-}
-M68KMAKE_OP(btst, 32, s, d)
-{
+0800 fff8 btst l . 01:10 234fc:4
m_not_z_flag = DY() & (1 << (OPER_I_8() & 0x1f));
-}
-M68KMAKE_OP(btst, 8, s, .)
-{
+0800 ffc0 btst b A+-DXWLdx 01:8 234fc:4
uint32_t bit = OPER_I_8() & 7;
m_not_z_flag = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
-}
-M68KMAKE_OP(callm, 32, ., .)
-{
+06c0 ffc0 callm l ADXWLdx 234fc:60
/* note: watch out for pcrelative modes */
if(CPU_TYPE_IS_020_VARIANT())
{
@@ -3121,17 +2239,15 @@ M68KMAKE_OP(callm, 32, ., .)
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m_pc += 2;
-(void)ea; /* just to avoid an 'unused variable' warning */
+ (void)ea; /* just to avoid an 'unused variable' warning */
logerror("%s at %08x: called unimplemented instruction %04x (callm)\n",
tag(), m_ppc, m_ir);
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cas, 8, ., .)
-{
+0ac0 ffc0 cas b A+-DXWL 234fc:12
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3156,11 +2272,9 @@ M68KMAKE_OP(cas, 8, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cas, 16, ., .)
-{
+0cc0 ffc0 cas w A+-DXWL 234fc:12
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3185,11 +2299,9 @@ M68KMAKE_OP(cas, 16, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cas, 32, ., .)
-{
+0ec0 ffc0 cas l A+-DXWL 234fc:12
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3214,11 +2326,9 @@ M68KMAKE_OP(cas, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cas2, 16, ., .)
-{
+0cfc ffff cas2 w . 234fc:12
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_32();
@@ -3259,11 +2369,9 @@ M68KMAKE_OP(cas2, 16, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cas2, 32, ., .)
-{
+0efc ffff cas2 l . 234fc:12
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_32();
@@ -3304,11 +2412,9 @@ M68KMAKE_OP(cas2, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk, 16, ., d)
-{
+4180 f1f8 chk w . 0:10 1234fc:8
int32_t src = MAKE_INT_16(DX());
int32_t bound = MAKE_INT_16(DY());
@@ -3322,11 +2428,9 @@ M68KMAKE_OP(chk, 16, ., d)
}
m_n_flag = (src < 0)<<7;
m68ki_exception_trap(EXCEPTION_CHK);
-}
-M68KMAKE_OP(chk, 16, ., .)
-{
+4180 f1c0 chk w A+-DXWLdxI 0:10 1234fc:8
int32_t src = MAKE_INT_16(DX());
int32_t bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
@@ -3340,11 +2444,9 @@ M68KMAKE_OP(chk, 16, ., .)
}
m_n_flag = (src < 0)<<7;
m68ki_exception_trap(EXCEPTION_CHK);
-}
-M68KMAKE_OP(chk, 32, ., d)
-{
+4100 f1f8 chk l . 234fc:8
if(CPU_TYPE_IS_EC020_PLUS())
{
int32_t src = MAKE_INT_32(DX());
@@ -3363,11 +2465,9 @@ M68KMAKE_OP(chk, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk, 32, ., .)
-{
+4100 f1c0 chk l A+-DXWLdxI 234fc:8
if(CPU_TYPE_IS_EC020_PLUS())
{
int32_t src = MAKE_INT_32(DX());
@@ -3386,11 +2486,9 @@ M68KMAKE_OP(chk, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
-{
+00fa ffff chk2cmp2 b . 234fc:23
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3420,11 +2518,9 @@ M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk2cmp2, 8, ., pcix)
-{
+00fb ffff chk2cmp2 b . 234fc:23
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3454,11 +2550,9 @@ M68KMAKE_OP(chk2cmp2, 8, ., pcix)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk2cmp2, 8, ., .)
-{
+00c0 ffc0 chk2cmp2 b ADXWL 234fc:18
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3488,11 +2582,9 @@ M68KMAKE_OP(chk2cmp2, 8, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
-{
+02fa ffff chk2cmp2 w . 234fc:23
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3522,11 +2614,9 @@ M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk2cmp2, 16, ., pcix)
-{
+02fb ffff chk2cmp2 w . 234fc:23
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3556,11 +2646,9 @@ M68KMAKE_OP(chk2cmp2, 16, ., pcix)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk2cmp2, 16, ., .)
-{
+02c0 ffc0 chk2cmp2 w ADXWL 234fc:18
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3590,11 +2678,9 @@ M68KMAKE_OP(chk2cmp2, 16, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
-{
+04fa ffff chk2cmp2 l . 234fc:23
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3619,11 +2705,9 @@ M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk2cmp2, 32, ., pcix)
-{
+04fb ffff chk2cmp2 l . 234fc:23
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3648,11 +2732,9 @@ M68KMAKE_OP(chk2cmp2, 32, ., pcix)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(chk2cmp2, 32, ., .)
-{
+04c0 ffc0 chk2cmp2 l ADXWL 234fc:18
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -3677,22 +2759,18 @@ M68KMAKE_OP(chk2cmp2, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(clr, 8, ., d)
-{
+4200 fff8 clr b . 01:4 234fc:2
DY() &= 0xffffff00;
m_n_flag = NFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
m_not_z_flag = ZFLAG_SET;
-}
-M68KMAKE_OP(clr, 8, ., .)
-{
+4200 ffc0 clr b A+-DXWL 0:8 1234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
if(CPU_TYPE_IS_000())
@@ -3706,22 +2784,18 @@ M68KMAKE_OP(clr, 8, ., .)
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
m_not_z_flag = ZFLAG_SET;
-}
-M68KMAKE_OP(clr, 16, ., d)
-{
+4240 fff8 clr w . 01:4 234fc:2
DY() &= 0xffff0000;
m_n_flag = NFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
m_not_z_flag = ZFLAG_SET;
-}
-M68KMAKE_OP(clr, 16, ., .)
-{
+4240 ffc0 clr w A+-DXWL 0:8 1234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_16;
if(CPU_TYPE_IS_000())
@@ -3735,22 +2809,18 @@ M68KMAKE_OP(clr, 16, ., .)
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
m_not_z_flag = ZFLAG_SET;
-}
-M68KMAKE_OP(clr, 32, ., d)
-{
+4280 fff8 clr l . 01:6 234fc:2
DY() = 0;
m_n_flag = NFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
m_not_z_flag = ZFLAG_SET;
-}
-M68KMAKE_OP(clr, 32, ., .)
-{
+4280 ffc0 clr l A+-DXWL 0:12 1:6 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_32;
if(CPU_TYPE_IS_000())
@@ -3764,11 +2834,9 @@ M68KMAKE_OP(clr, 32, ., .)
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
m_not_z_flag = ZFLAG_SET;
-}
-M68KMAKE_OP(cmp, 8, ., d)
-{
+b000 f1f8 cmp b . 01:4 234fc:2
uint32_t src = MASK_OUT_ABOVE_8(DY());
uint32_t dst = MASK_OUT_ABOVE_8(DX());
uint32_t res = dst - src;
@@ -3777,11 +2845,9 @@ M68KMAKE_OP(cmp, 8, ., d)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m_v_flag = VFLAG_SUB_8(src, dst, res);
m_c_flag = CFLAG_8(res);
-}
-M68KMAKE_OP(cmp, 8, ., .)
-{
+b000 f1c0 cmp b A+-DXWLdxI 01:4 234fc:2
uint32_t src = M68KMAKE_GET_OPER_AY_8;
uint32_t dst = MASK_OUT_ABOVE_8(DX());
uint32_t res = dst - src;
@@ -3790,11 +2856,9 @@ M68KMAKE_OP(cmp, 8, ., .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m_v_flag = VFLAG_SUB_8(src, dst, res);
m_c_flag = CFLAG_8(res);
-}
-M68KMAKE_OP(cmp, 16, ., d)
-{
+b040 f1f8 cmp w . 01:4 234fc:2
uint32_t src = MASK_OUT_ABOVE_16(DY());
uint32_t dst = MASK_OUT_ABOVE_16(DX());
uint32_t res = dst - src;
@@ -3803,11 +2867,9 @@ M68KMAKE_OP(cmp, 16, ., d)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m_v_flag = VFLAG_SUB_16(src, dst, res);
m_c_flag = CFLAG_16(res);
-}
-M68KMAKE_OP(cmp, 16, ., a)
-{
+b048 f1f8 cmp w . 01:4 234fc:2
uint32_t src = MASK_OUT_ABOVE_16(AY());
uint32_t dst = MASK_OUT_ABOVE_16(DX());
uint32_t res = dst - src;
@@ -3816,11 +2878,9 @@ M68KMAKE_OP(cmp, 16, ., a)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m_v_flag = VFLAG_SUB_16(src, dst, res);
m_c_flag = CFLAG_16(res);
-}
-M68KMAKE_OP(cmp, 16, ., .)
-{
+b040 f1c0 cmp w A+-DXWLdxI 01:4 234fc:2
uint32_t src = M68KMAKE_GET_OPER_AY_16;
uint32_t dst = MASK_OUT_ABOVE_16(DX());
uint32_t res = dst - src;
@@ -3829,11 +2889,9 @@ M68KMAKE_OP(cmp, 16, ., .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m_v_flag = VFLAG_SUB_16(src, dst, res);
m_c_flag = CFLAG_16(res);
-}
-M68KMAKE_OP(cmp, 32, ., d)
-{
+b080 f1f8 cmp l . 01:6 234fc:2
uint32_t src = DY();
uint32_t dst = DX();
uint32_t res = dst - src;
@@ -3842,11 +2900,9 @@ M68KMAKE_OP(cmp, 32, ., d)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmp, 32, ., a)
-{
+b088 f1f8 cmp l . 01:6 234fc:2
uint32_t src = AY();
uint32_t dst = DX();
uint32_t res = dst - src;
@@ -3855,11 +2911,9 @@ M68KMAKE_OP(cmp, 32, ., a)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmp, 32, ., .)
-{
+b080 f1c0 cmp l A+-DXWLdxI 01:6 234fc:2
uint32_t src = M68KMAKE_GET_OPER_AY_32;
uint32_t dst = DX();
uint32_t res = dst - src;
@@ -3868,11 +2922,9 @@ M68KMAKE_OP(cmp, 32, ., .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmpa, 16, ., d)
-{
+b0c0 f1f8 cmpa w . 01:6 234fc:4
uint32_t src = MAKE_INT_16(DY());
uint32_t dst = AX();
uint32_t res = dst - src;
@@ -3881,11 +2933,9 @@ M68KMAKE_OP(cmpa, 16, ., d)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmpa, 16, ., a)
-{
+b0c8 f1f8 cmpa w . 01:6 234fc:4
uint32_t src = MAKE_INT_16(AY());
uint32_t dst = AX();
uint32_t res = dst - src;
@@ -3894,11 +2944,9 @@ M68KMAKE_OP(cmpa, 16, ., a)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmpa, 16, ., .)
-{
+b0c0 f1c0 cmpa w A+-DXWLdxI 01:6 234fc:4
uint32_t src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
uint32_t dst = AX();
uint32_t res = dst - src;
@@ -3907,11 +2955,9 @@ M68KMAKE_OP(cmpa, 16, ., .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmpa, 32, ., d)
-{
+b1c0 f1f8 cmpa l . 01:6 234fc:4
uint32_t src = DY();
uint32_t dst = AX();
uint32_t res = dst - src;
@@ -3920,11 +2966,9 @@ M68KMAKE_OP(cmpa, 32, ., d)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmpa, 32, ., a)
-{
+b1c8 f1f8 cmpa l . 01:6 234fc:4
uint32_t src = AY();
uint32_t dst = AX();
uint32_t res = dst - src;
@@ -3933,11 +2977,9 @@ M68KMAKE_OP(cmpa, 32, ., a)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmpa, 32, ., .)
-{
+b1c0 f1c0 cmpa l A+-DXWLdxI 01:6 234fc:4
uint32_t src = M68KMAKE_GET_OPER_AY_32;
uint32_t dst = AX();
uint32_t res = dst - src;
@@ -3946,11 +2988,9 @@ M68KMAKE_OP(cmpa, 32, ., .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmpi, 8, ., d)
-{
+0c00 fff8 cmpi b . 01:8 234fc:2
uint32_t src = OPER_I_8();
uint32_t dst = MASK_OUT_ABOVE_8(DY());
uint32_t res = dst - src;
@@ -3959,11 +2999,9 @@ M68KMAKE_OP(cmpi, 8, ., d)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m_v_flag = VFLAG_SUB_8(src, dst, res);
m_c_flag = CFLAG_8(res);
-}
-M68KMAKE_OP(cmpi, 8, ., .)
-{
+0c00 ffc0 cmpi b A+-DXWL 01:8 234fc:2
uint32_t src = OPER_I_8();
uint32_t dst = M68KMAKE_GET_OPER_AY_8;
uint32_t res = dst - src;
@@ -3972,11 +3010,9 @@ M68KMAKE_OP(cmpi, 8, ., .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m_v_flag = VFLAG_SUB_8(src, dst, res);
m_c_flag = CFLAG_8(res);
-}
-M68KMAKE_OP(cmpi, 8, ., pcdi)
-{
+0c3a ffff cmpi b . 234fc:7
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t src = OPER_I_8();
@@ -3990,11 +3026,9 @@ M68KMAKE_OP(cmpi, 8, ., pcdi)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cmpi, 8, ., pcix)
-{
+0c3b ffff cmpi b . 234fc:9
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t src = OPER_I_8();
@@ -4008,11 +3042,9 @@ M68KMAKE_OP(cmpi, 8, ., pcix)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cmpi, 16, ., d)
-{
+0c40 fff8 cmpi w . 01:8 234fc:2
uint32_t src = OPER_I_16();
uint32_t dst = MASK_OUT_ABOVE_16(DY());
uint32_t res = dst - src;
@@ -4021,11 +3053,9 @@ M68KMAKE_OP(cmpi, 16, ., d)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m_v_flag = VFLAG_SUB_16(src, dst, res);
m_c_flag = CFLAG_16(res);
-}
-M68KMAKE_OP(cmpi, 16, ., .)
-{
+0c40 ffc0 cmpi w A+-DXWL 01:8 234fc:2
uint32_t src = OPER_I_16();
uint32_t dst = M68KMAKE_GET_OPER_AY_16;
uint32_t res = dst - src;
@@ -4034,11 +3064,9 @@ M68KMAKE_OP(cmpi, 16, ., .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m_v_flag = VFLAG_SUB_16(src, dst, res);
m_c_flag = CFLAG_16(res);
-}
-M68KMAKE_OP(cmpi, 16, ., pcdi)
-{
+0c7a ffff cmpi w . 234fc:7
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t src = OPER_I_16();
@@ -4052,11 +3080,9 @@ M68KMAKE_OP(cmpi, 16, ., pcdi)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cmpi, 16, ., pcix)
-{
+0c7b ffff cmpi w . 234fc:9
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t src = OPER_I_16();
@@ -4070,11 +3096,9 @@ M68KMAKE_OP(cmpi, 16, ., pcix)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cmpi, 32, ., d)
-{
+0c80 fff8 cmpi l . 0:14 1:12 234fc:2
uint32_t src = OPER_I_32();
uint32_t dst = DY();
uint32_t res = dst - src;
@@ -4086,11 +3110,9 @@ M68KMAKE_OP(cmpi, 32, ., d)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmpi, 32, ., .)
-{
+0c80 ffc0 cmpi l A+-DXWL 01:12 234fc:2
uint32_t src = OPER_I_32();
uint32_t dst = M68KMAKE_GET_OPER_AY_32;
uint32_t res = dst - src;
@@ -4099,11 +3121,9 @@ M68KMAKE_OP(cmpi, 32, ., .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cmpi, 32, ., pcdi)
-{
+0cba ffff cmpi l . 234fc:7
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t src = OPER_I_32();
@@ -4117,11 +3137,9 @@ M68KMAKE_OP(cmpi, 32, ., pcdi)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cmpi, 32, ., pcix)
-{
+0cbb ffff cmpi l . 234fc:9
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t src = OPER_I_32();
@@ -4135,11 +3153,9 @@ M68KMAKE_OP(cmpi, 32, ., pcix)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cmpm, 8, ., ax7)
-{
+bf08 fff8 cmpm b . 01:12 234fc:9
uint32_t src = OPER_AY_PI_8();
uint32_t dst = OPER_A7_PI_8();
uint32_t res = dst - src;
@@ -4148,11 +3164,9 @@ M68KMAKE_OP(cmpm, 8, ., ax7)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m_v_flag = VFLAG_SUB_8(src, dst, res);
m_c_flag = CFLAG_8(res);
-}
-M68KMAKE_OP(cmpm, 8, ., ay7)
-{
+b10f f1ff cmpm b . 01:12 234fc:9
uint32_t src = OPER_A7_PI_8();
uint32_t dst = OPER_AX_PI_8();
uint32_t res = dst - src;
@@ -4161,11 +3175,9 @@ M68KMAKE_OP(cmpm, 8, ., ay7)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m_v_flag = VFLAG_SUB_8(src, dst, res);
m_c_flag = CFLAG_8(res);
-}
-M68KMAKE_OP(cmpm, 8, ., axy7)
-{
+bf0f ffff cmpm b . 01:12 234fc:9
uint32_t src = OPER_A7_PI_8();
uint32_t dst = OPER_A7_PI_8();
uint32_t res = dst - src;
@@ -4174,11 +3186,9 @@ M68KMAKE_OP(cmpm, 8, ., axy7)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m_v_flag = VFLAG_SUB_8(src, dst, res);
m_c_flag = CFLAG_8(res);
-}
-M68KMAKE_OP(cmpm, 8, ., .)
-{
+b108 f1f8 cmpm b . 01:12 234fc:9
uint32_t src = OPER_AY_PI_8();
uint32_t dst = OPER_AX_PI_8();
uint32_t res = dst - src;
@@ -4187,11 +3197,9 @@ M68KMAKE_OP(cmpm, 8, ., .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m_v_flag = VFLAG_SUB_8(src, dst, res);
m_c_flag = CFLAG_8(res);
-}
-M68KMAKE_OP(cmpm, 16, ., .)
-{
+b148 f1f8 cmpm w . 01:12 234fc:9
uint32_t src = OPER_AY_PI_16();
uint32_t dst = OPER_AX_PI_16();
uint32_t res = dst - src;
@@ -4200,11 +3208,9 @@ M68KMAKE_OP(cmpm, 16, ., .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m_v_flag = VFLAG_SUB_16(src, dst, res);
m_c_flag = CFLAG_16(res);
-}
-M68KMAKE_OP(cmpm, 32, ., .)
-{
+b188 f1f8 cmpm l . 01:20 234fc:9
uint32_t src = OPER_AY_PI_32();
uint32_t dst = OPER_AX_PI_32();
uint32_t res = dst - src;
@@ -4213,11 +3219,9 @@ M68KMAKE_OP(cmpm, 32, ., .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m_v_flag = VFLAG_SUB_32(src, dst, res);
m_c_flag = CFLAG_SUB_32(src, dst, res);
-}
-M68KMAKE_OP(cpbcc, 32, ., .)
-{
+f080 f180 cpbcc l . 23:4
if(CPU_TYPE_IS_EC020_PLUS())
{
logerror("%s at %08x: called unimplemented instruction %04x (cpbcc)\n",
@@ -4225,11 +3229,9 @@ M68KMAKE_OP(cpbcc, 32, ., .)
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(cpdbcc, 32, ., .)
-{
+f048 f1f8 cpdbcc l . 23:4
if(CPU_TYPE_IS_EC020_PLUS())
{
logerror("%s at %08x: called unimplemented instruction %04x (cpdbcc)\n",
@@ -4237,11 +3239,9 @@ M68KMAKE_OP(cpdbcc, 32, ., .)
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(cpgen, 32, ., .)
-{
+f000 f1c0 cpgen l . 23:4
if(CPU_TYPE_IS_EC020_PLUS() && (m_has_fpu || m_has_pmmu))
{
logerror("%s at %08x: called unimplemented instruction %04x (cpgen)\n",
@@ -4249,11 +3249,9 @@ M68KMAKE_OP(cpgen, 32, ., .)
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(cpscc, 32, ., .)
-{
+f040 f1c0 cpscc l . 23:4
if(CPU_TYPE_IS_EC020_PLUS())
{
logerror("%s at %08x: called unimplemented instruction %04x (cpscc)\n",
@@ -4261,11 +3259,9 @@ M68KMAKE_OP(cpscc, 32, ., .)
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(cptrapcc, 32, ., .)
-{
+f078 f1f8 cptrapcc l . 23:4
if(CPU_TYPE_IS_EC020_PLUS())
{
logerror("%s at %08x: called unimplemented instruction %04x (cptrapcc)\n",
@@ -4273,26 +3269,22 @@ M68KMAKE_OP(cptrapcc, 32, ., .)
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(ftrapcc, 32, ., .)
-{
+
+f278 fff8 ftrapcc l . 23:4
if(m_has_fpu)
{
m68881_ftrap();
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(dbt, 16, ., .)
-{
+
+50c8 fff8 dbt w . 01:12 234fc:6
m_pc += 2;
-}
-M68KMAKE_OP(dbf, 16, ., .)
-{
+51c8 fff8 dbf w . 01:12 2:6 34fc:4
uint32_t* r_dst = &DY();
uint32_t res = MASK_OUT_ABOVE_16(*r_dst - 1);
@@ -4308,11 +3300,9 @@ M68KMAKE_OP(dbf, 16, ., .)
}
m_pc += 2;
m_icount -= m_cyc_dbcc_f_exp;
-}
-M68KMAKE_OP(dbcc, 16, ., .)
-{
+50c8 f0f8 dbcc w . 01:12 234fc:6
if(M68KMAKE_NOT_CC)
{
uint32_t* r_dst = &DY();
@@ -4333,11 +3323,9 @@ M68KMAKE_OP(dbcc, 16, ., .)
return;
}
m_pc += 2;
-}
-M68KMAKE_OP(divs, 16, ., d)
-{
+81c0 f1f8 divs w . 0:158 1:122 234fc:56
uint32_t* r_dst = &DX();
int32_t src = MAKE_INT_16(DY());
int32_t quotient;
@@ -4370,11 +3358,9 @@ M68KMAKE_OP(divs, 16, ., d)
return;
}
m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
-}
-M68KMAKE_OP(divs, 16, ., .)
-{
+81c0 f1c0 divs w A+-DXWLdxI 0:158 1:122 234fc:56
uint32_t* r_dst = &DX();
int32_t src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
int32_t quotient;
@@ -4407,11 +3393,9 @@ M68KMAKE_OP(divs, 16, ., .)
return;
}
m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
-}
-M68KMAKE_OP(divu, 16, ., d)
-{
+80c0 f1f8 divu w . 0:140 1:108 234fc:44
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_16(DY());
@@ -4433,11 +3417,9 @@ M68KMAKE_OP(divu, 16, ., d)
return;
}
m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
-}
-M68KMAKE_OP(divu, 16, ., .)
-{
+80c0 f1c0 divu w A+-DXWLdxI 0:140 1:108 234fc:44
uint32_t* r_dst = &DX();
uint32_t src = M68KMAKE_GET_OPER_AY_16;
@@ -4459,11 +3441,9 @@ M68KMAKE_OP(divu, 16, ., .)
return;
}
m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
-}
-M68KMAKE_OP(divl, 32, ., d)
-{
+4c40 fff8 divl l . 234fc:84
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -4529,11 +3509,9 @@ M68KMAKE_OP(divl, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(divl, 32, ., .)
-{
+4c40 ffc0 divl l A+-DXWLdxI 234fc:84
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -4599,22 +3577,18 @@ M68KMAKE_OP(divl, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(eor, 8, ., d)
-{
+b100 f1f8 eor b . 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_8(DY() ^= MASK_OUT_ABOVE_8(DX()));
m_n_flag = NFLAG_8(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eor, 8, ., .)
-{
+b100 f1c0 eor b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t res = MASK_OUT_ABOVE_8(DX() ^ m68ki_read_8(ea));
@@ -4624,22 +3598,18 @@ M68KMAKE_OP(eor, 8, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eor, 16, ., d)
-{
+b140 f1f8 eor w . 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_16(DY() ^= MASK_OUT_ABOVE_16(DX()));
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eor, 16, ., .)
-{
+b140 f1c0 eor w A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t res = MASK_OUT_ABOVE_16(DX() ^ m68ki_read_16(ea));
@@ -4649,22 +3619,18 @@ M68KMAKE_OP(eor, 16, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eor, 32, ., d)
-{
+b180 f1f8 eor l . 0:8 1:6 234fc:2
uint32_t res = DY() ^= DX();
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eor, 32, ., .)
-{
+b180 f1c0 eor l A+-DXWL 01:12 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t res = DX() ^ m68ki_read_32(ea);
@@ -4674,22 +3640,18 @@ M68KMAKE_OP(eor, 32, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eori, 8, ., d)
-{
+0a00 fff8 eori b . 01:8 234fc:2
uint32_t res = MASK_OUT_ABOVE_8(DY() ^= OPER_I_8());
m_n_flag = NFLAG_8(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eori, 8, ., .)
-{
+0a00 ffc0 eori b A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_8();
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t res = src ^ m68ki_read_8(ea);
@@ -4700,22 +3662,18 @@ M68KMAKE_OP(eori, 8, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eori, 16, ., d)
-{
+0a40 fff8 eori w . 01:8 234fc:2
uint32_t res = MASK_OUT_ABOVE_16(DY() ^= OPER_I_16());
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eori, 16, ., .)
-{
+0a40 ffc0 eori w A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_16();
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t res = src ^ m68ki_read_16(ea);
@@ -4726,22 +3684,18 @@ M68KMAKE_OP(eori, 16, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eori, 32, ., d)
-{
+0a80 fff8 eori l . 0:16 1:14 234fc:2
uint32_t res = DY() ^= OPER_I_32();
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eori, 32, ., .)
-{
+0a80 ffc0 eori l A+-DXWL 01:20 234fc:4
uint32_t src = OPER_I_32();
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t res = src ^ m68ki_read_32(ea);
@@ -4752,17 +3706,13 @@ M68KMAKE_OP(eori, 32, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(eori, 8, toc, .)
-{
+0a3c ffff eori w . 0:20 1:16 234fc:12
m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8());
-}
-M68KMAKE_OP(eori, 16, tos, .)
-{
+0a7c ffff eori w . 0:20p 1:16p 234fc:12p
if(m_s_flag)
{
uint32_t src = OPER_I_16();
@@ -4771,41 +3721,33 @@ M68KMAKE_OP(eori, 16, tos, .)
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(exg, 32, dd, .)
-{
+c140 f1f8 exg l . 01:6 234fc:2
uint32_t* reg_a = &DX();
uint32_t* reg_b = &DY();
uint32_t tmp = *reg_a;
*reg_a = *reg_b;
*reg_b = tmp;
-}
-M68KMAKE_OP(exg, 32, aa, .)
-{
+c148 f1f8 exg l . 01:6 234fc:2
uint32_t* reg_a = &AX();
uint32_t* reg_b = &AY();
uint32_t tmp = *reg_a;
*reg_a = *reg_b;
*reg_b = tmp;
-}
-M68KMAKE_OP(exg, 32, da, .)
-{
+c188 f1f8 exg l . 01:6 234fc:2
uint32_t* reg_a = &DX();
uint32_t* reg_b = &AY();
uint32_t tmp = *reg_a;
*reg_a = *reg_b;
*reg_b = tmp;
-}
-M68KMAKE_OP(ext, 16, ., .)
-{
+4880 fff8 ext w . 01234fc:4
uint32_t* r_dst = &DY();
*r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
@@ -4814,11 +3756,9 @@ M68KMAKE_OP(ext, 16, ., .)
m_not_z_flag = MASK_OUT_ABOVE_16(*r_dst);
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(ext, 32, ., .)
-{
+48c0 fff8 ext l . 01234fc:4
uint32_t* r_dst = &DY();
*r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
@@ -4827,11 +3767,9 @@ M68KMAKE_OP(ext, 32, ., .)
m_not_z_flag = *r_dst;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(extb, 32, ., .)
-{
+49c0 fff8 extb l . 234fc:4
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t* r_dst = &DY();
@@ -4845,58 +3783,45 @@ M68KMAKE_OP(extb, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(illegal, 0, ., .)
-{
+4afc ffff illegal . . 01234fc:4
m68ki_exception_illegal();
-}
-M68KMAKE_OP(jmp, 32, ., .)
-{
+
+4ec0 ffc0 jmp l ADXWLdx 01:4 234fc:0
m68ki_jump(M68KMAKE_GET_EA_AY_32);
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
if(m_pc == m_ppc && m_icount > 0)
m_icount = 0;
-}
-M68KMAKE_OP(jsr, 32, ., .)
-{
+4e80 ffc0 jsr l ADXWLdx 01:12 234fc:0
uint32_t ea = M68KMAKE_GET_EA_AY_32;
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_push_32(m_pc);
m68ki_jump(ea);
-}
-M68KMAKE_OP(lea, 32, ., .)
-{
+41c0 f1c0 lea l ADXWLdx 01:0 234fc:2
AX() = M68KMAKE_GET_EA_AY_32;
-}
-M68KMAKE_OP(link, 16, ., a7)
-{
+4e57 ffff link w . 01:16 234fc:5
REG_A()[7] -= 4;
m68ki_write_32(REG_A()[7], REG_A()[7]);
REG_A()[7] = MASK_OUT_ABOVE_32(REG_A()[7] + MAKE_INT_16(OPER_I_16()));
-}
-M68KMAKE_OP(link, 16, ., .)
-{
+4e50 fff8 link w . 01:16 234fc:5
uint32_t* r_dst = &AY();
m68ki_push_32(*r_dst);
*r_dst = REG_A()[7];
REG_A()[7] = MASK_OUT_ABOVE_32(REG_A()[7] + MAKE_INT_16(OPER_I_16()));
-}
-M68KMAKE_OP(link, 32, ., a7)
-{
+480f ffff link l . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
REG_A()[7] -= 4;
@@ -4905,11 +3830,9 @@ M68KMAKE_OP(link, 32, ., a7)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(link, 32, ., .)
-{
+4808 fff8 link l . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t* r_dst = &AY();
@@ -4920,11 +3843,9 @@ M68KMAKE_OP(link, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(lsr, 8, s, .)
-{
+e008 f1f8 lsr b . 01:6 234fc:4
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -4939,11 +3860,9 @@ M68KMAKE_OP(lsr, 8, s, .)
m_not_z_flag = res;
m_x_flag = m_c_flag = src << (9-shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsr, 16, s, .)
-{
+e048 f1f8 lsr w . 01:6 234fc:4
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -4958,11 +3877,9 @@ M68KMAKE_OP(lsr, 16, s, .)
m_not_z_flag = res;
m_x_flag = m_c_flag = src << (9-shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsr, 32, s, .)
-{
+e088 f1f8 lsr l . 01:8 234fc:4
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = *r_dst;
@@ -4977,11 +3894,9 @@ M68KMAKE_OP(lsr, 32, s, .)
m_not_z_flag = res;
m_x_flag = m_c_flag = src << (9-shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsr, 8, r, .)
-{
+e028 f1f8 lsr b . 01234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -5014,11 +3929,9 @@ M68KMAKE_OP(lsr, 8, r, .)
m_n_flag = NFLAG_8(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsr, 16, r, .)
-{
+e068 f1f8 lsr w . 01234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -5051,11 +3964,9 @@ M68KMAKE_OP(lsr, 16, r, .)
m_n_flag = NFLAG_16(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsr, 32, r, .)
-{
+e0a8 f1f8 lsr l . 01:8 234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = *r_dst;
@@ -5087,11 +3998,9 @@ M68KMAKE_OP(lsr, 32, r, .)
m_n_flag = NFLAG_32(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsr, 16, ., .)
-{
+e2c0 ffc0 lsr w A+-DXWL 01:8 234fc:5
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = src >> 1;
@@ -5102,11 +4011,9 @@ M68KMAKE_OP(lsr, 16, ., .)
m_not_z_flag = res;
m_c_flag = m_x_flag = src << 8;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsl, 8, s, .)
-{
+e108 f1f8 lsl b . 01:6 234fc:4
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -5121,11 +4028,9 @@ M68KMAKE_OP(lsl, 8, s, .)
m_not_z_flag = res;
m_x_flag = m_c_flag = src << shift;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsl, 16, s, .)
-{
+e148 f1f8 lsl w . 01:6 234fc:4
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -5140,11 +4045,9 @@ M68KMAKE_OP(lsl, 16, s, .)
m_not_z_flag = res;
m_x_flag = m_c_flag = src >> (8-shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsl, 32, s, .)
-{
+e188 f1f8 lsl l . 01:8 234fc:4
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = *r_dst;
@@ -5159,11 +4062,9 @@ M68KMAKE_OP(lsl, 32, s, .)
m_not_z_flag = res;
m_x_flag = m_c_flag = src >> (24-shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsl, 8, r, .)
-{
+e128 f1f8 lsl b . 01234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -5196,11 +4097,9 @@ M68KMAKE_OP(lsl, 8, r, .)
m_n_flag = NFLAG_8(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsl, 16, r, .)
-{
+e168 f1f8 lsl w . 01234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -5233,11 +4132,9 @@ M68KMAKE_OP(lsl, 16, r, .)
m_n_flag = NFLAG_16(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsl, 32, r, .)
-{
+e1a8 f1f8 lsl l . 01:8 234fc:6
uint32_t* r_dst = &DY();
uint32_t shift = DX() & 0x3f;
uint32_t src = *r_dst;
@@ -5269,11 +4166,9 @@ M68KMAKE_OP(lsl, 32, r, .)
m_n_flag = NFLAG_32(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(lsl, 16, ., .)
-{
+e3c0 ffc0 lsl w A+-DXWL 01:8 234fc:5
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = MASK_OUT_ABOVE_16(src << 1);
@@ -5284,11 +4179,9 @@ M68KMAKE_OP(lsl, 16, ., .)
m_not_z_flag = res;
m_x_flag = m_c_flag = src >> 7;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, d, d)
-{
+1000 f1f8 move b . 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t* r_dst = &DX();
@@ -5298,11 +4191,9 @@ M68KMAKE_OP(move, 8, d, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, d, .)
-{
+1000 f1c0 move b A+-DXWLdxI 01:4 234fc:2
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t* r_dst = &DX();
@@ -5312,11 +4203,9 @@ M68KMAKE_OP(move, 8, d, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, ai, d)
-{
+1080 f1f8 move b . 01:8 234fc:4
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t ea = EA_AX_AI_8();
@@ -5326,11 +4215,9 @@ M68KMAKE_OP(move, 8, ai, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, ai, .)
-{
+1080 f1c0 move b A+-DXWLdxI 01:8 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t ea = EA_AX_AI_8();
@@ -5340,11 +4227,9 @@ M68KMAKE_OP(move, 8, ai, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, pi7, d)
-{
+1ec0 fff8 move b . 01:8 234fc:4
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t ea = EA_A7_PI_8();
@@ -5354,11 +4239,9 @@ M68KMAKE_OP(move, 8, pi7, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, pi, d)
-{
+10c0 f1f8 move b . 01:8 234fc:4
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t ea = EA_AX_PI_8();
@@ -5368,11 +4251,9 @@ M68KMAKE_OP(move, 8, pi, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, pi7, .)
-{
+1ec0 ffc0 move b A+-DXWLdxI 01:8 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t ea = EA_A7_PI_8();
@@ -5382,11 +4263,9 @@ M68KMAKE_OP(move, 8, pi7, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, pi, .)
-{
+10c0 f1c0 move b A+-DXWLdxI 01:8 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t ea = EA_AX_PI_8();
@@ -5396,11 +4275,9 @@ M68KMAKE_OP(move, 8, pi, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, pd7, d)
-{
+1f00 fff8 move b . 01:8 234fc:5
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t ea = EA_A7_PD_8();
@@ -5410,11 +4287,9 @@ M68KMAKE_OP(move, 8, pd7, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, pd, d)
-{
+1100 f1f8 move b . 01:8 234fc:5
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t ea = EA_AX_PD_8();
@@ -5424,11 +4299,9 @@ M68KMAKE_OP(move, 8, pd, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, pd7, .)
-{
+1f00 ffc0 move b A+-DXWLdxI 01:8 234fc:5
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t ea = EA_A7_PD_8();
@@ -5438,11 +4311,9 @@ M68KMAKE_OP(move, 8, pd7, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, pd, .)
-{
+1100 f1c0 move b A+-DXWLdxI 01:8 234fc:5
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t ea = EA_AX_PD_8();
@@ -5452,11 +4323,9 @@ M68KMAKE_OP(move, 8, pd, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, di, d)
-{
+1140 f1f8 move b . 01:12 234fc:5
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t ea = EA_AX_DI_8();
@@ -5466,11 +4335,9 @@ M68KMAKE_OP(move, 8, di, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, di, .)
-{
+1140 f1c0 move b A+-DXWLdxI 01:12 234fc:5
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t ea = EA_AX_DI_8();
@@ -5480,11 +4347,9 @@ M68KMAKE_OP(move, 8, di, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, ix, d)
-{
+1180 f1f8 move b . 01:14 234fc:7
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t ea = EA_AX_IX_8();
@@ -5494,11 +4359,9 @@ M68KMAKE_OP(move, 8, ix, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, ix, .)
-{
+1180 f1c0 move b A+-DXWLdxI 01:14 234fc:7
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t ea = EA_AX_IX_8();
@@ -5508,11 +4371,9 @@ M68KMAKE_OP(move, 8, ix, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, aw, d)
-{
+11c0 fff8 move b . 01:12 234fc:4
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t ea = EA_AW_8();
@@ -5522,11 +4383,9 @@ M68KMAKE_OP(move, 8, aw, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, aw, .)
-{
+11c0 ffc0 move b A+-DXWLdxI 01:12 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t ea = EA_AW_8();
@@ -5536,11 +4395,9 @@ M68KMAKE_OP(move, 8, aw, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, al, d)
-{
+13c0 fff8 move b . 01:16 234fc:6
uint32_t res = MASK_OUT_ABOVE_8(DY());
uint32_t ea = EA_AL_8();
@@ -5550,11 +4407,9 @@ M68KMAKE_OP(move, 8, al, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 8, al, .)
-{
+13c0 ffc0 move b A+-DXWLdxI 01:16 234fc:6
uint32_t res = M68KMAKE_GET_OPER_AY_8;
uint32_t ea = EA_AL_8();
@@ -5564,11 +4419,9 @@ M68KMAKE_OP(move, 8, al, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, d, d)
-{
+3000 f1f8 move w . 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_16(DY());
uint32_t* r_dst = &DX();
@@ -5578,11 +4431,9 @@ M68KMAKE_OP(move, 16, d, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, d, a)
-{
+3008 f1f8 move w . 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_16(AY());
uint32_t* r_dst = &DX();
@@ -5592,11 +4443,9 @@ M68KMAKE_OP(move, 16, d, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, d, .)
-{
+3000 f1c0 move w A+-DXWLdxI 01:4 234fc:2
uint32_t res = M68KMAKE_GET_OPER_AY_16;
uint32_t* r_dst = &DX();
@@ -5606,11 +4455,9 @@ M68KMAKE_OP(move, 16, d, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, ai, d)
-{
+3080 f1f8 move w . 01:8 234fc:4
uint32_t res = MASK_OUT_ABOVE_16(DY());
uint32_t ea = EA_AX_AI_16();
@@ -5620,11 +4467,9 @@ M68KMAKE_OP(move, 16, ai, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, ai, a)
-{
+3088 f1f8 move w . 01:8 234fc:4
uint32_t res = MASK_OUT_ABOVE_16(AY());
uint32_t ea = EA_AX_AI_16();
@@ -5634,11 +4479,9 @@ M68KMAKE_OP(move, 16, ai, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, ai, .)
-{
+3080 f1c0 move w A+-DXWLdxI 01:8 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_16;
uint32_t ea = EA_AX_AI_16();
@@ -5648,11 +4491,9 @@ M68KMAKE_OP(move, 16, ai, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, pi, d)
-{
+30c0 f1f8 move w . 01:8 234fc:4
uint32_t res = MASK_OUT_ABOVE_16(DY());
uint32_t ea = EA_AX_PI_16();
@@ -5662,11 +4503,9 @@ M68KMAKE_OP(move, 16, pi, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, pi, a)
-{
+30c8 f1f8 move w . 01:8 234fc:4
uint32_t res = MASK_OUT_ABOVE_16(AY());
uint32_t ea = EA_AX_PI_16();
@@ -5676,11 +4515,9 @@ M68KMAKE_OP(move, 16, pi, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, pi, .)
-{
+30c0 f1c0 move w A+-DXWLdxI 01:8 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_16;
uint32_t ea = EA_AX_PI_16();
@@ -5690,11 +4527,9 @@ M68KMAKE_OP(move, 16, pi, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, pd, d)
-{
+3100 f1f8 move w . 01:8 234fc:5
uint32_t res = MASK_OUT_ABOVE_16(DY());
uint32_t ea = EA_AX_PD_16();
@@ -5704,11 +4539,9 @@ M68KMAKE_OP(move, 16, pd, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, pd, a)
-{
+3108 f1f8 move w . 01:8 234fc:5
uint32_t res = MASK_OUT_ABOVE_16(AY());
uint32_t ea = EA_AX_PD_16();
@@ -5718,11 +4551,9 @@ M68KMAKE_OP(move, 16, pd, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, pd, .)
-{
+3100 f1c0 move w A+-DXWLdxI 01:8 234fc:5
uint32_t res = M68KMAKE_GET_OPER_AY_16;
uint32_t ea = EA_AX_PD_16();
@@ -5732,11 +4563,9 @@ M68KMAKE_OP(move, 16, pd, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, di, d)
-{
+3140 f1f8 move w . 01:12 234fc:5
uint32_t res = MASK_OUT_ABOVE_16(DY());
uint32_t ea = EA_AX_DI_16();
@@ -5746,11 +4575,9 @@ M68KMAKE_OP(move, 16, di, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, di, a)
-{
+3148 f1f8 move w . 01:12 234fc:5
uint32_t res = MASK_OUT_ABOVE_16(AY());
uint32_t ea = EA_AX_DI_16();
@@ -5760,11 +4587,9 @@ M68KMAKE_OP(move, 16, di, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, di, .)
-{
+3140 f1c0 move w A+-DXWLdxI 01:12 234fc:5
uint32_t res = M68KMAKE_GET_OPER_AY_16;
uint32_t ea = EA_AX_DI_16();
@@ -5774,11 +4599,9 @@ M68KMAKE_OP(move, 16, di, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, ix, d)
-{
+3180 f1f8 move w . 01:14 234fc:7
uint32_t res = MASK_OUT_ABOVE_16(DY());
uint32_t ea = EA_AX_IX_16();
@@ -5788,11 +4611,9 @@ M68KMAKE_OP(move, 16, ix, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, ix, a)
-{
+3188 f1f8 move w . 01:14 234fc:7
uint32_t res = MASK_OUT_ABOVE_16(AY());
uint32_t ea = EA_AX_IX_16();
@@ -5802,11 +4623,9 @@ M68KMAKE_OP(move, 16, ix, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, ix, .)
-{
+3180 f1c0 move w A+-DXWLdxI 01:14 234fc:7
uint32_t res = M68KMAKE_GET_OPER_AY_16;
uint32_t ea = EA_AX_IX_16();
@@ -5816,11 +4635,9 @@ M68KMAKE_OP(move, 16, ix, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, aw, d)
-{
+31c0 fff8 move w . 01:12 234fc:4
uint32_t res = MASK_OUT_ABOVE_16(DY());
uint32_t ea = EA_AW_16();
@@ -5830,11 +4647,9 @@ M68KMAKE_OP(move, 16, aw, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, aw, a)
-{
+31c8 fff8 move w . 01:12 234fc:4
uint32_t res = MASK_OUT_ABOVE_16(AY());
uint32_t ea = EA_AW_16();
@@ -5844,11 +4659,9 @@ M68KMAKE_OP(move, 16, aw, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, aw, .)
-{
+31c0 ffc0 move w A+-DXWLdxI 01:12 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_16;
uint32_t ea = EA_AW_16();
@@ -5858,11 +4671,9 @@ M68KMAKE_OP(move, 16, aw, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, al, d)
-{
+33c0 fff8 move w . 01:16 234fc:6
uint32_t res = MASK_OUT_ABOVE_16(DY());
uint32_t ea = EA_AL_16();
@@ -5872,11 +4683,9 @@ M68KMAKE_OP(move, 16, al, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, al, a)
-{
+33c8 fff8 move w . 01:16 234fc:6
uint32_t res = MASK_OUT_ABOVE_16(AY());
uint32_t ea = EA_AL_16();
@@ -5886,11 +4695,9 @@ M68KMAKE_OP(move, 16, al, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 16, al, .)
-{
+33c0 ffc0 move w A+-DXWLdxI 01:16 234fc:6
uint32_t res = M68KMAKE_GET_OPER_AY_16;
uint32_t ea = EA_AL_16();
@@ -5900,11 +4707,9 @@ M68KMAKE_OP(move, 16, al, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, d, d)
-{
+2000 f1f8 move l . 01:4 234fc:2
uint32_t res = DY();
uint32_t* r_dst = &DX();
@@ -5914,11 +4719,9 @@ M68KMAKE_OP(move, 32, d, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, d, a)
-{
+2008 f1f8 move l . 01:4 234fc:2
uint32_t res = AY();
uint32_t* r_dst = &DX();
@@ -5928,11 +4731,9 @@ M68KMAKE_OP(move, 32, d, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, d, .)
-{
+2000 f1c0 move l A+-DXWLdxI 01:4 234fc:2
uint32_t res = M68KMAKE_GET_OPER_AY_32;
uint32_t* r_dst = &DX();
@@ -5942,11 +4743,9 @@ M68KMAKE_OP(move, 32, d, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, ai, d)
-{
+2080 f1f8 move l . 01:12 234fc:4
uint32_t res = DY();
uint32_t ea = EA_AX_AI_32();
@@ -5956,11 +4755,9 @@ M68KMAKE_OP(move, 32, ai, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, ai, a)
-{
+2088 f1f8 move l . 01:12 234fc:4
uint32_t res = AY();
uint32_t ea = EA_AX_AI_32();
@@ -5970,11 +4767,9 @@ M68KMAKE_OP(move, 32, ai, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, ai, .)
-{
+2080 f1c0 move l A+-DXWLdxI 01:12 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_32;
uint32_t ea = EA_AX_AI_32();
@@ -5984,11 +4779,9 @@ M68KMAKE_OP(move, 32, ai, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, pi, d)
-{
+20c0 f1f8 move l . 01:12 234fc:4
uint32_t res = DY();
uint32_t ea = EA_AX_PI_32();
@@ -5998,11 +4791,9 @@ M68KMAKE_OP(move, 32, pi, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, pi, a)
-{
+20c8 f1f8 move l . 01:12 234fc:4
uint32_t res = AY();
uint32_t ea = EA_AX_PI_32();
@@ -6012,11 +4803,9 @@ M68KMAKE_OP(move, 32, pi, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, pi, .)
-{
+20c0 f1c0 move l A+-DXWLdxI 01:12 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_32;
uint32_t ea = EA_AX_PI_32();
@@ -6026,11 +4815,9 @@ M68KMAKE_OP(move, 32, pi, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, pd, d)
-{
+2100 f1f8 move l . 0:12 1:14 234fc:5
uint32_t res = DY();
uint32_t ea = EA_AX_PD_32();
@@ -6041,11 +4828,9 @@ M68KMAKE_OP(move, 32, pd, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, pd, a)
-{
+2108 f1f8 move l . 0:12 1:14 234fc:5
uint32_t res = AY();
uint32_t ea = EA_AX_PD_32();
@@ -6056,11 +4841,9 @@ M68KMAKE_OP(move, 32, pd, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, pd, .)
-{
+2100 f1c0 move l A+-DXWLdxI 0:12 1:14 234fc:5
uint32_t res = M68KMAKE_GET_OPER_AY_32;
uint32_t ea = EA_AX_PD_32();
@@ -6071,11 +4854,9 @@ M68KMAKE_OP(move, 32, pd, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, di, d)
-{
+2140 f1f8 move l . 01:16 234fc:5
uint32_t res = DY();
uint32_t ea = EA_AX_DI_32();
@@ -6085,11 +4866,9 @@ M68KMAKE_OP(move, 32, di, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, di, a)
-{
+2148 f1f8 move l . 01:16 234fc:5
uint32_t res = AY();
uint32_t ea = EA_AX_DI_32();
@@ -6099,11 +4878,9 @@ M68KMAKE_OP(move, 32, di, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, di, .)
-{
+2140 f1c0 move l A+-DXWLdxI 01:16 234fc:5
uint32_t res = M68KMAKE_GET_OPER_AY_32;
uint32_t ea = EA_AX_DI_32();
@@ -6113,11 +4890,9 @@ M68KMAKE_OP(move, 32, di, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, ix, d)
-{
+2180 f1f8 move l . 01:18 234fc:7
uint32_t res = DY();
uint32_t ea = EA_AX_IX_32();
@@ -6127,11 +4902,9 @@ M68KMAKE_OP(move, 32, ix, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, ix, a)
-{
+2188 f1f8 move l . 01:18 234fc:7
uint32_t res = AY();
uint32_t ea = EA_AX_IX_32();
@@ -6141,11 +4914,9 @@ M68KMAKE_OP(move, 32, ix, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, ix, .)
-{
+2180 f1c0 move l A+-DXWLdxI 01:18 234fc:7
uint32_t res = M68KMAKE_GET_OPER_AY_32;
uint32_t ea = EA_AX_IX_32();
@@ -6155,11 +4926,9 @@ M68KMAKE_OP(move, 32, ix, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, aw, d)
-{
+21c0 fff8 move l . 01:16 234fc:4
uint32_t res = DY();
uint32_t ea = EA_AW_32();
@@ -6169,11 +4938,9 @@ M68KMAKE_OP(move, 32, aw, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, aw, a)
-{
+21c8 fff8 move l . 01:16 234fc:4
uint32_t res = AY();
uint32_t ea = EA_AW_32();
@@ -6183,11 +4950,9 @@ M68KMAKE_OP(move, 32, aw, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, aw, .)
-{
+21c0 ffc0 move l A+-DXWLdxI 01:16 234fc:4
uint32_t res = M68KMAKE_GET_OPER_AY_32;
uint32_t ea = EA_AW_32();
@@ -6197,11 +4962,9 @@ M68KMAKE_OP(move, 32, aw, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, al, d)
-{
+23c0 fff8 move l . 01:20 234fc:6
uint32_t res = DY();
uint32_t ea = EA_AL_32();
@@ -6211,11 +4974,9 @@ M68KMAKE_OP(move, 32, al, d)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, al, a)
-{
+23c8 fff8 move l . 01:20 234fc:6
uint32_t res = AY();
uint32_t ea = EA_AL_32();
@@ -6225,11 +4986,9 @@ M68KMAKE_OP(move, 32, al, a)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move, 32, al, .)
-{
+23c0 ffc0 move l A+-DXWLdxI 01:20 234fc:6
uint32_t res = M68KMAKE_GET_OPER_AY_32;
uint32_t ea = EA_AL_32();
@@ -6239,92 +4998,68 @@ M68KMAKE_OP(move, 32, al, .)
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(movea, 16, ., d)
-{
+3040 f1f8 movea w . 01:4 234fc:2
AX() = MAKE_INT_16(DY());
-}
-M68KMAKE_OP(movea, 16, ., a)
-{
+3048 f1f8 movea w . 01:4 234fc:2
AX() = MAKE_INT_16(AY());
-}
-M68KMAKE_OP(movea, 16, ., .)
-{
+3040 f1c0 movea w A+-DXWLdxI 01:4 234fc:2
AX() = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
-}
-M68KMAKE_OP(movea, 32, ., d)
-{
+2040 f1f8 movea l . 01:4 234fc:2
AX() = DY();
-}
-M68KMAKE_OP(movea, 32, ., a)
-{
+2048 f1f8 movea l . 01:4 234fc:2
AX() = AY();
-}
-M68KMAKE_OP(movea, 32, ., .)
-{
+2040 f1c0 movea l A+-DXWLdxI 01:4 234fc:2
AX() = M68KMAKE_GET_OPER_AY_32;
-}
-M68KMAKE_OP(move, 16, frc, d)
-{
+42c0 fff8 move w . 1234fc:4
if(CPU_TYPE_IS_010_PLUS())
{
DY() = MASK_OUT_BELOW_16(DY()) | m68ki_get_ccr();
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(move, 16, frc, .)
-{
+42c0 ffc0 move w A+-DXWL 1:8 234fc:4
if(CPU_TYPE_IS_010_PLUS())
{
m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(move, 16, toc, d)
-{
+44c0 fff8 move w . 01:12 234fc:4
m68ki_set_ccr(DY());
-}
-M68KMAKE_OP(move, 16, toc, .)
-{
+44c0 ffc0 move w A+-DXWLdxI 01:12 234fc:4
m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
-}
-M68KMAKE_OP(move, 16, frs, d)
-{
+40c0 fff8 move w . 0:6 1:4p 234fc:8p
if(CPU_TYPE_IS_000() || CPU_TYPE_IS_070() || m_s_flag) /* NS990408 */
{
DY() = MASK_OUT_BELOW_16(DY()) | m68ki_get_sr();
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(move, 16, frs, .)
-{
+40c0 ffc0 move w A+-DXWL 0:8 1234fc:8p
if(CPU_TYPE_IS_000() || CPU_TYPE_IS_070() || m_s_flag) /* NS990408 */
{
uint32_t ea = M68KMAKE_GET_EA_AY_16;
@@ -6332,22 +5067,18 @@ M68KMAKE_OP(move, 16, frs, .)
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(move, 16, tos, d)
-{
+46c0 fff8 move w . 01:12p 234fc:8p
if(m_s_flag)
{
m68ki_set_sr(DY());
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(move, 16, tos, .)
-{
+46c0 ffc0 move w A+-DXWLdxI 01:12p 234fc:8p
if(m_s_flag)
{
uint32_t new_sr = M68KMAKE_GET_OPER_AY_16;
@@ -6356,22 +5087,18 @@ M68KMAKE_OP(move, 16, tos, .)
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(move, 32, fru, .)
-{
+4e68 fff8 move l . 0:4p 1:6p 234fc:2p
if(m_s_flag)
{
AY() = REG_USP();
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(move, 32, tou, .)
-{
+4e60 fff8 move l . 0:4p 1:6p 234fc:2p
if(m_s_flag)
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
@@ -6379,11 +5106,9 @@ M68KMAKE_OP(move, 32, tou, .)
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(movec, 32, cr, .)
-{
+4e7a ffff movec l . 1:12p 234fc:6p
if(CPU_TYPE_IS_010_PLUS())
{
if(m_s_flag)
@@ -6593,11 +5318,9 @@ M68KMAKE_OP(movec, 32, cr, .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(movec, 32, rc, .)
-{
+4e7b ffff movec l . 1:10p 234fc:12p
if(CPU_TYPE_IS_010_PLUS())
{
if(m_s_flag)
@@ -6631,7 +5354,7 @@ M68KMAKE_OP(movec, 32, rc, .)
m_cacr = REG_DA()[(word2 >> 12) & 15] & 0x0f;
}
-// logerror("movec to cacr=%04x\n", m_cacr);
+ // logerror("movec to cacr=%04x\n", m_cacr);
if (m_cacr & (M68K_CACR_CI | M68K_CACR_CEI))
{
m68ki_ic_clear();
@@ -6847,11 +5570,9 @@ M68KMAKE_OP(movec, 32, rc, .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(movem, 16, re, pd)
-{
+48a0 fff8 movem w . 01:8 234fc:4
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = AY();
@@ -6867,11 +5588,9 @@ M68KMAKE_OP(movem, 16, re, pd)
AY() = ea;
m_icount -= count<<m_cyc_movem_w;
-}
-M68KMAKE_OP(movem, 16, re, .)
-{
+4880 ffc0 movem w ADXWL 01:8 234fc:4
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = M68KMAKE_GET_EA_AY_16;
@@ -6886,11 +5605,9 @@ M68KMAKE_OP(movem, 16, re, .)
}
m_icount -= count<<m_cyc_movem_w;
-}
-M68KMAKE_OP(movem, 32, re, pd)
-{
+48e0 fff8 movem l . 01:8 234fc:4
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = AY();
@@ -6907,11 +5624,9 @@ M68KMAKE_OP(movem, 32, re, pd)
AY() = ea;
m_icount -= count<<m_cyc_movem_l;
-}
-M68KMAKE_OP(movem, 32, re, .)
-{
+48c0 ffc0 movem l ADXWL 01:8 234fc:4
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = M68KMAKE_GET_EA_AY_32;
@@ -6926,11 +5641,9 @@ M68KMAKE_OP(movem, 32, re, .)
}
m_icount -= count<<m_cyc_movem_l;
-}
-M68KMAKE_OP(movem, 16, er, pi)
-{
+4c98 fff8 movem w . 01:12 234fc:8
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = AY();
@@ -6946,11 +5659,9 @@ M68KMAKE_OP(movem, 16, er, pi)
AY() = ea;
m_icount -= count<<m_cyc_movem_w;
-}
-M68KMAKE_OP(movem, 16, er, pcdi)
-{
+4cba ffff movem w . 01:16 234fc:9
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = EA_PCDI_16();
@@ -6965,11 +5676,9 @@ M68KMAKE_OP(movem, 16, er, pcdi)
}
m_icount -= count<<m_cyc_movem_w;
-}
-M68KMAKE_OP(movem, 16, er, pcix)
-{
+4cbb ffff movem w . 01:18 234fc:11
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = EA_PCIX_16();
@@ -6984,11 +5693,9 @@ M68KMAKE_OP(movem, 16, er, pcix)
}
m_icount -= count<<m_cyc_movem_w;
-}
-M68KMAKE_OP(movem, 16, er, .)
-{
+4c80 ffc0 movem w ADXWL 01:12 234fc:8
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = M68KMAKE_GET_EA_AY_16;
@@ -7003,11 +5710,9 @@ M68KMAKE_OP(movem, 16, er, .)
}
m_icount -= count<<m_cyc_movem_w;
-}
-M68KMAKE_OP(movem, 32, er, pi)
-{
+4cd8 fff8 movem l . 01:12 234fc:8
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = AY();
@@ -7023,11 +5728,9 @@ M68KMAKE_OP(movem, 32, er, pi)
AY() = ea;
m_icount -= count<<m_cyc_movem_l;
-}
-M68KMAKE_OP(movem, 32, er, pcdi)
-{
+4cfa ffff movem l . 01:16 234fc:9
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = EA_PCDI_32();
@@ -7042,11 +5745,9 @@ M68KMAKE_OP(movem, 32, er, pcdi)
}
m_icount -= count<<m_cyc_movem_l;
-}
-M68KMAKE_OP(movem, 32, er, pcix)
-{
+4cfb ffff movem l . 01:18 234fc:11
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = EA_PCIX_32();
@@ -7061,11 +5762,9 @@ M68KMAKE_OP(movem, 32, er, pcix)
}
m_icount -= count<<m_cyc_movem_l;
-}
-M68KMAKE_OP(movem, 32, er, .)
-{
+4cc0 ffc0 movem l ADXWL 01:12 234fc:8
uint32_t i = 0;
uint32_t register_list = OPER_I_16();
uint32_t ea = M68KMAKE_GET_EA_AY_32;
@@ -7080,21 +5779,17 @@ M68KMAKE_OP(movem, 32, er, .)
}
m_icount -= count<<m_cyc_movem_l;
-}
-M68KMAKE_OP(movep, 16, re, .)
-{
+0188 f1f8 movep w . 01:16 234fc:11
uint32_t ea = EA_AY_DI_16();
uint32_t src = DX();
m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
-}
-M68KMAKE_OP(movep, 32, re, .)
-{
+01c8 f1f8 movep l . 01:24 234fc:17
uint32_t ea = EA_AY_DI_32();
uint32_t src = DX();
@@ -7102,29 +5797,23 @@ M68KMAKE_OP(movep, 32, re, .)
m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
-}
-M68KMAKE_OP(movep, 16, er, .)
-{
+0108 f1f8 movep w . 01:16 234fc:12
uint32_t ea = EA_AY_DI_16();
uint32_t* r_dst = &DX();
*r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
-}
-M68KMAKE_OP(movep, 32, er, .)
-{
+0148 f1f8 movep l . 01:24 234fc:18
uint32_t ea = EA_AY_DI_32();
DX() = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
+ (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
-}
-M68KMAKE_OP(moves, 8, ., .)
-{
+0e00 ffc0 moves b A+-DXWL 1:14p 234fc:5p
if(CPU_TYPE_IS_010_PLUS())
{
if(m_s_flag)
@@ -7155,11 +5844,9 @@ M68KMAKE_OP(moves, 8, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(moves, 16, ., .)
-{
+0e40 ffc0 moves w A+-DXWL 1:14p 234fc:5p
if(CPU_TYPE_IS_010_PLUS())
{
if(m_s_flag)
@@ -7190,11 +5877,9 @@ M68KMAKE_OP(moves, 16, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(moves, 32, ., .)
-{
+0e80 ffc0 moves l A+-DXWL 1:16p 234fc:5p
if(CPU_TYPE_IS_010_PLUS())
{
if(m_s_flag)
@@ -7220,22 +5905,18 @@ M68KMAKE_OP(moves, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(moveq, 32, ., .)
-{
+7000 f100 moveq l . 01:4 234fc:2
uint32_t res = DX() = MAKE_INT_8(MASK_OUT_ABOVE_8(m_ir));
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(move16, 32, ., .)
-{
+f620 fff8 move16 l . 4f:4 c:4p
uint16_t w2 = OPER_I_16();
int ax = m_ir & 7;
int ay = (w2 >> 12) & 7;
@@ -7246,11 +5927,9 @@ M68KMAKE_OP(move16, 32, ., .)
REG_A()[ax] += 16;
REG_A()[ay] += 16;
-}
-M68KMAKE_OP(muls, 16, ., d)
-{
+c1c0 f1f8 muls w . 0:54 1:32 234fc:27
uint32_t* r_dst = &DX();
uint32_t res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
@@ -7260,11 +5939,9 @@ M68KMAKE_OP(muls, 16, ., d)
m_n_flag = NFLAG_32(res);
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(muls, 16, ., .)
-{
+c1c0 f1c0 muls w A+-DXWLdxI 0:54 1:32 234fc:27
uint32_t* r_dst = &DX();
uint32_t res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
@@ -7274,11 +5951,9 @@ M68KMAKE_OP(muls, 16, ., .)
m_n_flag = NFLAG_32(res);
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(mulu, 16, ., d)
-{
+c0c0 f1f8 mulu w . 0:54 1:30 234fc:27
uint32_t* r_dst = &DX();
uint32_t res = MASK_OUT_ABOVE_16(DY()) * MASK_OUT_ABOVE_16(*r_dst);
@@ -7288,11 +5963,9 @@ M68KMAKE_OP(mulu, 16, ., d)
m_n_flag = NFLAG_32(res);
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(mulu, 16, ., .)
-{
+c0c0 f1c0 mulu w A+-DXWLdxI 0:54 1:30 234fc:27
uint32_t* r_dst = &DX();
uint32_t res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
@@ -7302,11 +5975,9 @@ M68KMAKE_OP(mulu, 16, ., .)
m_n_flag = NFLAG_32(res);
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(mull, 32, ., d)
-{
+4c00 fff8 mull l . 234fc:43
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -7352,11 +6023,9 @@ M68KMAKE_OP(mull, 32, ., d)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(mull, 32, ., .)
-{
+4c00 ffc0 mull l A+-DXWLdxI 234fc:43
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t word2 = OPER_I_16();
@@ -7402,11 +6071,9 @@ M68KMAKE_OP(mull, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(nbcd, 8, ., d)
-{
+4800 fff8 nbcd b . 01234fc:6
uint32_t* r_dst = &DY();
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
uint32_t res = -dst - XFLAG_1();
@@ -7435,11 +6102,9 @@ M68KMAKE_OP(nbcd, 8, ., d)
m_x_flag = XFLAG_CLEAR;
}
m_n_flag = NFLAG_8(res); /* Undefined N behavior */
-}
-M68KMAKE_OP(nbcd, 8, ., .)
-{
+4800 ffc0 nbcd b A+-DXWL 01:8 234fc:6
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t dst = m68ki_read_8(ea);
uint32_t res = -dst - XFLAG_1();
@@ -7468,11 +6133,9 @@ M68KMAKE_OP(nbcd, 8, ., .)
m_x_flag = XFLAG_CLEAR;
}
m_n_flag = NFLAG_8(res); /* Undefined N behavior */
-}
-M68KMAKE_OP(neg, 8, ., d)
-{
+4400 fff8 neg b . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t res = 0 - MASK_OUT_ABOVE_8(*r_dst);
@@ -7482,11 +6145,9 @@ M68KMAKE_OP(neg, 8, ., d)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
*r_dst = MASK_OUT_BELOW_8(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(neg, 8, ., .)
-{
+4400 ffc0 neg b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = m68ki_read_8(ea);
uint32_t res = 0 - src;
@@ -7497,11 +6158,9 @@ M68KMAKE_OP(neg, 8, ., .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
m68ki_write_8(ea, m_not_z_flag);
-}
-M68KMAKE_OP(neg, 16, ., d)
-{
+4440 fff8 neg w . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t res = 0 - MASK_OUT_ABOVE_16(*r_dst);
@@ -7511,11 +6170,9 @@ M68KMAKE_OP(neg, 16, ., d)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(neg, 16, ., .)
-{
+4440 ffc0 neg w A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = 0 - src;
@@ -7526,11 +6183,9 @@ M68KMAKE_OP(neg, 16, ., .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
m68ki_write_16(ea, m_not_z_flag);
-}
-M68KMAKE_OP(neg, 32, ., d)
-{
+4480 fff8 neg l . 01:6 234fc:2
uint32_t* r_dst = &DY();
uint32_t res = 0 - *r_dst;
@@ -7540,11 +6195,9 @@ M68KMAKE_OP(neg, 32, ., d)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(neg, 32, ., .)
-{
+4480 ffc0 neg l A+-DXWL 01:12 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t src = m68ki_read_32(ea);
uint32_t res = 0 - src;
@@ -7555,11 +6208,9 @@ M68KMAKE_OP(neg, 32, ., .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
m68ki_write_32(ea, m_not_z_flag);
-}
-M68KMAKE_OP(negx, 8, ., d)
-{
+4000 fff8 negx b . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_1();
@@ -7571,11 +6222,9 @@ M68KMAKE_OP(negx, 8, ., d)
m_not_z_flag |= res;
*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
-}
-M68KMAKE_OP(negx, 8, ., .)
-{
+4000 ffc0 negx b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = m68ki_read_8(ea);
uint32_t res = 0 - src - XFLAG_1();
@@ -7588,11 +6237,9 @@ M68KMAKE_OP(negx, 8, ., .)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(negx, 16, ., d)
-{
+4040 fff8 negx w . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_1();
@@ -7604,11 +6251,9 @@ M68KMAKE_OP(negx, 16, ., d)
m_not_z_flag |= res;
*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
-}
-M68KMAKE_OP(negx, 16, ., .)
-{
+4040 ffc0 negx w A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_1();
@@ -7621,11 +6266,9 @@ M68KMAKE_OP(negx, 16, ., .)
m_not_z_flag |= res;
m68ki_write_16(ea, res);
-}
-M68KMAKE_OP(negx, 32, ., d)
-{
+4080 fff8 negx l . 01:6 234fc:2
uint32_t* r_dst = &DY();
uint32_t res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_1();
@@ -7637,11 +6280,9 @@ M68KMAKE_OP(negx, 32, ., d)
m_not_z_flag |= res;
*r_dst = res;
-}
-M68KMAKE_OP(negx, 32, ., .)
-{
+4080 ffc0 negx l A+-DXWL 01:12 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t src = m68ki_read_32(ea);
uint32_t res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_1();
@@ -7654,17 +6295,13 @@ M68KMAKE_OP(negx, 32, ., .)
m_not_z_flag |= res;
m68ki_write_32(ea, res);
-}
-M68KMAKE_OP(nop, 0, ., .)
-{
+4e71 ffff nop . . 01:4 234fc:2
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
-}
-M68KMAKE_OP(not, 8, ., d)
-{
+4600 fff8 not b . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t res = MASK_OUT_ABOVE_8(~*r_dst);
@@ -7674,11 +6311,9 @@ M68KMAKE_OP(not, 8, ., d)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(not, 8, ., .)
-{
+4600 ffc0 not b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
@@ -7688,11 +6323,9 @@ M68KMAKE_OP(not, 8, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(not, 16, ., d)
-{
+4640 fff8 not w . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t res = MASK_OUT_ABOVE_16(~*r_dst);
@@ -7702,11 +6335,9 @@ M68KMAKE_OP(not, 16, ., d)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(not, 16, ., .)
-{
+4640 ffc0 not w A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
@@ -7716,11 +6347,9 @@ M68KMAKE_OP(not, 16, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(not, 32, ., d)
-{
+4680 fff8 not l . 01:6 234fc:2
uint32_t* r_dst = &DY();
uint32_t res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
@@ -7728,11 +6357,9 @@ M68KMAKE_OP(not, 32, ., d)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(not, 32, ., .)
-{
+4680 ffc0 not l A+-DXWL 01:12 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
@@ -7742,77 +6369,63 @@ M68KMAKE_OP(not, 32, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(or, 8, er, d)
-{
+8000 f1f8 or b . 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_8((DX() |= MASK_OUT_ABOVE_8(DY())));
m_n_flag = NFLAG_8(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(or, 8, er, .)
-{
+8000 f1c0 or b A+-DXWLdxI 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_8((DX() |= M68KMAKE_GET_OPER_AY_8));
m_n_flag = NFLAG_8(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(or, 16, er, d)
-{
+8040 f1f8 or w . 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_16((DX() |= MASK_OUT_ABOVE_16(DY())));
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(or, 16, er, .)
-{
+8040 f1c0 or w A+-DXWLdxI 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_16((DX() |= M68KMAKE_GET_OPER_AY_16));
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(or, 32, er, d)
-{
+8080 f1f8 or l . 01:6 234fc:2
uint32_t res = DX() |= DY();
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(or, 32, er, .)
-{
+8080 f1c0 or l A+-DXWLdxI 01:6 234fc:2
uint32_t res = DX() |= M68KMAKE_GET_OPER_AY_32;
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(or, 8, re, .)
-{
+8100 f1c0 or b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t res = MASK_OUT_ABOVE_8(DX() | m68ki_read_8(ea));
@@ -7822,11 +6435,9 @@ M68KMAKE_OP(or, 8, re, .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(or, 16, re, .)
-{
+8140 f1c0 or w A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t res = MASK_OUT_ABOVE_16(DX() | m68ki_read_16(ea));
@@ -7836,11 +6447,9 @@ M68KMAKE_OP(or, 16, re, .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(or, 32, re, .)
-{
+8180 f1c0 or l A+-DXWL 01:12 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t res = DX() | m68ki_read_32(ea);
@@ -7850,22 +6459,18 @@ M68KMAKE_OP(or, 32, re, .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ori, 8, ., d)
-{
+0000 fff8 ori b . 01:8 234fc:2
uint32_t res = MASK_OUT_ABOVE_8((DY() |= OPER_I_8()));
m_n_flag = NFLAG_8(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ori, 8, ., .)
-{
+0000 ffc0 ori b A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_8();
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
@@ -7876,22 +6481,18 @@ M68KMAKE_OP(ori, 8, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ori, 16, ., d)
-{
+0040 fff8 ori w . 01:8 234fc:2
uint32_t res = MASK_OUT_ABOVE_16(DY() |= OPER_I_16());
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ori, 16, ., .)
-{
+0040 ffc0 ori w A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_16();
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
@@ -7902,22 +6503,18 @@ M68KMAKE_OP(ori, 16, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ori, 32, ., d)
-{
+0080 fff8 ori l . 0:16 1:14 234fc:2
uint32_t res = DY() |= OPER_I_32();
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ori, 32, ., .)
-{
+0080 ffc0 ori l A+-DXWL 01:20 234fc:4
uint32_t src = OPER_I_32();
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t res = src | m68ki_read_32(ea);
@@ -7928,17 +6525,13 @@ M68KMAKE_OP(ori, 32, ., .)
m_not_z_flag = res;
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ori, 8, toc, .)
-{
+003c ffff ori w . 0:20 1:16 234fc:12
m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8());
-}
-M68KMAKE_OP(ori, 16, tos, .)
-{
+007c ffff ori w . 0:20p 1:16p 234fc:12p
if(m_s_flag)
{
uint32_t src = OPER_I_16();
@@ -7947,11 +6540,9 @@ M68KMAKE_OP(ori, 16, tos, .)
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(pack, 16, rr, .)
-{
+8140 f1f8 pack w . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
/* Note: DX() and DY() are reversed in Motorola's docs */
@@ -7962,11 +6553,9 @@ M68KMAKE_OP(pack, 16, rr, .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(pack, 16, mm, ax7)
-{
+8f48 fff8 pack w . 234fc:13
if(CPU_TYPE_IS_EC020_PLUS())
{
/* Note: AX and AY are reversed in Motorola's docs */
@@ -7979,11 +6568,9 @@ M68KMAKE_OP(pack, 16, mm, ax7)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(pack, 16, mm, ay7)
-{
+814f f1ff pack w . 234fc:13
if(CPU_TYPE_IS_EC020_PLUS())
{
/* Note: AX and AY are reversed in Motorola's docs */
@@ -7996,11 +6583,9 @@ M68KMAKE_OP(pack, 16, mm, ay7)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(pack, 16, mm, axy7)
-{
+8f4f ffff pack w . 234fc:13
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t ea_src = EA_A7_PD_8();
@@ -8012,11 +6597,9 @@ M68KMAKE_OP(pack, 16, mm, axy7)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(pack, 16, mm, .)
-{
+8148 f1f8 pack w . 234fc:13
if(CPU_TYPE_IS_EC020_PLUS())
{
/* Note: AX and AY are reversed in Motorola's docs */
@@ -8029,38 +6612,33 @@ M68KMAKE_OP(pack, 16, mm, .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(pea, 32, ., .)
-{
+4840 ffc0 pea l ADXWLdx 01:6 234fc:5
uint32_t ea = M68KMAKE_GET_EA_AY_32;
m68ki_push_32(ea);
-}
-M68KMAKE_OP(pflusha, 32, ., .)
-{
+
+f518 fff8 pflusha l . 4fc:4p
if ((CPU_TYPE_IS_EC020_PLUS()) && (m_has_pmmu))
{
logerror("68040: unhandled PFLUSHA (ir=%04x)\n", m_ir);
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(pflushan, 32, ., .)
-{
+
+f510 fff8 pflushan l . 4fc:4p
if ((CPU_TYPE_IS_EC020_PLUS()) && (m_has_pmmu))
{
logerror("68040: unhandled PFLUSHAN (ir=%04x)\n", m_ir);
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(pmmu, 32, ., .)
-{
+
+f000 fe00 pmmu l . 234fc:8p
if ((CPU_TYPE_IS_EC020_PLUS()) && (m_has_pmmu))
{
m68851_mmu_ops();
@@ -8069,10 +6647,9 @@ M68KMAKE_OP(pmmu, 32, ., .)
{
m68ki_exception_1111();
}
-}
-M68KMAKE_OP(ptest, 32, ., .)
-{
+
+f548 ffd8 ptest l . 4:8p
if ((CPU_TYPE_IS_040_PLUS()) && (m_has_pmmu))
{
logerror("68040: unhandled PTEST\n");
@@ -8082,10 +6659,9 @@ M68KMAKE_OP(ptest, 32, ., .)
{
m68ki_exception_1111();
}
-}
-M68KMAKE_OP(reset, 0, ., .)
-{
+
+4e70 ffff reset . . 01234fc:0p
if(m_s_flag)
{
if (!m_reset_instr_callback.isnull())
@@ -8095,11 +6671,9 @@ M68KMAKE_OP(reset, 0, ., .)
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(ror, 8, s, .)
-{
+e018 f1f8 ror b . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t orig_shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t shift = orig_shift & 7;
@@ -8115,11 +6689,9 @@ M68KMAKE_OP(ror, 8, s, .)
m_not_z_flag = res;
m_c_flag = src << (9-orig_shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ror, 16, s, .)
-{
+e058 f1f8 ror w . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -8134,11 +6706,9 @@ M68KMAKE_OP(ror, 16, s, .)
m_not_z_flag = res;
m_c_flag = src << (9-shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ror, 32, s, .)
-{
+e098 f1f8 ror l . 01234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint64_t src = *r_dst;
@@ -8153,11 +6723,9 @@ M68KMAKE_OP(ror, 32, s, .)
m_not_z_flag = res;
m_c_flag = src << (9-shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ror, 8, r, .)
-{
+e038 f1f8 ror b . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
uint32_t shift = orig_shift & 7;
@@ -8180,11 +6748,9 @@ M68KMAKE_OP(ror, 8, r, .)
m_n_flag = NFLAG_8(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ror, 16, r, .)
-{
+e078 f1f8 ror w . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
uint32_t shift = orig_shift & 15;
@@ -8207,11 +6773,9 @@ M68KMAKE_OP(ror, 16, r, .)
m_n_flag = NFLAG_16(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ror, 32, r, .)
-{
+e0b8 f1f8 ror l . 01234fc:8
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
uint32_t shift = orig_shift & 31;
@@ -8234,11 +6798,9 @@ M68KMAKE_OP(ror, 32, r, .)
m_n_flag = NFLAG_32(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(ror, 16, ., .)
-{
+e6c0 ffc0 ror w A+-DXWL 01:8 234fc:7
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = ROR_16(src, 1);
@@ -8249,11 +6811,9 @@ M68KMAKE_OP(ror, 16, ., .)
m_not_z_flag = res;
m_c_flag = src << 8;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(rol, 8, s, .)
-{
+e118 f1f8 rol b . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t orig_shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t shift = orig_shift & 7;
@@ -8269,11 +6829,9 @@ M68KMAKE_OP(rol, 8, s, .)
m_not_z_flag = res;
m_c_flag = src << orig_shift;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(rol, 16, s, .)
-{
+e158 f1f8 rol w . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -8288,11 +6846,9 @@ M68KMAKE_OP(rol, 16, s, .)
m_not_z_flag = res;
m_c_flag = src >> (8-shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(rol, 32, s, .)
-{
+e198 f1f8 rol l . 01234fc:8
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint64_t src = *r_dst;
@@ -8307,11 +6863,9 @@ M68KMAKE_OP(rol, 32, s, .)
m_not_z_flag = res;
m_c_flag = src >> (24-shift);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(rol, 8, r, .)
-{
+e138 f1f8 rol b . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
uint32_t shift = orig_shift & 7;
@@ -8342,11 +6896,9 @@ M68KMAKE_OP(rol, 8, r, .)
m_n_flag = NFLAG_8(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(rol, 16, r, .)
-{
+e178 f1f8 rol w . 01:6 234fc:8
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
uint32_t shift = orig_shift & 15;
@@ -8377,11 +6929,9 @@ M68KMAKE_OP(rol, 16, r, .)
m_n_flag = NFLAG_16(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(rol, 32, r, .)
-{
+e1b8 f1f8 rol l . 01234fc:8
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
uint32_t shift = orig_shift & 31;
@@ -8405,11 +6955,9 @@ M68KMAKE_OP(rol, 32, r, .)
m_n_flag = NFLAG_32(src);
m_not_z_flag = src;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(rol, 16, ., .)
-{
+e7c0 ffc0 rol w A+-DXWL 01:8 234fc:7
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
@@ -8420,11 +6968,9 @@ M68KMAKE_OP(rol, 16, ., .)
m_not_z_flag = res;
m_c_flag = src >> 7;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxr, 8, s, .)
-{
+e010 f1f8 roxr b . 01:6 234fc:12
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -8441,11 +6987,9 @@ M68KMAKE_OP(roxr, 8, s, .)
m_n_flag = NFLAG_8(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxr, 16, s, .)
-{
+e050 f1f8 roxr w . 01:6 234fc:12
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -8462,11 +7006,9 @@ M68KMAKE_OP(roxr, 16, s, .)
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxr, 32, s, .)
-{
+e090 f1f8 roxr l . 01:8 234fc:12
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint64_t src = *r_dst;
@@ -8485,11 +7027,9 @@ M68KMAKE_OP(roxr, 32, s, .)
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxr, 8, r, .)
-{
+e030 f1f8 roxr b . 01:6 234fc:12
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
@@ -8515,11 +7055,9 @@ M68KMAKE_OP(roxr, 8, r, .)
m_n_flag = NFLAG_8(*r_dst);
m_not_z_flag = MASK_OUT_ABOVE_8(*r_dst);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxr, 16, r, .)
-{
+e070 f1f8 roxr w . 01:6 234fc:12
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
@@ -8545,11 +7083,9 @@ M68KMAKE_OP(roxr, 16, r, .)
m_n_flag = NFLAG_16(*r_dst);
m_not_z_flag = MASK_OUT_ABOVE_16(*r_dst);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxr, 32, r, .)
-{
+e0b0 f1f8 roxr l . 01:8 234fc:12
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
@@ -8577,11 +7113,9 @@ M68KMAKE_OP(roxr, 32, r, .)
m_n_flag = NFLAG_32(*r_dst);
m_not_z_flag = *r_dst;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxr, 16, ., .)
-{
+e4c0 ffc0 roxr w A+-DXWL 01:8 234fc:5
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = ROR_17(src | (XFLAG_1() << 16), 1);
@@ -8594,11 +7128,9 @@ M68KMAKE_OP(roxr, 16, ., .)
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxl, 8, s, .)
-{
+e110 f1f8 roxl b . 01:6 234fc:12
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_8(*r_dst);
@@ -8615,11 +7147,9 @@ M68KMAKE_OP(roxl, 8, s, .)
m_n_flag = NFLAG_8(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxl, 16, s, .)
-{
+e150 f1f8 roxl w . 01:6 234fc:12
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t src = MASK_OUT_ABOVE_16(*r_dst);
@@ -8636,11 +7166,9 @@ M68KMAKE_OP(roxl, 16, s, .)
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxl, 32, s, .)
-{
+e190 f1f8 roxl l . 01:8 234fc:12
uint32_t* r_dst = &DY();
uint32_t shift = (((m_ir >> 9) - 1) & 7) + 1;
uint64_t src = *r_dst;
@@ -8659,11 +7187,9 @@ M68KMAKE_OP(roxl, 32, s, .)
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxl, 8, r, .)
-{
+e130 f1f8 roxl b . 01:6 234fc:12
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
@@ -8690,11 +7216,9 @@ M68KMAKE_OP(roxl, 8, r, .)
m_n_flag = NFLAG_8(*r_dst);
m_not_z_flag = MASK_OUT_ABOVE_8(*r_dst);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxl, 16, r, .)
-{
+e170 f1f8 roxl w . 01:6 234fc:12
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
@@ -8720,11 +7244,9 @@ M68KMAKE_OP(roxl, 16, r, .)
m_n_flag = NFLAG_16(*r_dst);
m_not_z_flag = MASK_OUT_ABOVE_16(*r_dst);
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxl, 32, r, .)
-{
+e1b0 f1f8 roxl l . 01:8 234fc:12
uint32_t* r_dst = &DY();
uint32_t orig_shift = DX() & 0x3f;
@@ -8752,11 +7274,9 @@ M68KMAKE_OP(roxl, 32, r, .)
m_n_flag = NFLAG_32(*r_dst);
m_not_z_flag = *r_dst;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(roxl, 16, ., .)
-{
+e5c0 ffc0 roxl w A+-DXWL 01:8 234fc:5
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = m68ki_read_16(ea);
uint32_t res = ROL_17(src | (XFLAG_1() << 16), 1);
@@ -8769,11 +7289,9 @@ M68KMAKE_OP(roxl, 16, ., .)
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(rtd, 32, ., .)
-{
+4e74 ffff rtd l . 1:16 234fc:10
if(CPU_TYPE_IS_010_PLUS())
{
uint32_t new_pc = m68ki_pull_32();
@@ -8784,11 +7302,9 @@ M68KMAKE_OP(rtd, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(rte, 32, ., .)
-{
+4e73 ffff rte l . 0234fc:20p 1:24p
if(m_s_flag)
{
uint32_t new_sr;
@@ -8834,7 +7350,7 @@ M68KMAKE_OP(rte, 32, ., .)
}
/* Otherwise it's 020 */
-rte_loop:
+ rte_loop:
format_word = m68ki_read_16(REG_A()[7]+6) >> 12;
switch(format_word)
{
@@ -8948,11 +7464,9 @@ rte_loop:
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(rtm, 32, ., .)
-{
+06c0 fff0 rtm l . 234fc:19
if(CPU_TYPE_IS_020_VARIANT())
{
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
@@ -8961,26 +7475,20 @@ M68KMAKE_OP(rtm, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(rtr, 32, ., .)
-{
+4e77 ffff rtr l . 01:20 234fc:14
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_set_ccr(m68ki_pull_16());
m68ki_jump(m68ki_pull_32());
-}
-M68KMAKE_OP(rts, 32, ., .)
-{
+4e75 ffff rts l . 01:16 234fc:10
m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
m68ki_jump(m68ki_pull_32());
-}
-M68KMAKE_OP(sbcd, 8, rr, .)
-{
+8100 f1f8 sbcd b . 01:6 234fc:4
uint32_t* r_dst = &DX();
uint32_t src = DY();
uint32_t dst = *r_dst;
@@ -9008,11 +7516,9 @@ M68KMAKE_OP(sbcd, 8, rr, .)
m_not_z_flag |= res;
*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
-}
-M68KMAKE_OP(sbcd, 8, mm, ax7)
-{
+8f08 fff8 sbcd b . 01:18 234fc:16
uint32_t src = OPER_AY_PD_8();
uint32_t ea = EA_A7_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -9040,11 +7546,9 @@ M68KMAKE_OP(sbcd, 8, mm, ax7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(sbcd, 8, mm, ay7)
-{
+810f f1ff sbcd b . 01:18 234fc:16
uint32_t src = OPER_A7_PD_8();
uint32_t ea = EA_AX_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -9072,11 +7576,9 @@ M68KMAKE_OP(sbcd, 8, mm, ay7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(sbcd, 8, mm, axy7)
-{
+8f0f ffff sbcd b . 01:18 234fc:16
uint32_t src = OPER_A7_PD_8();
uint32_t ea = EA_A7_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -9104,11 +7606,9 @@ M68KMAKE_OP(sbcd, 8, mm, axy7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(sbcd, 8, mm, .)
-{
+8108 f1f8 sbcd b . 01:18 234fc:16
uint32_t src = OPER_AY_PD_8();
uint32_t ea = EA_AX_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -9136,35 +7636,25 @@ M68KMAKE_OP(sbcd, 8, mm, .)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(st, 8, ., d)
-{
+50c0 fff8 st b . 0:6 1234fc:4
DY() |= 0xff;
-}
-M68KMAKE_OP(st, 8, ., .)
-{
+50c0 ffc0 st b A+-DXWL 01:8 234fc:6
m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
-}
-M68KMAKE_OP(sf, 8, ., d)
-{
+51c0 fff8 sf b . 01234fc:4
DY() &= 0xffffff00;
-}
-M68KMAKE_OP(sf, 8, ., .)
-{
+51c0 ffc0 sf b A+-DXWL 01:8 234fc:6
m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
-}
-M68KMAKE_OP(scc, 8, ., d)
-{
+50c0 f0f8 scc b . 01234fc:4
if(M68KMAKE_CC)
{
DY() |= 0xff;
@@ -9172,17 +7662,13 @@ M68KMAKE_OP(scc, 8, ., d)
return;
}
DY() &= 0xffffff00;
-}
-M68KMAKE_OP(scc, 8, ., .)
-{
+50c0 f0c0 scc b A+-DXWL 01:8 234fc:6
m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
-}
-M68KMAKE_OP(stop, 0, ., .)
-{
+4e72 ffff stop . . 01:4p 234fc:8p
if(m_s_flag)
{
uint32_t new_sr = OPER_I_16();
@@ -9193,11 +7679,9 @@ M68KMAKE_OP(stop, 0, ., .)
return;
}
m68ki_exception_privilege_violation();
-}
-M68KMAKE_OP(sub, 8, er, d)
-{
+9000 f1f8 sub b . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_8(DY());
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -9209,11 +7693,9 @@ M68KMAKE_OP(sub, 8, er, d)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
*r_dst = MASK_OUT_BELOW_8(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(sub, 8, er, .)
-{
+9000 f1c0 sub b A+-DXWLdxI 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = M68KMAKE_GET_OPER_AY_8;
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -9225,11 +7707,9 @@ M68KMAKE_OP(sub, 8, er, .)
m_not_z_flag = MASK_OUT_ABOVE_8(res);
*r_dst = MASK_OUT_BELOW_8(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(sub, 16, er, d)
-{
+9040 f1f8 sub w . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_16(DY());
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -9241,11 +7721,9 @@ M68KMAKE_OP(sub, 16, er, d)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(sub, 16, er, a)
-{
+9048 f1f8 sub w . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_16(AY());
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -9257,11 +7735,9 @@ M68KMAKE_OP(sub, 16, er, a)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(sub, 16, er, .)
-{
+9040 f1c0 sub w A+-DXWLdxI 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = M68KMAKE_GET_OPER_AY_16;
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -9273,11 +7749,9 @@ M68KMAKE_OP(sub, 16, er, .)
m_not_z_flag = MASK_OUT_ABOVE_16(res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(sub, 32, er, d)
-{
+9080 f1f8 sub l . 01:6 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = DY();
uint32_t dst = *r_dst;
@@ -9289,11 +7763,9 @@ M68KMAKE_OP(sub, 32, er, d)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(sub, 32, er, a)
-{
+9088 f1f8 sub l . 01:6 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = AY();
uint32_t dst = *r_dst;
@@ -9305,11 +7777,9 @@ M68KMAKE_OP(sub, 32, er, a)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(sub, 32, er, .)
-{
+9080 f1c0 sub l A+-DXWLdxI 01:6 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = M68KMAKE_GET_OPER_AY_32;
uint32_t dst = *r_dst;
@@ -9321,11 +7791,9 @@ M68KMAKE_OP(sub, 32, er, .)
m_not_z_flag = MASK_OUT_ABOVE_32(res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(sub, 8, re, .)
-{
+9100 f1c0 sub b A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t src = MASK_OUT_ABOVE_8(DX());
uint32_t dst = m68ki_read_8(ea);
@@ -9337,11 +7805,9 @@ M68KMAKE_OP(sub, 8, re, .)
m_v_flag = VFLAG_SUB_8(src, dst, res);
m68ki_write_8(ea, m_not_z_flag);
-}
-M68KMAKE_OP(sub, 16, re, .)
-{
+9140 f1c0 sub w A+-DXWL 01:8 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t src = MASK_OUT_ABOVE_16(DX());
uint32_t dst = m68ki_read_16(ea);
@@ -9353,11 +7819,9 @@ M68KMAKE_OP(sub, 16, re, .)
m_v_flag = VFLAG_SUB_16(src, dst, res);
m68ki_write_16(ea, m_not_z_flag);
-}
-M68KMAKE_OP(sub, 32, re, .)
-{
+9180 f1c0 sub l A+-DXWL 01:12 234fc:4
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t src = DX();
uint32_t dst = m68ki_read_32(ea);
@@ -9369,61 +7833,47 @@ M68KMAKE_OP(sub, 32, re, .)
m_v_flag = VFLAG_SUB_32(src, dst, res);
m68ki_write_32(ea, m_not_z_flag);
-}
-M68KMAKE_OP(suba, 16, ., d)
-{
+90c0 f1f8 suba w . 01:8 234fc:2
uint32_t* r_dst = &AX();
*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY()));
-}
-M68KMAKE_OP(suba, 16, ., a)
-{
+90c8 f1f8 suba w . 01:8 234fc:2
uint32_t* r_dst = &AX();
*r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY()));
-}
-M68KMAKE_OP(suba, 16, ., .)
-{
+90c0 f1c0 suba w A+-DXWLdxI 01:8 234fc:2
uint32_t* r_dst = &AX();
uint32_t src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
-}
-M68KMAKE_OP(suba, 32, ., d)
-{
+91c0 f1f8 suba l . 01:6 234fc:2
uint32_t* r_dst = &AX();
*r_dst = MASK_OUT_ABOVE_32(*r_dst - DY());
-}
-M68KMAKE_OP(suba, 32, ., a)
-{
+91c8 f1f8 suba l . 01:6 234fc:2
uint32_t* r_dst = &AX();
*r_dst = MASK_OUT_ABOVE_32(*r_dst - AY());
-}
-M68KMAKE_OP(suba, 32, ., .)
-{
+91c0 f1c0 suba l A+-DXWLdxI 01:6 234fc:2
uint32_t* r_dst = &AX();
uint32_t src = M68KMAKE_GET_OPER_AY_32;
*r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
-}
-M68KMAKE_OP(subi, 8, ., d)
-{
+0400 fff8 subi b . 01:8 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = OPER_I_8();
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -9435,11 +7885,9 @@ M68KMAKE_OP(subi, 8, ., d)
m_v_flag = VFLAG_SUB_8(src, dst, res);
*r_dst = MASK_OUT_BELOW_8(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(subi, 8, ., .)
-{
+0400 ffc0 subi b A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_8();
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t dst = m68ki_read_8(ea);
@@ -9451,11 +7899,9 @@ M68KMAKE_OP(subi, 8, ., .)
m_v_flag = VFLAG_SUB_8(src, dst, res);
m68ki_write_8(ea, m_not_z_flag);
-}
-M68KMAKE_OP(subi, 16, ., d)
-{
+0440 fff8 subi w . 01:8 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = OPER_I_16();
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -9467,11 +7913,9 @@ M68KMAKE_OP(subi, 16, ., d)
m_v_flag = VFLAG_SUB_16(src, dst, res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(subi, 16, ., .)
-{
+0440 ffc0 subi w A+-DXWL 01:12 234fc:4
uint32_t src = OPER_I_16();
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t dst = m68ki_read_16(ea);
@@ -9483,11 +7927,9 @@ M68KMAKE_OP(subi, 16, ., .)
m_v_flag = VFLAG_SUB_16(src, dst, res);
m68ki_write_16(ea, m_not_z_flag);
-}
-M68KMAKE_OP(subi, 32, ., d)
-{
+0480 fff8 subi l . 0:16 1:14 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = OPER_I_32();
uint32_t dst = *r_dst;
@@ -9499,11 +7941,9 @@ M68KMAKE_OP(subi, 32, ., d)
m_v_flag = VFLAG_SUB_32(src, dst, res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(subi, 32, ., .)
-{
+0480 ffc0 subi l A+-DXWL 01:20 234fc:4
uint32_t src = OPER_I_32();
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t dst = m68ki_read_32(ea);
@@ -9515,11 +7955,9 @@ M68KMAKE_OP(subi, 32, ., .)
m_v_flag = VFLAG_SUB_32(src, dst, res);
m68ki_write_32(ea, m_not_z_flag);
-}
-M68KMAKE_OP(subq, 8, ., d)
-{
+5100 f1f8 subq b . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -9531,11 +7969,9 @@ M68KMAKE_OP(subq, 8, ., d)
m_v_flag = VFLAG_SUB_8(src, dst, res);
*r_dst = MASK_OUT_BELOW_8(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(subq, 8, ., .)
-{
+5100 f1c0 subq b A+-DXWL 01:8 234fc:4
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t dst = m68ki_read_8(ea);
@@ -9547,11 +7983,9 @@ M68KMAKE_OP(subq, 8, ., .)
m_v_flag = VFLAG_SUB_8(src, dst, res);
m68ki_write_8(ea, m_not_z_flag);
-}
-M68KMAKE_OP(subq, 16, ., d)
-{
+5140 f1f8 subq w . 01:4 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -9563,19 +7997,15 @@ M68KMAKE_OP(subq, 16, ., d)
m_v_flag = VFLAG_SUB_16(src, dst, res);
*r_dst = MASK_OUT_BELOW_16(*r_dst) | m_not_z_flag;
-}
-M68KMAKE_OP(subq, 16, ., a)
-{
+5148 f1f8 subq w . 0:8 1:4 234fc:2
uint32_t* r_dst = &AY();
*r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((m_ir >> 9) - 1) & 7) + 1));
-}
-M68KMAKE_OP(subq, 16, ., .)
-{
+5140 f1c0 subq w A+-DXWL 01:8 234fc:4
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t ea = M68KMAKE_GET_EA_AY_16;
uint32_t dst = m68ki_read_16(ea);
@@ -9587,11 +8017,9 @@ M68KMAKE_OP(subq, 16, ., .)
m_v_flag = VFLAG_SUB_16(src, dst, res);
m68ki_write_16(ea, m_not_z_flag);
-}
-M68KMAKE_OP(subq, 32, ., d)
-{
+5180 f1f8 subq l . 01:8 234fc:2
uint32_t* r_dst = &DY();
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t dst = *r_dst;
@@ -9603,19 +8031,15 @@ M68KMAKE_OP(subq, 32, ., d)
m_v_flag = VFLAG_SUB_32(src, dst, res);
*r_dst = m_not_z_flag;
-}
-M68KMAKE_OP(subq, 32, ., a)
-{
+5188 f1f8 subq l . 01:8 234fc:2
uint32_t* r_dst = &AY();
*r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((m_ir >> 9) - 1) & 7) + 1));
-}
-M68KMAKE_OP(subq, 32, ., .)
-{
+5180 f1c0 subq l A+-DXWL 01:12 234fc:4
uint32_t src = (((m_ir >> 9) - 1) & 7) + 1;
uint32_t ea = M68KMAKE_GET_EA_AY_32;
uint32_t dst = m68ki_read_32(ea);
@@ -9627,11 +8051,9 @@ M68KMAKE_OP(subq, 32, ., .)
m_v_flag = VFLAG_SUB_32(src, dst, res);
m68ki_write_32(ea, m_not_z_flag);
-}
-M68KMAKE_OP(subx, 8, rr, .)
-{
+9100 f1f8 subx b . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_8(DY());
uint32_t dst = MASK_OUT_ABOVE_8(*r_dst);
@@ -9645,11 +8067,9 @@ M68KMAKE_OP(subx, 8, rr, .)
m_not_z_flag |= res;
*r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
-}
-M68KMAKE_OP(subx, 16, rr, .)
-{
+9140 f1f8 subx w . 01:4 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = MASK_OUT_ABOVE_16(DY());
uint32_t dst = MASK_OUT_ABOVE_16(*r_dst);
@@ -9663,11 +8083,9 @@ M68KMAKE_OP(subx, 16, rr, .)
m_not_z_flag |= res;
*r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
-}
-M68KMAKE_OP(subx, 32, rr, .)
-{
+9180 f1f8 subx l . 0:8 1:6 234fc:2
uint32_t* r_dst = &DX();
uint32_t src = DY();
uint32_t dst = *r_dst;
@@ -9681,11 +8099,9 @@ M68KMAKE_OP(subx, 32, rr, .)
m_not_z_flag |= res;
*r_dst = res;
-}
-M68KMAKE_OP(subx, 8, mm, ax7)
-{
+9f08 fff8 subx b . 01:18 234fc:12
uint32_t src = OPER_AY_PD_8();
uint32_t ea = EA_A7_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -9699,11 +8115,9 @@ M68KMAKE_OP(subx, 8, mm, ax7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(subx, 8, mm, ay7)
-{
+910f f1ff subx b . 01:18 234fc:12
uint32_t src = OPER_A7_PD_8();
uint32_t ea = EA_AX_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -9717,11 +8131,9 @@ M68KMAKE_OP(subx, 8, mm, ay7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(subx, 8, mm, axy7)
-{
+9f0f ffff subx b . 01:18 234fc:12
uint32_t src = OPER_A7_PD_8();
uint32_t ea = EA_A7_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -9735,11 +8147,9 @@ M68KMAKE_OP(subx, 8, mm, axy7)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(subx, 8, mm, .)
-{
+9108 f1f8 subx b . 01:18 234fc:12
uint32_t src = OPER_AY_PD_8();
uint32_t ea = EA_AX_PD_8();
uint32_t dst = m68ki_read_8(ea);
@@ -9753,11 +8163,9 @@ M68KMAKE_OP(subx, 8, mm, .)
m_not_z_flag |= res;
m68ki_write_8(ea, res);
-}
-M68KMAKE_OP(subx, 16, mm, .)
-{
+9148 f1f8 subx w . 01:18 234fc:12
uint32_t src = OPER_AY_PD_16();
uint32_t ea = EA_AX_PD_16();
uint32_t dst = m68ki_read_16(ea);
@@ -9771,11 +8179,9 @@ M68KMAKE_OP(subx, 16, mm, .)
m_not_z_flag |= res;
m68ki_write_16(ea, res);
-}
-M68KMAKE_OP(subx, 32, mm, .)
-{
+9188 f1f8 subx l . 01:30 234fc:12
uint32_t src = OPER_AY_PD_32();
uint32_t ea = EA_AX_PD_32();
uint32_t dst = m68ki_read_32(ea);
@@ -9789,11 +8195,9 @@ M68KMAKE_OP(subx, 32, mm, .)
m_not_z_flag |= res;
m68ki_write_32(ea, res);
-}
-M68KMAKE_OP(swap, 32, ., .)
-{
+4840 fff8 swap l . 01234fc:4
uint32_t* r_dst = &DY();
m_not_z_flag = MASK_OUT_ABOVE_32(*r_dst<<16);
@@ -9803,11 +8207,9 @@ M68KMAKE_OP(swap, 32, ., .)
m_n_flag = NFLAG_32(*r_dst);
m_c_flag = CFLAG_CLEAR;
m_v_flag = VFLAG_CLEAR;
-}
-M68KMAKE_OP(tas, 8, ., d)
-{
+4ac0 fff8 tas b . 01234fc:4
uint32_t* r_dst = &DY();
m_not_z_flag = MASK_OUT_ABOVE_8(*r_dst);
@@ -9815,11 +8217,9 @@ M68KMAKE_OP(tas, 8, ., d)
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
*r_dst |= 0x80;
-}
-M68KMAKE_OP(tas, 8, ., .)
-{
+4ac0 ffc0 tas b A+-DXWL 01:14 234fc:12
uint32_t ea = M68KMAKE_GET_EA_AY_8;
uint32_t dst = m68ki_read_8(ea);
@@ -9837,83 +8237,67 @@ M68KMAKE_OP(tas, 8, ., .)
(m_tas_write_callback)(*m_program, ea, dst | 0x80, 0xff);
else
m68ki_write_8(ea, dst | 0x80);
-}
-M68KMAKE_OP(trap, 0, ., .)
-{
+4e40 fff0 trap . . 01234fc:4
/* Trap#n stacks exception frame type 0 */
m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (m_ir & 0xf)); /* HJB 990403 */
-}
-M68KMAKE_OP(trapt, 0, ., .)
-{
+50fc ffff trapt . . 234fc:4
if(CPU_TYPE_IS_EC020_PLUS())
{
m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(trapt, 16, ., .)
-{
+50fa ffff trapt w . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(trapt, 32, ., .)
-{
+50fb ffff trapt l . 234fc:8
if(CPU_TYPE_IS_EC020_PLUS())
{
m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(trapf, 0, ., .)
-{
+51fc ffff trapf . . 234fc:4
if(CPU_TYPE_IS_EC020_PLUS())
{
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(trapf, 16, ., .)
-{
+51fa ffff trapf w . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
m_pc += 2;
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(trapf, 32, ., .)
-{
+51fb ffff trapf l . 234fc:8
if(CPU_TYPE_IS_EC020_PLUS())
{
m_pc += 4;
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(trapcc, 0, ., .)
-{
+50fc f0ff trapcc . . 234fc:4
if(CPU_TYPE_IS_EC020_PLUS())
{
if(M68KMAKE_CC)
@@ -9921,11 +8305,9 @@ M68KMAKE_OP(trapcc, 0, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(trapcc, 16, ., .)
-{
+50fa f0ff trapcc w . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
if(M68KMAKE_CC)
@@ -9937,11 +8319,9 @@ M68KMAKE_OP(trapcc, 16, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(trapcc, 32, ., .)
-{
+50fb f0ff trapcc l . 234fc:8
if(CPU_TYPE_IS_EC020_PLUS())
{
if(M68KMAKE_CC)
@@ -9953,43 +8333,35 @@ M68KMAKE_OP(trapcc, 32, ., .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(trapv, 0, ., .)
-{
+4e76 ffff trapv . . 01234fc:4
if(COND_VC())
{
return;
}
m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
-}
-M68KMAKE_OP(tst, 8, ., d)
-{
+4a00 fff8 tst b . 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_8(DY());
m_n_flag = NFLAG_8(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(tst, 8, ., .)
-{
+4a00 ffc0 tst b A+-DXWL 01:4 234fc:2
uint32_t res = M68KMAKE_GET_OPER_AY_8;
m_n_flag = NFLAG_8(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(tst, 8, ., pcdi)
-{
+4a3a ffff tst b . 234fc:7
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = OPER_PCDI_8();
@@ -10001,11 +8373,9 @@ M68KMAKE_OP(tst, 8, ., pcdi)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 8, ., pcix)
-{
+4a3b ffff tst b . 234fc:9
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = OPER_PCIX_8();
@@ -10017,11 +8387,9 @@ M68KMAKE_OP(tst, 8, ., pcix)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 8, ., i)
-{
+4a3c ffff tst b . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = OPER_I_8();
@@ -10033,22 +8401,18 @@ M68KMAKE_OP(tst, 8, ., i)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 16, ., d)
-{
+4a40 fff8 tst w . 01:4 234fc:2
uint32_t res = MASK_OUT_ABOVE_16(DY());
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(tst, 16, ., a)
-{
+4a48 fff8 tst w . 234fc:2
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = MAKE_INT_16(AY());
@@ -10060,22 +8424,18 @@ M68KMAKE_OP(tst, 16, ., a)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 16, ., .)
-{
+4a40 ffc0 tst w A+-DXWL 01:4 234fc:2
uint32_t res = M68KMAKE_GET_OPER_AY_16;
m_n_flag = NFLAG_16(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(tst, 16, ., pcdi)
-{
+4a7a ffff tst w . 234fc:7
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = OPER_PCDI_16();
@@ -10087,11 +8447,9 @@ M68KMAKE_OP(tst, 16, ., pcdi)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 16, ., pcix)
-{
+4a7b ffff tst w . 234fc:9
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = OPER_PCIX_16();
@@ -10103,11 +8461,9 @@ M68KMAKE_OP(tst, 16, ., pcix)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 16, ., i)
-{
+4a7c ffff tst w . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = OPER_I_16();
@@ -10119,22 +8475,18 @@ M68KMAKE_OP(tst, 16, ., i)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 32, ., d)
-{
+4a80 fff8 tst l . 01:4 234fc:2
uint32_t res = DY();
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(tst, 32, ., a)
-{
+4a88 fff8 tst l . 234fc:2
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = AY();
@@ -10146,22 +8498,18 @@ M68KMAKE_OP(tst, 32, ., a)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 32, ., .)
-{
+4a80 ffc0 tst l A+-DXWL 01:4 234fc:2
uint32_t res = M68KMAKE_GET_OPER_AY_32;
m_n_flag = NFLAG_32(res);
m_not_z_flag = res;
m_v_flag = VFLAG_CLEAR;
m_c_flag = CFLAG_CLEAR;
-}
-M68KMAKE_OP(tst, 32, ., pcdi)
-{
+4aba ffff tst l . 234fc:7
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = OPER_PCDI_32();
@@ -10173,11 +8521,9 @@ M68KMAKE_OP(tst, 32, ., pcdi)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 32, ., pcix)
-{
+4abb ffff tst l . 234fc:9
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = OPER_PCIX_32();
@@ -10189,11 +8535,9 @@ M68KMAKE_OP(tst, 32, ., pcix)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(tst, 32, ., i)
-{
+4abc ffff tst l . 234fc:6
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t res = OPER_I_32();
@@ -10205,26 +8549,20 @@ M68KMAKE_OP(tst, 32, ., i)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(unlk, 32, ., a7)
-{
+4e5f ffff unlk l . 01:12 234fc:6
REG_A()[7] = m68ki_read_32(REG_A()[7]);
-}
-M68KMAKE_OP(unlk, 32, ., .)
-{
+4e58 fff8 unlk l . 01:12 234fc:6
uint32_t* r_dst = &AY();
REG_A()[7] = *r_dst;
*r_dst = m68ki_pull_32();
-}
-M68KMAKE_OP(unpk, 16, rr, .)
-{
+8180 f1f8 unpk w . 234fc:8
if(CPU_TYPE_IS_EC020_PLUS())
{
/* Note: DX() and DY() are reversed in Motorola's docs */
@@ -10235,11 +8573,9 @@ M68KMAKE_OP(unpk, 16, rr, .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(unpk, 16, mm, ax7)
-{
+8f88 fff8 unpk w . 234fc:13
if(CPU_TYPE_IS_EC020_PLUS())
{
/* Note: AX and AY are reversed in Motorola's docs */
@@ -10254,11 +8590,9 @@ M68KMAKE_OP(unpk, 16, mm, ax7)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(unpk, 16, mm, ay7)
-{
+818f f1ff unpk w . 234fc:13
if(CPU_TYPE_IS_EC020_PLUS())
{
/* Note: AX and AY are reversed in Motorola's docs */
@@ -10273,11 +8607,9 @@ M68KMAKE_OP(unpk, 16, mm, ay7)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(unpk, 16, mm, axy7)
-{
+8f8f ffff unpk w . 234fc:13
if(CPU_TYPE_IS_EC020_PLUS())
{
uint32_t src = OPER_A7_PD_8();
@@ -10291,11 +8623,9 @@ M68KMAKE_OP(unpk, 16, mm, axy7)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(unpk, 16, mm, .)
-{
+8188 f1f8 unpk w . 234fc:13
if(CPU_TYPE_IS_EC020_PLUS())
{
/* Note: AX and AY are reversed in Motorola's docs */
@@ -10310,17 +8640,15 @@ M68KMAKE_OP(unpk, 16, mm, .)
return;
}
m68ki_exception_illegal();
-}
-M68KMAKE_OP(cinv, 32, ., .)
-{
+f400 ff20 cinv l . 4:16
if(CPU_TYPE_IS_040_PLUS())
{
uint16_t ir = m_ir;
uint8_t cache = (ir >> 6) & 3;
-// uint8_t scope = (ir >> 3) & 3;
-// logerror("68040 %s: pc=%08x ir=%04x cache=%d scope=%d register=%d\n", ir & 0x0020 ? "cpush" : "cinv", m_ppc, ir, cache, scope, ir & 7);
+ // uint8_t scope = (ir >> 3) & 3;
+ // logerror("68040 %s: pc=%08x ir=%04x cache=%d scope=%d register=%d\n", ir & 0x0020 ? "cpush" : "cinv", m_ppc, ir, cache, scope, ir & 7);
switch (cache)
{
case 2:
@@ -10331,10 +8659,9 @@ M68KMAKE_OP(cinv, 32, ., .)
return;
}
m68ki_exception_1111();
-}
-M68KMAKE_OP(cpush, 32, ., .)
-{
+
+f420 ff20 cpush l . 4:16
if(CPU_TYPE_IS_040_PLUS())
{
logerror("%s at %08x: called unimplemented instruction %04x (cpush)\n",
@@ -10342,5 +8669,5 @@ M68KMAKE_OP(cpush, 32, ., .)
return;
}
m68ki_exception_1111();
-}
+